JPH06132243A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain thermally stable metal silicide by releasing residual pollutant from the surface where a metal silicide layer was formed to inert gas atmosphere and performing sputter etching in inert gas ion plasma while maintaining vacuum. CONSTITUTION:Pwell 2 is formed on a p-type silicon substrate 1, a field oxide film 3 is formed, a gate oxide film 4 is formed, moreover, polysilicon is deposited and phosphorus is diffused inside the deposit. Then, a gate electrode 5 is formed, and a side wall film 6 is formed on a gate side wall. Thereafter, a source drain portion 7 is formed, Then, it is washed with a dilute hydrofluoric acid base and, after spin drying, residual pollutant 11 is released by lamp heating for one minute at 200 deg.C in Ar atmosphere. Thereafter, spatter etching is performed in Av + ion plasma without breaking vacuum, titanium 12 is vapor-deposited, and titanium silicide 13 is formed by selfconformance on a source drain 7 and the gate electrode 5 from which natural oxide film 8 was removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS semiconductor device, and more particularly to the production of metal silicide by the salicide method.

[0002]

2. Description of the Related Art As MOS type semiconductor devices have been highly integrated, the processing size of MOSFETs (MOS type field effect transistors) formed on a substrate has been reduced. When the processing dimension becomes a submicron level, the parasitic resistance of the gate electrode and the source / drain of the MOSFET has become an obstacle to speeding up the MOS integrated circuit. In order to reduce the parasitic resistance, a method (salicide method) has been developed in which a refractory metal is vapor-deposited and a low resistance metal silicide is self-aligned on the gate electrode and the source / drain by thermal reaction.

FIG. 6 shows a part of a process for manufacturing a MOSFET by the salicide method which is generally used at present, which will be described below in the order of processes.

FIG. 6A, a Pwell (well) 2 is formed on a P-type silicon substrate 1 by a normal method, and LOCOS is formed.
(Local Oxidation of Silic
on) method to form the field oxide film 3. After that, gate oxide film 4, polysilicon electrode (gate electrode)
5 is deposited and patterned. Further, after forming the gate side wall film (sidewall) 6, the source / drain portion 7 is formed.
Are formed by ion implantation and activation annealing.

Next, as shown in FIG. 6B, the gate electrode 5, the source
The natural oxide film 8 on the drain portion 7 is sputter-etched in Ar ⁺ ion plasma.

Next, the silicon substrate is transferred to another chamber to deposit a refractory metal 9 on it, and as shown in FIG. 6 (d), a thermal reaction is performed on the gate electrode 5 and the source / drain 7 as shown in FIG. 6 (c). To produce metal silicide 10. After that, an intermediate insulating film is formed, contact holes are opened, and a wiring layer is formed using aluminum or the like.

[0007]

In the manufacturing method described above, Ar for removing the natural oxide film on the metal silicide forming surface is used.
^{+ At} the time of ion sputter etching, the residual contaminants 11 on the surface of the silicon substrate may be taken into the substrate, the non-uniformity of the silicidation reaction due to the residual contaminants, and the agglomeration of the generated metal silicide due to the heat treatment. Etc., the layer resistance of the gate electrode, the source / drain portion is varied, the junction leak current is increased, the gate breakdown voltage is deteriorated, and the performance of the MOS integrated circuit is deteriorated.

The present invention prevents the above-mentioned variations in layer resistance of the gate electrode, source / drain portions, increase in junction leak current, deterioration of gate breakdown voltage, etc., and realizes stable and favorable high-speed MOS integrated circuit performance. Therefore, prior to Ar ⁺ ion sputter etching, the purpose is to remove residual contaminants on the surface of the silicon substrate, to bring about a uniform metal silicide formation reaction, and at the same time to form a thermally stable metal silicide layer. To do.

[0009]

For this purpose, the present invention releases residual contaminants on the surface forming a metal silicide layer by performing lamp heating in an inert gas atmosphere in a heating chamber. After that, the silicon substrate is sent to the etching chamber while the vacuum is maintained, and the sputter etching is performed in the inert gas ion plasma.

[0010]

As described above, according to the manufacturing method of the present invention,
Ar ⁺ which is the process of removing the natural oxide film on the surface of the metal silicide
Prior to sputter etching with ions, the surface residual contaminants were released by lamp heating to prevent residual impurities from being taken into the silicon substrate during the natural oxide film removal process, and to provide a stable metal silicide layer. Can be formed, and variations in the surface layer resistance can be suppressed.
Therefore, on the N ⁺ / P type junction, the reverse junction leakage current is reduced, and stable and high-speed MOS type integrated circuit performance can be realized.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a main part of a process for manufacturing a MOSFET by a salicide method according to a first embodiment of the present invention. The steps will be described below in order. In this example, titanium is used as the metal.

As shown in FIG. 1A, a Pwell 2 is formed on a P-type silicon substrate 1 by a conventional method as in the conventional method, and LOCOS is used.
The field oxide film 3 is formed by the method. After that, the gate oxide film 4 is formed by thermal oxidation of the silicon substrate. Further, polysilicon is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) method, and phosphorus is diffused in the polysilicon by POCl ₃ . Next, the gate electrode 5 is patterned and formed by a normal photolithography / etching process. An oxide film is deposited on the entire surface by the CVD method, and the sidewall film 6 is formed on the gate sidewall by anisotropic etching.
After that, the source / drain portion 7 is subjected to N ⁺ type ion implantation (A
s ⁺ ion, acceleration voltage 40 keV, dose 5 × 10 ¹⁵
cm ⁻² ) and activated annealing (900 ° C., 1 hour, in a nitrogen atmosphere) to form.

FIG. 1 (b) Next, after cleaning with a dilute hydrofluoric acid-based chemical solution and spin drying, by lamp heating at 200 ° C. for about 1 minute in an Ar atmosphere as an inert gas in a heating chamber. , Release residual contaminants 11.

After that, the substrate is sent to the etching chamber without breaking the vacuum, and sputter etching corresponding to an oxide film of 80 Å is performed in Ar ⁺ ion plasma, so that the gate electrode 5 and the source / drain portion 7 are formed. The native oxide film 8 is removed.

Similarly, as shown in FIG. 1D, the substrate is sent to the vapor deposition chamber without breaking the vacuum, and titanium 12 is vapor-deposited at 400 Å.

After that, as shown in FIG. 1 (e), a titanium silicide 13 is generated in a self-aligned manner on the gate electrode 5 and the source / drain 7 by a normal two-step lamp heating method. After that, although not shown, formation of an intermediate insulating film, wiring of Al or the like, formation of a final protective film, and the like are completed.

FIG. 2 shows the source / drain portions (area 20 μm × 0.6 μm) formed by the manufacturing method according to this embodiment.
3 shows the layer resistance distribution of. In the conventional method, the layer resistance is 10Ω /
□ or more accounted for 60%, and only an extremely non-uniform silicide layer was obtained, whereas according to this example, 85% showed an extremely uniform layer resistance distribution of 10 Ω / □ or less. ing. Further, FIG. 3 shows a reverse junction leakage current distribution diagram of the N ⁺ / P type junction formed by the manufacturing method according to this example (junction area 0.04 mm ² , peripheral length 24 mm, applied voltage 5 V). After all, the junction leak resistance is improved as compared with the conventional method.

FIG. 4 shows a second embodiment of the present invention, which will be described below in the order of steps.

In FIG. 4A, Pwel is formed on the P-type silicon substrate 1.
12 is formed, and the field oxide film 3 is formed by the LOCOS method. After that, the gate oxide film 4 is formed by thermal oxidation of the silicon substrate. Further, polysilicon is deposited by the LPCVD method, and phosphorus is diffused in the polysilicon by POCl ₃ . Next, the gate electrode 5 is patterned and formed by a photolithography / etching process.
An oxide film is deposited on the entire surface by the CVD method, and a sidewall film 6 is formed on the gate sidewall by anisotropic etching. Next, after cleaning with a hydrofluoric acid-based chemical solution and spin drying, residual contaminants 11 are released by lamp heating in an Ar atmosphere at 200 ° C. for about 1 minute in a heating chamber.

After that, as shown in FIG. 4 (b), the silicon substrate is sent to the etching chamber while maintaining the vacuum, and the oxide film 80Å
The reduced sputter etching is performed in Ar ⁺ ion plasma to remove the gate electrode 5 and the natural oxide film 8 in the element formation region 14.

Continuing with FIG. 4 (c), while maintaining the vacuum,
The silicon substrate is sent to the vapor deposition chamber and titanium 12
About 400Å is deposited by vapor deposition.

After that, as shown in FIG. 4 (d), the titanium silicide 13 is generated in a self-aligned manner on the gate electrode 5 and the element forming region 14 by a normal two-step lamp heating method.

4E, the source / drain portions 7 are formed in the element forming region 14 by N ⁺ type ion implantation and activation annealing. After that, although not shown, an intermediate insulating film is formed, wiring is formed using Al or the like, and a final protective film is formed.

The first and second embodiments described above are the NMOS type F
I have described the manufacturing method of ET, but all are Nwell
The same applies to the manufacturing method of the PMOS FET, if the formation and the P ⁺ type ion implantation are performed.

FIG. 5 shows a third embodiment of the present invention, which will be described below in the order of steps.

FIG. 5A: The field oxide film 3, the gate oxide film 4, the polysilicon electrode 5 are patterned, the gate side wall film 6 is formed, and the source / drain portions 7 are formed by a normal MOSFET manufacturing method. After that, the intermediate insulating film 13 is deposited by the CVD method, and the contact hole 15 is opened at a predetermined portion, and then the residual contaminant 11 is released in the heating chamber.

FIG. 5 (b) Next, the substrate is sent to an etching chamber while maintaining a vacuum, and sputter etching of oxide film 80Å conversion is performed in Ar ⁺ ion plasma.
The native oxide film 8 at the bottom of the contact hole 15 is removed.

Next, as shown in FIG. 5 (c), the silicon substrate is sent to the vapor deposition chamber while the vacuum is maintained, and titanium 12 is vapor-deposited to about 400 Å.

After that, as shown in FIG. 5 (d), the titanium silicide 13 is generated in a self-aligned manner at the bottom of the contact hole 15 by a lamp heating method at 760 ° C. for about 30 seconds, and at the same time, titanium nitride, which is a barrier metal layer, is formed on the upper layer. Object 18
Is generated.

5 (e), a wiring metal 16 such as aluminum is deposited, and a wiring layer is formed by a normal photolithography / etching process, and the final protective film 1 is formed.
7 is deposited.

In any of the embodiments described above, a uniform and stable metal silicide layer can be formed as compared with the conventional method, good contact characteristics can be obtained, and the performance of the MOS integrated circuit can be improved.

[0032]

As described above, according to the manufacturing method of the present invention, the Ar ⁺ ion which is the step of removing the natural oxide film on the surface where the metal silicide is generated (source / drain portion and the gate electrode or the contact bottom surface) is obtained. Prior to the sputter etching by the method, the surface residual contaminants were released by lamp heating to prevent residual impurities from being taken into the silicon substrate during the natural oxide film removal step, and to stabilize the metal silicide layer. It is possible to form, suppress variations in the surface layer resistance, reduce reverse junction leakage current on the N ⁺ / P type junction, and achieve stable and high-speed MOS integrated circuit performance. Becomes

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

[Fig. 2] Layer resistance distribution diagram of source / drain part

FIG. 3 is a reverse junction leakage current distribution diagram of an N ⁺ / P type junction.

FIG. 4 is a second embodiment of the present invention.

FIG. 5 is a third embodiment of the present invention.

FIG. 6 Conventional example

[Explanation of symbols]

 5 Gate Electrode 7 Source / Drain 8 Natural Oxide Film 11 Residual Contaminant 12 Titanium 13 Titanium Silicide

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/336 29/784

Claims (1)

[Claims] 1. A manufacturing method for forming a metal silicide layer on a semiconductor substrate, comprising: (a) forming a circuit element such as a gate electrode and a source / drain layer on the semiconductor substrate, and then in an inert gas atmosphere. Heating the lamp to discharge residual contaminants generated when the circuit element is formed, (b) after the step, without exposing the substrate to the atmosphere,
Then, a step of removing the natural oxide film formed at the time of forming the circuit element by sputter etching in an inert gas ion plasma, (c) subsequently, refractory metal is removed without exposing the substrate to the atmosphere. A method of manufacturing a semiconductor device, comprising the steps of depositing a metal silicide layer on the substrate and forming the metal silicide layer.