JPH06124241A - Testing circuit - Google Patents

Abstract

PURPOSE:To enable the constitution of a valuable LSI by improving the secrecy of the internal information and the processing processes of an information processor used in a semiconductor integrated circuit or the like. CONSTITUTION:By providing an EEPROM 5 and a scramble circuit 7 inside, data unreadable by a third person are outputted at the time of outputting them to the outside of the LSI for a dump system which was the main current of the conventional testing system of the LSI. At the time of a test, the test of inside ROM information or the like can be executed by the EEPROM 8 attached at the outside, etc. Thus, the LSI with the improved secrecy can be constituted, the leakage of the know-how of LSI development including software development in the future or the like can be effectively prevented and the development can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit, and particularly in a large-scale LSI, when observing the processing data of a plurality of internal processing devices from the outside, meaningless data can be output to a third party. The test circuit with confidentiality of internal data.

[0002]

2. Description of the Related Art In recent years, in semiconductor integrated circuits, the internal size of LSI has become complicated due to the increase in chip size and the increase in functions, resulting in an increase in the number of bits. As a result, the number of internal elements of LSI exceeds 1 million transistors and is about to increase. If there is even one defective portion on the LSI, the LSI basically malfunctions, but a means for detecting the defective portion has not been completely established, so various test methods have been proposed. The main method is to derive the internal state to the external output terminal and
This is a method of observing with an SI tester or the like. Therefore, observability becomes very important, and it is necessary to incorporate it at the LSI design stage.

On the other hand, the enormous amount of design man-hours and technological development know-how expended in the development of the LSI are realized on the LSI chip, and it is desired to protect the contents.
Needless to say, there are strong demands from SI developers and software developers. Behind this, due to development competition with competitors and unfair methods,
It seems that there is an illegal group that wants to know the technology and know-how realized on the LSI and put it on the market at a low development cost, so that they will compete excessively without enjoying the legitimate recovery cost of the development cost. This is because the harmful effects such as getting in are occurring.

As described above, methods such as scrambling, encryption, passwords, etc., with enhanced confidentiality have been proposed to avoid conflicting matters. These have both internal observability and confidentiality performance, and further development is expected in the future.

The above description will be described with reference to the drawings. The idea of placing importance on observability is an unavoidable matter when considering a test method for detecting a defective portion on an LSI. However, the increase in the number of LSI elements exponentially increases the test time, and each semiconductor maker is currently devoting considerable human resources to reducing the test time.

Then, the block diagram shown in FIG. 6 was conceived. In FIG. 6, this is a method for sweeping out the contents of the internal information processing device 34 to the outside. The external test terminal 33 directly outputs the output data 43 of an arbitrary portion of the internal information processing device 34 to the external terminal 63 as it is, and observes its state. The ROM dump method and the like fall into these categories. The feature of this method is that its function is relatively simple and its observability is excellent. However, while the observability is good,
It also has a weak point that a processing result of the internal information processing device 34 can be easily used by a third party.

In the password system, as long as a password decoding circuit is provided on the LSI chip, it is actually relatively easy to decrypt. Particularly when programmed software is installed in an LSI, the confidentiality of a ROM (Read Only Memory), which is the storage location of the software, is very important. In addition, probing technology for directly reading electrical signals on semiconductor integrated circuits has made rapid progress, and both non-contact and contact types are widely available on the market, and competition between the development side and illegal groups continues. It can be seen as if it is present.

[0008]

The above-mentioned conventional test circuit has good observability to the outside, but has a drawback that information inside the LSI can be easily used by a third party. It is strongly desired to realize an LSI having a high degree of confidentiality by converting this point into internal data and improving the confidentiality of the LSI so that the data is not easily diverted to a third party.

It is an object of the present invention to provide a test circuit which solves the above-mentioned drawbacks, is easy to test, and at the same time has improved confidentiality.

[0010]

A test circuit according to the present invention comprises a semiconductor integrated circuit having first and second storage means and first and second data / address input / output terminals. It is characterized in that a scramble circuit for converting information to data and outputting it to the outside is provided.

[0011]

1 is a block diagram showing a test circuit according to a first embodiment of the present invention. In FIG. 1, the test circuit according to the first embodiment of the present invention is arranged on the circuit of the semiconductor integrated circuit 1.
Control circuit 2, address generator 3, EEPROM 5, RO
M6, scramble circuit 7 and external EEPROM
There is 8. The semiconductor integrated circuit 1 controls and operates through the control circuit 2 in accordance with various commands and data contained in the internal ROM 6 to control the entire operation of the semiconductor integrated circuit 1.

Here, the EEPROM is an electric
c Erasable Programmable Re
Abbreviation for ad Only Memory. The terminals include a test terminal 4, a control signal 16 terminal, and a data / address input 17 terminal. In the control circuit 2,
There is a test circuit body 20. The scramble circuit 7 is E
EPROM 5 output 13, ROM 6 output 12, EEP
An output 19 of a ROM (ROM) 8 is received, and an output 11 to various control circuits and an external output 10 are output.

In this embodiment, in a test circuit on a semiconductor integrated circuit, a plurality of information processing devices are internally provided, a plurality of external control terminals and a plurality of ROMs (Read Only Memories).
y), a plurality of EEPROMs (Electric Era)
save Programmable Read On
It is a test circuit that includes a LY memory), a plurality of data / address input / output terminals, and a scramble circuit, and can convert a plurality of internal information into data by the scramble circuit and output the data to the outside.

Here, the confidentiality of the ROM code will be described as in the conventional example. Here, a scramble circuit 7 is provided so that the contents of the ROM 6 cannot be directly read by a third party. The contents of the ROM 6 become normal data after passing through the scramble circuit 7. Therefore, if this scrambling is not performed correctly, the control signal is not correctly supplied to the various control circuits. EEPRO controls this scramble circuit 7.
It is M5. The reason for setting the EEPROM 5 is that writing data cannot be read by directly observing the chip surface by an optical method. For a normal ROM,
There are diffusion switching, aluminum switching, contact switching, etc. By observing the chip surface with a microscope, the written data contents can be read relatively easily.

Further, in the EEPROM 5, even if the data written in the ROM cell is read by the laser probing method which is said to be the most advanced technology, the bit line is different from a normal transistor and the voltage rises and falls in the vicinity of the threshold of the transistor. However, the ON / OFF switching frequency of the laser on the power supply terminal cannot be detected efficiently. In the case of a RAM or the like, this laser probing is possible and is read out to the outside.

In the test mode, the contents of the internal ROM 6 are scrambled by the EEPROM 8 and observed through the external terminals. Here, the instruction code and the like cannot be correctly observed unless the EEPROM 8 is correctly input.

Generally, if the semiconductor integrated circuit production side and the user entrusting it are the data common to each other, that is, in this case, if the contents contained in the EEPROM 5 and the EEPROM 8 are the same, the judgment of verification etc. is correct, and the LSI It will be done on the production side and the user side. As a matter of course,
The contents of the ROM 6 may be scrambled.
Because the operation of the scramble circuit 7 is known to the LSI developer and the entrusted user, it can be considered in advance. The above is the description of the operation.

The detailed operation of the semiconductor integrated circuit 1 is as follows.
It looks like this: The control circuit 2 is the semiconductor integrated circuit 1
Is controlled by a plurality of control signals 16. At the same time, addresses, data, etc. from the outside are input from the signal line 17, and are used for writing into the EEPROM 5 and control and calculation in the control circuit 2. The address generator 3, which is a kind of control circuit, is composed of EEPROM5, ROM6,
It is also possible to connect to the external EEPROM 8 through the output terminal 18. Of course, the output may be open.

The output 12 of the ROM 6 and the output 13 of the EEPROM 5 are input to the scramble circuit 7, and a control signal 9 is used to determine whether the output 13 or the output 19 controls the scramble circuit 7. The output 11 of the scramble circuit 7 is also supplied to various internal control circuits. Further, the control circuit output 9 serves as an external output 10 which is also used for verification of the ROM 6. The test terminal 4 is input to the internal test circuit 20. This is a part of the control circuit 2 and controls the test mode.

FIG. 3 is a detailed block diagram of the scramble circuit 7 used in FIG. In FIG. 3, outputs a, b, and c are scrambled and output with respect to inputs A, B, and C.
The control signals are S10 to S12, S20 to S22,
S30 to S32, which is the EEPROM of FIGS.
This corresponds to the decoded output 13. X10 to X1
2, X20 to X22 and X30 to X32 correspond to the switching elements of the scramble circuit 7, respectively. In the general operation, the inputs A, B and C are switched by the control signal Sxx and converted into outputs a, b and c.

FIG. 4 is a diagram showing a truth table of control signal generation for controlling the scramble circuit 7 used in FIG. 1 and the logic of the conversion method. In FIG. 4, the code is E
EPROM output 13, in this case 3 bits (bi
t). The code is decoded, but this method is also possible with the ROM method, the PLA method, and the wired logic using a random circuit. Of the control signals, each of the S1x, S2x, and S3x groups has 3-bit information and is exclusively output. The decoding method shown in this table is an example, and other decoding logic that can be realized can be easily inferred from FIG. Input I, B,
With respect to C, a, b, and c indicate before conversion and after conversion, respectively. That is, this is referred to as scrambled.

Explaining in detail, the input {A, B,
It is assumed that {XYZ} is input to each of C} and {011} is applied to the code (here, EEPROM output). In this case, the control signals S10 to S12,
S20 to S22 and S30 to S32 are {01
It can be seen from FIG. 4 that 1}, {001}, and {100} are obtained. Therefore, the elements X10 to X12, X20 to X2
2, X30 to X32 are respectively (off, on, of
f}, {off, off, on}, {on, off, o
ff}. In other words, input {A} to {X} are input, and {X10, X11, X12} are respectively {off,
Since it is on, off}, it is output to b through X11. The other input BCs are converted in the same manner, and eventually the output {ab
The converted {XYZ} is output to c}. As described above, the scrambling operation is performed through the conversion process.

FIG. 5 is a block diagram showing an example of this concrete circuit, and is an example in which the switching element is realized by using the clocked buffer 50. This is 3 bits
Is considered as one unit, but 4bi
It is possible to have t or more, and it is also possible to have a 2-bit configuration. Further, the element can be other than the clocked buffer, and can be a transfer configuration or a wired logic configuration.

According to the present embodiment, when the information of the information processing device inside the LSI is to be observed externally, the information is not simply output to the outside, but is output once through the conversion process so that a third party directly observes the information. You can do that, but the observed data will be meaningless. However, with this method, the LSI development side,
The user who outsources the LSI development also needs the same decoder for decoding the data output to the outside. Also, a similar decoder is required inside the semiconductor integrated circuit.

FIG. 2 is a block diagram showing a test circuit according to the second embodiment of the present invention. 2, in the present embodiment, a DRAM 105 is applied instead of the EEPROM 5 of FIG. Other parts are the same as in FIG. this is,
Unlike the EEPROM, when the power is off, all scramble control data contained therein is lost. In a sense, the semiconductor integrated circuit 1 has extremely high confidentiality. However, the DR
The contents of AM 105 must be written. As a method for this, backup from a main host computer, data transfer through a public line, or the like can be considered, but in any case, the confidentiality after turning off the power is excellent.

[0026]

As described above, according to the present invention, there is an effect that an internal processing information of a semiconductor integrated circuit cannot be easily known to a third party and a highly confidential LSI can be supplied. ROMs on semiconductor integrated circuits are all EEPROM
However, it is possible, and it is decided by the LSI development side and the user who outsources the production, and it is an element determined by the balance between cost and supply and demand.

Further, considering that the technology for highly utilizing public lines will be developed in the future, the LS can be arbitrarily changed as in the present invention.
It is necessary to be able to process the data storage section on I at any time, and the concept of fixing it on the LSI must be said to be old. If this idea is used, it is possible to regularly update the data storage unit and irregularly update the data storage unit, and it is possible to supply an LSI or the like having higher confidentiality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a test circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a test circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a scramble circuit used in FIG.

FIG. 4 is a diagram showing a truth table of a scramble circuit used in FIG. 1 and a logic of a conversion method.

5 is a block diagram showing a specific example of a scramble circuit used in FIG.

FIG. 6 is a block diagram showing a conventional test circuit.

[Explanation of symbols]

 1 semiconductor integrated circuit 2 control circuit 3 address generator 4.33 test terminal 5,8 EEPROM 6 ROM 7 scramble circuit 9, 11 to 15, 18, 19 output 10 external output 16 control signal 17 data address input 20 test circuit main body 105 DRAM 34 Information processing device 43 Output data 66 Output terminal

Claims (2)

[Claims] 1. A scramble circuit which is provided with first and second storage means and first and second data / address input / output terminals on a semiconductor integrated circuit, and which converts internal information to data and outputs the data to the outside. A test circuit characterized by being provided. 2. The first storage means is a read only memory, and the second storage means is an electrically erasable programmable read only memory or a random access memory. Test circuit described.