JPH0612153A - Programmable controller - Google Patents

Abstract

PURPOSE:To provide the programmable controller which can hold the contents of a memory for arithmetic without backing up the controller by a battery at the time of a power source disconnection. CONSTITUTION:If an input voltage drops below a monitor voltage at the time of the power source disconnection, a power failure predicting circuit 6 supplies a power failure prediction signal S1 to a CPU 1. The CPU 1 performs interrupting operation with this power failure prediction signal S1 and writes the data from the RAM 3 for arithmetic in a stand-by EEPROM 5. The power failure predicting circuit 6 supplies the CPU 1 with a reset signal S2 a delay time after the generation of the power failure prediction signal S1 to reset the CPU 1. The CPU 1 after being initialized transfers the data held in the stand-by EEPROM 5 to the RAM 3 for arithmetic to reproduce the data in the RAM 3 for arithmetic before the power source disconnection.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a programmable controller.

[0002]

2. Description of the Related Art A conventional programmable controller is R
The contents of the arithmetic memory made up of AM have been backed up and held by using a battery when the power is turned off.

[0003]

However, in the battery backup as described above, it is necessary for the user to pay attention to the loss of the contents of the memory due to the battery exhaustion and to perform the battery maintenance regularly. The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable controller capable of holding the contents of an arithmetic memory without backing up by a battery when power is turned off. .

[0004]

In order to achieve the above-mentioned object, the present invention provides a system memory storing a system program of a programmable controller, an operation memory, a program storage memory, and an operation memory. Equipped with an evacuation memory consisting of an EEPROM for saving contents, a power failure notice signal is generated to the CPU for arithmetic processing of the programmable controller when the power is cut off, and reset after the power failure notice signal is generated. The CPU is provided with a power failure notice means for setting a delay time of a predetermined time width before outputting a signal, and the CPU has a power failure backup function for writing the contents of the arithmetic memory to the save memory in response to the power failure warning signal. , When the power is restored, the contents of the arithmetic memory written in the save memory are transferred to the arithmetic memory. It is those which gave a return function to be.

[0005]

According to the structure of the present invention, when there is a power failure warning signal from the power failure warning means when the power is cut off, the contents of the calculation memory are automatically adjusted by the power failure backup function of the CPU for the arithmetic processing of the programmable controller. EEPROM
Can save the contents of the calculation memory without backing up with a battery, and when the power is restored, the CPU recovery function automatically calculates the contents of the save memory. Since the data is transferred to the memory for use, the user does not need to be aware of the transfer.

[0006]

EXAMPLES The present invention will be described below with reference to examples. Figure 1
FIG. 1 is a basic block diagram of a programmable controller (hereinafter abbreviated as PC) using the present invention, in which a memory connected to a CPU 1 for performing arithmetic processing of the PC through a bus is a ROM 2 which is a system memory storing a system program; RAM3 which is a memory for calculation, EEPROM4 which is a memory for storing a program which stores a user program, and EEPROM which is a memory for saving the contents of the RAM3 for calculation when the power is turned off.
There is 5.

Then, a power cut is detected to detect the power failure notice signal S.
A power failure notice circuit 6 which gives ₁ to the CPU 1 and resets the CPU 1 after a certain delay time from the detection of power cut
Is connected to the CPU 1. Figure 2 shows this power failure notice circuit 6
The power failure notifying circuit 6 monitors the input voltage V of the stabilized power supply unit 9 that supplies the DC voltage Vcc to the CPU 1, detects the power failure, and outputs a power failure notifying signal. A delay circuit 8 for giving a reset signal to the CPU 1 after a delay time of a fixed time from the generation of the power failure detection signal S ₁ is provided.

Next, the operation of the power failure notice circuit 6 will be described with reference to the flowchart of FIG. 3 and the time chart of FIG.
In FIG. 2, the power supply monitoring circuit 7 detects whether or not the input voltage V is lower than the monitoring voltage L, and if the input voltage V is lower than that, gives a power failure notice signal S ₁ to the CPU 1 as an interrupt signal, and after that, when a delay time T elapses. The reset signal S ₂ is turned on and applied to the CPU 1 to reset the CPU 1.

That is, as shown in FIG. 4, when the input voltage V of, for example, 24 V drops below the monitoring voltage L at time t ₁ due to power-off, the power failure notice signal S ₁ falls, and the delay time T is delayed. The reset signal S ₂ falls. Here, the delay time T is devised so as to be longer than the time required to write the data of the calculation RAM 3 to the saving EEPROM 5.

FIG. 5 shows an evacuation EEPROM 5 according to a power failure notice signal S ₁ connected to an interrupt terminal INT of the CPU 1.
Shows a flowchart of the interrupt operation of the CPU 1 for saving the data of the calculation RAM 3, and when the power is cut off, the interruption by the power failure notice signal S ₁ of the power failure notice circuit 6
The CPU 1 writes the data in the calculation RAM 3 into the saving EEPROM 5 by using the discharge of the capacitor of the stabilized power supply unit 9 as a power supply. Therefore, the data is retained even when the power is turned off.

FIG. 6 shows a flow chart of the CPU 1 after the power is restored. When the power is restored, the CPU 1 initializes the data and then stores the data in the arithmetic RAM 3 held in the EEPROM 5 when the power is turned off.
Since it returns to 3, the data held at the time of power failure can be used for the operation as a PC such as the execution operation and the tool service at the time of the operation after the power is restored.

[0012]

According to the present invention, a system memory storing a system program of a programmable controller,
An arithmetic memory, a program storage memory, and an evacuation memory that is an EEPROM for saving the contents of the arithmetic memory are provided, and the CPU for arithmetic processing of the programmable controller is detected when the power is cut off. A power failure warning signal for generating a power failure warning signal, and setting a delay time of a predetermined time width after the power failure warning signal is output until the reset signal is output. When the power is turned off, the power failure backup function that writes the contents in the save memory to the save memory and the return function that transfers the contents of the calculation memory written in the save memory to the calculation memory when the power is restored are provided. When there is a power failure warning signal from the power failure warning means, the CPU's power failure backup function automatically operates the calculation memory. The contents can be written in the save memory composed of the EEPROM, so that the contents of the operation memory can be retained without backing up with a battery, and when the power is restored, the save function of the save memory is automatically saved by the CPU return function. Since the contents are transferred to the calculation memory, the user does not need to be particularly aware of the transfer, and since the battery is not used, maintenance of the battery is unnecessary and maintenance work can be simplified.
In addition, the hardware configuration of the programmable controller does not need to display a dead battery notice, and the structure can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a basic block diagram of a programmable controller using an embodiment of the present invention.

FIG. 2 is a detailed circuit configuration diagram of the power failure notice circuit of the above.

FIG. 3 is a flowchart for explaining the operation of the power failure notice circuit of the above.

FIG. 4 is a time chart for explaining the above operation.

FIG. 5 is a flowchart for explaining the operation at the time of the backup operation of the above.

FIG. 6 is a flowchart for explaining an operation when the power source is restored in the above.

[Explanation of symbols]

1 CPU 2 System ROM 3 Calculation RAM 4 User program EEPROM 5 Evacuation EEPROM 6 Power failure warning circuit S ₁ Power failure warning signal S ₂ Reset signal

Claims (1)

[Claims] 1. A power supply comprising: a system memory for storing a system program of a programmable controller; an operation memory; a program storage memory; and a save memory composed of an EEPROM for saving the contents of the operation memory. When a disconnection is detected, a power failure warning signal is generated to the CPU for arithmetic processing of the programmable controller when the power is cut off, and a delay time of a predetermined time width is set after the power failure warning signal is output until the reset signal is output. Means for storing the contents of the operation memory in the save memory in response to the power failure notice signal, and a power failure backup function for writing the contents of the operation memory to the save memory; A programmable device characterized by having a return function for transferring the contents to the arithmetic memory. Controller.