JPH06118930A - Device and system for display control - Google Patents

Abstract

PURPOSE:To provide the display controller which displays display information in a display area of different size from a display area that a display device has. CONSTITUTION:A timing signal control circuit 7 automatically detects a case wherein the display area of the display information is different from that of the display device 5 and generates a timing signal indicating the display area that the display device 5 has, and then the display information of different size from the display area that the display device 5 has is automatically displayed at an optional position in the display area that the display device 5 has. Consequently, the display information in the display area of different size from the display area that the display device has can automatically be displayed at the optional position in the display area that the display device has.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying display information by a timing signal indicating a display region, and a display device for displaying the display information in a display region having a size different from that of the display device. Involved in the scheme.

[0002]

2. Description of the Related Art In a conventional display device, a display area of display information to be displayed on the display device and a display area of the display device are shown by one timing signal, and the display information is displayed in the display area of the display device. Prior art (JP-A-60-25039)
6) will be described with reference to the drawings.

FIG. 4 is a schematic view showing an example of a conventional display device. Reference numeral 1 is a refresh memory for storing characters, figures and the like as display information, and 2 is display information for output to the display device on the refresh memory 1. Stored address,
A clock signal 202 for synchronizing display information and the like, a horizontal synchronizing signal 203 of display information, a vertical synchronizing signal 204, and a display area of the display information to be displayed on the display device at the same timing as the address to the refresh memory and a display of the display device. It is a display control circuit that generates a first timing signal 205 indicating a region. Reference numeral 4 denotes a display information generation circuit for masking the non-display area of the display information obtained in the refresh memory 1 by the first timing signal 205 and generating display information of the display device 5. Reference numeral 5 denotes synchronization of display information, display information and the like. A clock signal 202, a horizontal synchronization signal 203 of display information,
Vertical sync signal 204 and first timing signal 205
Is a display device that captures and displays. Reference numeral 6 denotes a CPU (central processing unit) that writes display information in the refresh memory 1 and controls the display control circuit 2.

Display information is stored in an address on the refresh memory 1 designated by the CPU 6 on the address bus 101 through the data bus 102. In the display control circuit 2, the control signal 601 from the CPU 6 causes the clock signal 202 for synchronizing the address indicating the display information on the refresh memory 1, the display information, and the horizontal synchronizing signal 20.
3. The vertical synchronization signal 204 and the first timing signal 205 indicating the display area of the display information to be displayed on the display device 5 and the display area of the display device 5 are generated at the same timing as the address to the refresh memory. Display control circuit 2
The address on the refresh memory 1 generated in step 1 is output to the address bus 201.
Specify the address on the refresh memory 1 through
The display information is output to the display data bus 103. The display information generation circuit 4 displays the display information from the display data bus 103 on the display device 5 by masking the non-display area of the display information with the first timing signal 205 generated by the display control circuit 2. Display information is generated and output to the display data bus 401. In the display device 5, the display information from the display data bus 401 is displayed on the display control circuit 2.
Clock signal 20 for synchronizing display information and the like generated in
2. By synchronizing with the horizontal synchronizing signal 203, the vertical synchronizing signal 204, and the first timing signal 205, the display information is displayed in the display area of the display device 5.

A timing chart of the above operation is shown in FIG. In this timing chart, the non-display area of the display information of the data bus 103 is masked by the first timing signal 205, the masked display information is output to the data bus 401, and the display information of the data bus 401 is the first
It is shown that the image is displayed in the display area of the display device by synchronizing with the timing signal 205.

[0006]

However, the above-mentioned prior art has the following problems when displaying a display area having a size different from the display area of the display device.

When the display information in the display area having a size different from the display area of the display device is displayed only by the timing signal indicating the display area of the display information, the display information is biased to the upper left of the display area of the display device. The balance of the display information displayed on the screen of the display device becomes poor.

Therefore, an object of the present invention is to display display information of a display area having a size different from that of the display area of the display device, and display the display area of a size different from that of the display area of the display device. Another object of the present invention is to provide a display control device capable of automatically displaying the display information of (1) on any place of the display area of the display device.

[0009]

In order to achieve the above object, the display control apparatus of the present invention automatically detects a case where the display area of the display information is different from that of the display apparatus, and when the display area is different, , Two timing signals, a first timing signal indicating the display area of the display information and a second timing signal indicating the display area of the display device, are generated, and a display area of a size different from the display area of the display device is generated. This can be realized by providing a means for automatically displaying the display information at an arbitrary position in the display area of the display device.

[0010]

From the first timing signal indicating the display area of the display information generated by the display control circuit and the second timing signal indicating the display area of the display device generated by the timing signal control circuit, the display apparatus and the display information are displayed. Detects different display areas. When the display area of the display information is different from that of the display device, the non-display area of the display information from the refresh memory is masked by the first timing signal indicating the display area of the display information at the same timing as the address to the refresh memory. However, display information to be displayed at an arbitrary position in the display area of the display device is generated, and the generated display information and the second timing signal indicating the display area of the display device make the display information different from the display area of the display device. The display information of the size is automatically displayed at an arbitrary place in the display area of the display device.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The refresh memory 1, the display control circuit 2, the display information generation circuit 4, the display device 5, and the CPU 6 have the same functions as those of the above-mentioned conventional technique.
Reference numeral 7 denotes a clock signal 202 for synchronizing detection and display information when the display area of the display information is different from that of the display device 5.
It is a timing signal control circuit that generates a second timing signal indicating a display area of the display device 5 from the horizontal synchronization signal 203 and the vertical synchronization signal 204.

The display information is stored by the CPU 6 through the data bus 102 at the address on the refresh memory 1 designated by the address bus 101. In the display control circuit 2, the control signal 601 from the CPU 6 causes the clock signal 202 for synchronizing the address indicating the display information on the refresh memory 1, the display information, and the horizontal synchronizing signal 20.
3. The vertical synchronization signal 204 and the first timing signal 205 indicating the display area of the display information are generated at the same timing as the address to the refresh memory 1. The address generated by the display control circuit 2 specifies the address on the refresh memory 1 through the address bus 201 and outputs the display information to the display data bus 103. The display information of the data bus 103 is input to the display information generation circuit 4,
First timing signal 20 generated by display control circuit 2
The non-display area is masked by 5, and the display information to be displayed on the display device 5 is output to the display data bus 401.

The timing signal control circuit 7 synchronizes the display information generated by the display control circuit 2 with a clock signal 202, a horizontal synchronization signal 203, and a vertical synchronization signal 204.
Thus, a second timing signal indicating the display area of the display device 5 is generated. Further, in order to detect a case where the display area of the display device 5 is different from the display area of the display information, the display areas indicated by the first timing signal 205 and the second timing signal are compared. When the display area of the display information is different from that of the display device 5, the second timing signal is output to the timing signal 701. When the display area of the display information matches the display area of the display information, the second timing signal from the display control circuit 2 is output. The timing signal 205 of 1 is the timing signal 701 as it is.
Is output to.

The display information of the display data bus 401 is input to the display device 5 and is synchronized with the clock signal 202, the horizontal synchronizing signal 203, the vertical synchronizing signal 204, and the timing signal 701 output from the timing signal control circuit 7. Thus, when the display area of the display device 5 is different from that of the display device 5, the display information of the display area having a size different from the display area of the display device 5 is automatically displayed at an arbitrary position of the display area of the display device 5. To display.

FIG. 2 is a timing chart showing the operation of FIG. 1 when the display area of the display device 5 is different from that of the display device 5. The display information of the data bus 103 is output to the data bus 401 with the non-display area masked by the first timing signal 205. Regarding the display information of the data bus 401, the timing signal 701 output from the timing signal control circuit 7 is the second timing signal indicating the display area of the display device. By synchronizing with this signal 701, the display information is displayed in the center of the display area of the display device 5.

FIG. 3 is a timing chart showing the operation of FIG. 1 when the display area of the display device 5 and the display area of the display information coincide with each other. The timing signal 701 output from the timing signal control circuit 7 is the first timing signal 205.
Is. As described above, the display area of the display information can always be displayed in the center of the display area of the display device by automatically detecting the case where the display area of the display device 5 is different from the display area of the display information.

Next, an embodiment of the timing signal control circuit 7 of FIG. 1 is shown in FIG. The circuits 71a and 71b are differentiating circuits, and their operation will be described with reference to the timing chart of FIG. The horizontal synchronizing signal 203 of the display information and the vertical synchronizing signal 204 of the display information are synchronized with the clock signal 202 for synchronizing the display information and the like, and a horizontal pulse signal 711 and a vertical pulse signal 712 are output.

A circuit 72 of FIG. 6 is an x-bit counter circuit (x is an arbitrary number), counts the clock signal 202 by the pulse signal 711, and outputs a count signal 721 indicating a horizontal display position. The circuit 73 is a y-bit counter circuit (y is an arbitrary number), counts the pulse signal 711 with the pulse signal 712, and outputs a count signal 731 indicating a display position in the vertical direction. The operation of the counter circuits 72 and 73 will be described with reference to the timing chart of FIG. When the horizontal pulse signal 711 is input, counting of the clock signal 202 is started, and the x-bit count signal 721 is output. Again pulse signal 711
When is input, the count signal 721 is reset once, the counting of the clock signal 202 is started again, and the x-bit count signal 721 is output. Similarly, the vertical pulse signal 712 causes the horizontal pulse signal 71
1 is counted, and a y-bit count signal 731 is output.

Reference numeral 74 in FIG. 6 denotes a register circuit which stores information indicating the position of the display area of the display device 5.
Then, the signal indicating the start point of the horizontal display area is 741, the signal indicating the end point is 742, the signal indicating the start point of the vertical display area is 743, and the signal indicating the end point is 744. 75
a, 75b, 75c, and 75d are a signal 741, a signal 71, which indicates the count signal 721 from the counter circuit 72, the count signal 731 from the counter circuit 73, and the horizontal and vertical end points (start point and end point) from the register circuit 74.
42, the signal 743 and the signal 744 are compared, and when the count signal 721 and the signal 741 are equal, the signal 751 indicating the starting point of the horizontal display area is output, and the count signal 721 and the signal 742 are equal. When the count signal 731 and the signal 743 are equal, the signal 752 indicating the end point of the horizontal display area is output, and the signal 753 indicating the start point of the vertical display area is output when the count signal 731 and the signal 743 are equal. A signal 754 indicating the end of the vertical display area if the signals 744 are equal.
Is output. The operation of this comparator will be described with reference to the timing chart of FIG. Only when the count value of the count signal 721 and the content of the signal 741 from the register circuit 74 match and the count value of the count signal 721 and the content of the signal 742 from the register circuit 74 match. A signal 751 indicating the start point and a signal 752 indicating the end point of the display area are output. Although FIG. 9 shows the operation of the signal in the horizontal direction, the same operation as the operation in the horizontal direction is performed for the signal in the vertical direction.

The circuits 76a and 76b in FIG. 6 are circuits for outputting a timing signal 761 for the horizontal display area and a timing signal 762 for the vertical display area between the start and end points in the horizontal and vertical directions. 6 shows with an SR flip-flop. The operation of this circuit 76 is shown in FIG.
The timing chart will be described. The timing signal 761 for the horizontal display area is output from when the signal 751 indicating the start point of the horizontal display area is input until the signal 752 indicating the end point is input. Although FIG. 10 shows only the operation of the signal in the horizontal direction, the same operation as the operation in the horizontal direction is performed for the signal in the vertical direction.

The circuit 77 of FIG. 6 is a signal 76 from the circuits 76a and 76b which indicates the horizontal and vertical display areas.
This is a circuit that calculates 1, 762 and outputs a second timing signal 771 indicating the display area of the display device.
In FIG. 6, it is shown by an AND gate. The operation of this circuit 77 will be described with reference to FIG. The second timing signal 771 indicating the display area of the display device 5 is output only while the timing signal 761 for the horizontal display area and the timing signal 762 for the vertical display area are simultaneously input.

Reference numeral 79 in FIG. 6 is a display area comparator for comparing the display area indicated by the first timing signal 205 generated by the display control circuit 2 with the display area indicated by the second timing signal 771. The horizontal display area can be obtained by counting the clock signals while the timing signals between the horizontal sync signals are valid, and the vertical display area is the effective number of timing signals between the vertical sync signals. Can be obtained by counting. This is shown in FIG. First timing signal 205
By comparing the display information obtained from the second timing signal 771 with the display area of the display device 5, it is possible to detect a case where the display areas are different. The signal 791 is effective when the display information and the display area of the display device 5 are different, that is, when the display areas indicated by the first timing signal 205 and the second timing signal 771 are different.

In the circuit 78 of FIG. 6, the second timing signal 77 is generated by the signal 791 indicating that the display area of the display device 5 and the display area of the display information are different from each other.
It is a selector circuit that selects the first or first timing signal 205. When the signal 791 is valid, that is, when the display area of the display device 5 is different from the display area of the display information, the second timing signal 771 is output to the signal 701, and when the signal 791 is not valid, that is, the display device 5 When the display area of the display area and the display area of the display information match, the first timing signal 205 is output as the signal 701. Thereby, when the display area of the display device 5 is different from that of the display device 5, the display information is automatically displayed at an arbitrary position of the display device 5.

[0024]

According to the present invention, when the display area of the display device is different from the display area of the display information, the display information of the display area having a size different from the display area of the display device is automatically displayed. It is possible to display at any position in the display area of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a display device of the present invention.

FIG. 2 is a timing chart showing the operation of FIG. 1 when the display area of display information is different from that of the display device 5.

3 is a timing chart showing the operation of FIG. 1 when the display device 5 and the display area of the display information match.

FIG. 4 is a block diagram of a display device using a conventional technique.

FIG. 5 is a timing chart showing the operation of FIG.

FIG. 6 is a circuit diagram showing an embodiment of a timing signal control circuit 7.

7 is a timing chart showing the operation of the circuits 71a and 71b of FIG.

8 is a timing chart showing an operation of the circuit 72 of FIG.

9 is a timing chart showing the operation of the circuits 75a and 75b of FIG.

10 is a timing chart showing the operation of the circuit 76a of FIG.

11 is a timing chart showing the operation of the circuit 77 of FIG.

12 is a timing chart showing the operation of the circuit 79 of FIG.

[Explanation of symbols]

1 ... Refresh memory for storing display information, 2 ... Display control circuit, 4 ... Display device generation circuit, 5 ... Display device, 6 ...
CPU, 7 ... Timing signal control circuit for generating a second timing signal indicating the display area of the display device 5 and detecting a case where the display area of the display information is different from that of the display device 5.

Claims (2)

[Claims] 1. A display device, a refresh memory for storing display information, and a display control circuit for generating an address and a clock signal, a horizontal synchronizing signal, a vertical synchronizing signal and a timing signal in which the display information on the refresh memory is stored. A display information generating circuit for generating display information to be displayed on a display device by masking a non-display area of the display information fetched from the refresh memory by the address with the timing signal; A display control device for displaying in a display area of a display device by synchronizing with a horizontal synchronization signal, a vertical synchronization signal and the timing signal, wherein the display control circuit has the same timing as an address to a refresh memory. By the first timing signal indicating the display area of the display information to be displayed on Display information to be displayed on the display device is generated by masking the display region, and generation of the second timing signal indicating the display region of the display device and generation of the display region indicated by the first timing signal and the second timing signal are performed. By comparing, it automatically detects when the display area of the display device and the display area of the display information are different,
A timing signal control circuit that outputs the first timing signal when the display areas match and outputs the second timing signal when the display areas differ is provided, and when the display device and the display area of the display information are different. In addition, by synchronizing the display information with a clock signal, a horizontal synchronizing signal, a vertical synchronizing signal, and a second timing signal, display information of a size different from the display area of the display device is displayed in the display area of the display device. A display control device characterized by automatically displaying at an arbitrary place. 2. A display control which has a display device and a refresh memory for storing display information, displays the display information on the refresh memory, and masks the non-display region to display the display information in the display region of the display device. In the system, when the display area of the display information is different from that of the display device, the first timing signal indicating the display area of the display information displayed on the display apparatus and the second timing signal indicating the display area of the display apparatus are provided. A display control method characterized in that display information is displayed automatically in a display area of a size different from the display area of a display device by using two timing signals.