JPH06113265A - Motion compensation predicting unit - Google Patents

Abstract

PURPOSE:To allow the motion compensation predicting unit in the decoding system of a digital motion picture to be in compliance with the H.261 and MPEG and to prevent the circuitry from being increased. CONSTITUTION:A selector 15 outputs data of a forward direction frame and of a backward direction frame as one data in the case of the MPEG. A lateral direction processing circuit 16 implements the MPEG lateral processing or the H.261 lateral processing. A longitudinal processing circuit 18 implements the MPEG longitudinal processing or the H.261 longitudinal processing. A selector 17 selects a signal of the result of the MPEG lateral processing or a signal of the result of the H.261 lateral processing. A forward backward both-direction processing circuit 19 implements motion compensation prediction in both the forward and backward directions. A selector 20 selects the signal of the result of motion compensation prediction of the MPEG or the signal of the result of motion compensation prediction of the H.261.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation predictor,
In particular, it relates to a motion compensation predictor in a digital moving image decoding system.

CCIT is an international standard for video coding.
T. (International Telegraph and Telephone Advisory Committee) Recommendation 261 and IS
O (International Organization for Standardization) MPEG (Moving Pi)
There is a demand for a decoding system that complies with both standards. Therefore, H.264. There is a need for a motion compensation predictor that is compliant with H.261 and MPEG and that suppresses an increase in circuit scale.

[0003]

2. Description of the Related Art CCITT Recommendation H.264. 261 is “p × 6
It is a video coding standard for video communication using a primary group sub-rate from 64 kb to 2 Mb / s, entitled "4 kb / s video coding method for audio-visual service". Video conferencing or video telephony is assumed as the main application.

[0004] FIG. 261 is a block diagram of a video decoding system in H.261. The transmission decoder 82 performs transmission decoding of the received data, and the video multiplexing decoder 83 decomposes the signal supplied from the transmission decoder 82 into frames,
Perform variable length decoding.

The source decoder 84, based on the side information supplied from the video multiplex decoder 83, dequantizes and inverse DCT the signal supplied from the video multiplex decoder 83.
After performing (discrete cosine transform) calculation, motion-compensated inter-frame prediction is performed. The post-processor 85 receives the signal from the source decoder 84, performs post-processing, and outputs display data. The video multiplexing / combining device 83 and the source / combining device 84
Are controlled by the decoding control circuit 81.

FIG. 11 shows the H.264 signal of FIG. A block diagram of a H.261 source decoder 84 is shown. The inverse quantizer 91 performs inverse quantization on the quantization index of the transform coefficient based on the side information, that is, the transmission / non-transmission identification flag and the quantization characteristic designation.

The inversely quantized video signal in the inverse quantizer 91 is subjected to inverse DCT operation in the inverse DCT unit 92 and supplied to the motion compensation interframe predictor 93 as a difference video signal. The motion compensation inter-frame predictor 93 includes an adder 94,
Variable delay frame memory 95, in-loop filter 9
6 and a switch 97.

The variable delay frame memory 95 has an inverse D
With respect to the video signal of the current difference supplied from the CT unit 92, data of the frame in the forward direction in time is stored, and the delay amount is changed according to the motion vector.

When the in-loop filter ON / OFF flag is ON, the in-loop filter 96 outputs the filtered output signal, and the in-loop filter ON / OF is output.
When the F flag is OFF, the signal supplied from the variable delay frame memory 95 is output as it is.

When the intra-frame / inter-frame identification flag enables inter-frame prediction, the switch 97 selects the output signal of the in-loop filter 96. At this time, the adder 94 adds the difference from the inverse DCT unit 92 and the output signal of the in-loop filter 96. The addition result is output as a video signal and stored in the variable delay frame memory 95 to serve as a reference for the next screen.

When the intra-frame / inter-frame identification flag enables intra-frame prediction, the switch 97 selects a logical zero ("0"). At this time, the adder 9
4 outputs the difference from the inverse DCT unit 92 as it is. While this output signal is output as a video signal, it is stored in the variable delay frame memory 95 to serve as a reference for the next screen.

ISO MPEG is a draft standard defining a video efficient coding scheme for digital storage media. The main use is CD-R
Assuming an environment in which a storage medium (storage device) such as OM, DAT, or hard disk with a transfer rate of about 1.5 Mb / s or less is connected to the decoder directly or via a transmission medium. There is. FIG. 12 shows this MPEG
The block diagram of a video decoding system is shown.

The system multiplexer / decoder 103 separates the multiplexed signal supplied from the storage device 102 into audio and text information and a video signal. The video decoder 104 includes a buffer 105 and a video multiplexing decoder 10.
6 and a video source decoder 107.

The video multiplex decoder 106 includes a buffer 1
After decomposing the signal supplied from 05 into frames, variable length decoding is performed. The video source decoder 107, based on the side information supplied from the video multiplexing decoder 106, converts the signal supplied from the video multiplexing decoder 106 into
After performing inverse quantization and inverse DCT calculation, motion compensation interframe prediction is performed. The post-processor 108 is supplied with a signal from the video source decoder 107 to perform post-processing, and the D / A converter 109 is supplied with a signal from the post-processor 108,
D / A conversion is performed and display data is output.

FIG. 13 shows a block diagram of the MPEG video source decoder 107 of FIG. The inverse quantizer 111 performs inverse quantization on the quantization index of the transform coefficient based on the side information, that is, the quantization characteristic designation.

The inversely quantized video signal by the inverse quantizer 111 is inversely DCT-calculated by the inverse DCT unit 112 and supplied to the motion-compensated interframe predictor 113 as a difference video signal.

The motion-compensated inter-frame predictor 113 includes an adder 114, a frame memory A115, a frame memory B116, a motion-compensated forward predictor 117, a motion-compensated backward predictor 118, and a motion-compensated bidirectional predictor 119.
And switches 120 and 121.

The frame memory A 115 has an inverse DCT.
The data of the forward frame in time is stored with respect to the current differential video signal supplied from the device 112.
The frame memory B116 stores the data of the frame backward in time with respect to the current difference video signal supplied from the inverse DCT unit 112.

When the coding mode identification flag specifies 1/2 pixel precision motion compensation prediction, the motion compensation forward predictor 117 outputs a signal supplied from the frame memory A115 based on the 1/2 pixel precision motion vector. 1/2
If pixel-accurate motion-compensated prediction is performed and the encoding mode identification flag specifies 1-pixel motion-compensated prediction, the signal supplied from the frame memory A115 is output as it is.

When the coding mode identification flag specifies 1/2 pixel precision motion compensated prediction, the motion compensated backward predictor 118 outputs a signal supplied from the frame memory B 116 based on the 1/2 pixel precision motion vector. 1/2
When pixel-precision motion-compensated prediction is performed and the coding mode identification flag specifies 1-pixel precision motion-compensated prediction, the signal supplied from the frame memory B116 is output as it is.

When the coding mode identification flag specifies 1/2 pixel precision motion compensated prediction, the motion compensation bi-directional predictor 119 predicts the frame memory A 115 and the frame memory B 116 based on the 1/2 pixel precision motion vector.
1/2 pixel precision motion-compensated prediction is performed for each of the signals supplied from the above, and front-back bidirectional motion-compensated prediction is performed.
Further, when the coding mode identification flag specifies 1-pixel precision motion-compensated prediction, the motion-compensated bidirectional predictor 119:
Frame memory A115 and frame memory B11
The forward and backward bidirectional motion compensation prediction is performed on the signal itself supplied from 6.

When the coding mode identification flag specifies forward prediction, the switch 120 selects the output signal of the motion compensation forward predictor 117. When the coding mode identification flag specifies backward prediction, the switch 120
Thus, the output signal of the motion-compensated backward predictor 118 is selected. Further, when the coding mode identification flag specifies the bidirectional prediction in the forward and backward directions, the switch 120 selects the output signal of the bidirectional predictor 119 in the motion compensated forward and backward directions.

Further, when the coding mode identification flag specifies any of forward prediction, backward prediction, and forward and backward bidirectional prediction, the switch 121 selects the output signal of the switch 120. At this time, in the adder 114, the inverse DC
The difference from the T unit 112 and the output signal of one of the predictors from the switch 121 are added. The result of this addition is
While being output as a video signal, it is stored in the frame memory A115 to serve as a reference for the next screen.

When the coding mode identification flag does not specify forward / backward bidirectional prediction, forward prediction or backward prediction, the switch 121 selects logical zero ("0"). At this time, the adder 114 has the inverse DCT unit 11
The difference from 2 is output as it is. While this signal is output as a video signal, it is stored in the frame memory A115 to serve as a reference for the next screen.

The above H. The motion-compensated inter-frame predictor having both the motion-compensated inter-frame prediction function 261 and the MPEG motion-compensated inter-frame prediction function is configured as follows.
The structure is as shown in FIG.

In FIG. 14, the read address creation unit 131 uses the frame memory A 132, the frame memory A 132, and the start address of the processing unit block and the motion vector as a basis.
An address to be supplied to the frame memory B133 is generated.

The frame memory A 132 has an inverse DCT.
The data of the frame that is forward in time is stored with respect to the current differential video signal supplied from the container. The frame memory B133 stores data of a frame backward in time with respect to the current difference video signal supplied from the inverse DCT device.

H. 261 In-loop filter circuit 142
Comprises a selector 147, a horizontal processing circuit 143, and a vertical processing circuit 144. When the intra-frame / inter-frame identification flag enables inter-frame prediction and the in-loop filter ON / OFF flag is ON, the selector 147
Selects the signal from frame memory A132. At this time, H. The H.261 loop filter circuit 142 includes a horizontal direction processing circuit 143 and a vertical direction processing circuit 144, and the H. Filtering of the low-pass characteristic defined by H.261 is performed.

Further, the intra-frame / inter-frame identification flag enables inter-frame prediction, and the intra-loop filter is turned on / on.
When the OFF flag is OFF, the selector 147 selects the signal from the frame memory A132, and H.264. 261
The in-loop filter circuit 142 uses the frame memory A1.
The signal supplied from 32 is output as it is.

When the intra-frame / inter-frame identification flag enables intra-frame prediction, the selector 147
Outputs a signal of logic zero (“0”), and H.264. The 261-in-loop filter circuit 142 outputs a signal of logic zero (“0”).

The MPEG motion compensation prediction circuit 134 includes a motion compensation forward predictor 135 and a motion compensation backward predictor 13.
6 and a front-back bidirectional processing circuit 141. The motion compensation forward predictor 135 includes a selector 148, a horizontal processing circuit 137, and a vertical processing circuit 138.

The coding mode identification flag is forward prediction,
When designating either the forward or backward bidirectional prediction, the selector 148 selects the signal from the frame memory A132. Further, when the value of the motion vector is 1/2 pixel precision, the motion compensation forward predictor 135 determines that the horizontal direction processing circuit 1
37 and the vertical direction processing circuit 138 perform 1/2 pixel precision motion compensation prediction on the signal supplied from the frame memory A 132. If the value of the motion vector has a precision of one pixel, the motion compensation forward predictor 135 outputs the signal supplied from the frame memory A132 as it is.

When the coding mode identification flag does not specify forward prediction or forward / backward bidirectional prediction, the selector 148 outputs a signal of logical zero ("0") and the motion compensation forward predictor 135. Outputs a signal of logic zero (“0”).

The motion-compensated backward predictor 136 is composed of a selector 149, a horizontal processing circuit 139, and a vertical processing circuit 140. When the coding mode identification flag specifies either backward prediction or forward and backward bidirectional prediction, the selector 149 selects the signal from the frame memory B133.

Further, when the value of the motion vector is 1/2 pixel precision, the motion compensation forward predictor 136 is a signal supplied from the frame memory B133 by the horizontal processing circuit 139 and the vertical processing circuit 140. 1/2
Perform pixel-accurate motion-compensated prediction. In addition, when the value of the motion vector is 1 pixel accuracy, the motion compensation forward predictor 136
The signal supplied from the frame memory B133 is output as it is.

When the coding mode identification flag does not specify either backward prediction or forward / backward bidirectional prediction, the selector 149 outputs a signal of logical zero ("0") and the motion compensation forward predictor 136. Outputs a signal of logic zero (“0”).

The forward / backward bidirectional processing circuit 141 uses the output signal of the motion-compensated forward predictor 135 and the output signal of the motion-compensated backward predictor 136 when the coding mode identification flag specifies forward / backward bidirectional prediction. , Bidirectional motion compensation prediction is performed. Further, when the coding mode identification flag specifies forward prediction, the signal of the prediction result by the motion compensation forward predictor 135 is output. When the coding mode identification flag specifies backward prediction, the signal of the prediction result by the motion compensation backward predictor 136 is output.

When the coding mode identification flag does not specify any of forward prediction, backward prediction, and forward and backward bidirectional prediction, the forward and backward bidirectional processing circuit 141 causes the motion-compensated forward predictor 135 or the motion-compensated forward predictor. It outputs a signal of logic zero (“0”) supplied from the direction predictor 136.

The selector 145 is an MPEG / H. 261
H. 2 depending on the flag. When the H.261 mode is designated, H.264 is specified.
The output signal of the H.261 loop filter circuit 142 is selected, and when the MPEG mode is designated, the output signal of the MPEG motion compensation prediction circuit 134 is selected.

The adder 146 adds the difference from the inverse DCT unit and the output signal of the selector 145. The result of this addition is output as a video signal, while it is stored in the frame memory A 132 for use as a reference for the next screen.

H. In 261 mode, in frame /
Output from the selector 145 when the inter-frame identification flag enables intra-frame prediction, or in the MPEG mode, when the coding mode identification flag does not specify any of forward prediction, backward prediction, and forward and backward bidirectional prediction. The signal becomes a logical zero (“0”), and the adder 146 outputs the inverse DCT output as it is. While this inverse DCT output is output as a video signal, it is stored in the frame memory A132 to serve as a reference for the next screen.

Next, H. 261 In-loop filter circuit 1
42 horizontal processing circuits 143 and vertical processing circuits 14
The in-loop filter composed of 4 will be described.
H. As shown in FIG. 15, the in-loop filter required in H.261 is 8 pixels in vertical direction extracted from one screen ×
The filter processing is performed with a 1-2-1 type low-pass characteristic on a block of 8 horizontal pixels. This 1-2-1
The type low-pass filter sets the weight for the pixel of interest to 2 and the weight to the preceding and subsequent pixels in both the horizontal and vertical processes.

FIG. 15 (I) shows a block of vertical 8 pixels × horizontal 8 pixels on which filter processing is performed, and FIG. 15 (II) shows (I).
The four types of pixels (, ◯, ⊚, □) indicate the related pixels during the filtering process, and FIG. 15 (III) shows the results of the filtering process for the above four types of pixels.

As shown in FIGS. 15 (II) and 15 (III),
The pixel of is left as it is. For the pixels of ○,
Assuming that the pixel of interest is B, the previous pixel is A, and the previous pixel is C, the value is (A + 2 × B + C) / 4. Further, for the pixel of ⊚, if the pixel of interest is B, the pixel one row before is A, and the pixel one row after is C, then (A + 2 × B +
C) / 4 value. Also, for the pixel of □, the pixel of interest is E, and the pixels around E are as shown in (II),
Assuming A, B, C, D, F, G, H, and I, ((A + 2
× B + C) + 2 × (D + 2 × E + F) + (G + 2 × H +
I)) / 16.

In the actual filtering process, data of 8 × 8 pixels is input, and (A
+ 2 × B + C) / 4 horizontal processing is performed, and (A + 2 × B + C) / 4 is obtained for the pixels in the upper and lower rows of the obtained results.
Necessary processing can be performed by performing the vertical processing of.

H. The in-loop filter in the 261 in-loop filter circuit 142 is composed of the horizontal direction processing circuit 143 shown in FIG. 16 and the vertical direction processing circuit 144 shown in FIG. As shown in FIG. 16, the horizontal processing circuit of the in-loop filter is composed of delay elements XD151 and XD152, adders 153 and 155, multipliers 154 and 156, and a selector 157. In FIG. 16, XD15
1, XD152 is a delay element that creates a delay for one pixel adjacent in the horizontal direction.

When the filter processing target / non-target flag designates the processing target, the selector 157 selects the adder 15
The output signal 5 is selected and output. At this time, if the data from the frame memory is input in the order of A, B, and C, and the current input data is C, the output of the selector 157 is A + 2 × B + C.

When the filtering target / non-target flag specifies non-target, the selector 157 determines that the multiplier 15
The output signal of 6 is selected and output. At this time, if the data from the frame memory is input in the order of A, B, and C, and the current input data is C, the output of the selector 157 is 4 × B.

As shown in FIG. 17, the vertical processing circuit of the in-loop filter has delay elements YD161, YD162,
It is composed of adders 163 and 165, multipliers 164 and 166, and a selector 167. In FIG. 17, YD16
1, YD 162 is for one adjacent vertical row (eight pixels)
Is a delay element that creates a delay of.

When the filter processing target / non-target flag designates the processing target, the selector 167 causes the adder 16 to operate.
The output signal 5 is selected and output. At this time, if the current input data supplied from the horizontal processing circuit is L, the data one row before is K, and the data one row before is J, the output of the selector 157 is J + 2 × K + L.

When the filtering target / non-target flag designates non-target, the selector 167 determines that the multiplier 16
The output signal of 6 is selected and output. At this time, if the current input data supplied from the horizontal direction processing circuit is L, the data one row before is K, and the data one row before is J, the output of the selector 167 is 4 × K.

Next, motion compensation prediction in the MPEG motion compensation prediction circuit 134 will be described. FIG. 18 shows 1
An explanatory view of / 2 pixel precision motion compensation prediction is shown. FIG.
(I) is vertical 9 pixels for which 1/2 pixel precision motion compensation prediction is performed.
A block of 9 pixels in the horizontal direction is shown. (II) and (III) are original adjacent pixels a, b, c, and d, a pixel A obtained by horizontal processing, a pixel B obtained by vertical processing, and a horizontal direction. The pixel C obtained as a result of the processing and the vertical processing is shown.

As shown in (III), the horizontal processing is performed by A
The average value of adjacent pixels in the horizontal direction is taken as = (a + b) / 2. The vertical processing is as shown in (III).
As B = (a + c) / 2, the average value of the pixels of the rows adjacent in the vertical direction of the data obtained as a result of the horizontal processing is taken. As a result of this horizontal processing and vertical processing, C = ((a +
b) + (c + d)) / 4, the average value of the adjacent pixel and the pixel is obtained, and the average value is set as a pseudo intermediate pixel between the pixel and the pixel.

FIG. 19 is an explanatory view of the forward and backward bidirectional motion compensation prediction. As shown in FIG. 19, the forward and backward bidirectional motion compensation prediction takes the average value A = (a + b) / 2 of the pixel a of the forward reference screen and the pixel b of the backward reference screen, and sets it as the official reference value. The processing is performed.

Both the motion-compensated forward predictor 135 and the motion-compensated backward predictor 136 shown in FIG. 14 are executed by the horizontal processing circuit shown in FIG. 20 and the vertical processing circuit shown in FIG. Be seen. The horizontal processing circuit shown in FIG. 20 includes a delay element XD 171, an adder 172, multipliers 173 and 175, and a selector 174. The delay element XD171 causes a delay of one pixel in the horizontal direction.

When the pixel interpolation target / non-target flag specifies the interpolation target, the selector 174 selects the output signal of the adder 172. At this time, from the frame memory,
Data is input in the order of a and b, and the current input data is b
Then, the selector 174 outputs the signal of a + b.

When the pixel interpolation target / non-target flag specifies non-target, the selector 174 selects the output signal of the multiplier 173. At this time, from the frame memory,
Data is input in the order of a and b, and the current input data is b
Then, the selector 174 outputs a 2 × a signal. It should be noted that the multiplier 175 is based on the H.264 circuit of FIG. This is for matching the output signal of the filter 261 in the 261 loop and the digit of the signal.

The vertical processing circuit shown in FIG. 21 includes a delay element YD181, an adder 182, a multiplier 183, and a selector 184. The delay element YD181
Causes a delay of one row in the vertical direction.

When the pixel interpolation target / non-target flag specifies the interpolation target, the selector 184 selects the output signal of the adder 182. At this time, assuming that the current input data supplied from the horizontal processing circuit is f and the data one row before is e, the selector 184 outputs a signal of e + f.

When the pixel interpolation target / non-target flag specifies non-target, the selector 184 selects the output signal of the multiplier 183. At this time, assuming that the current input data supplied from the horizontal processing circuit is f and the data one row before is e, the selector 184 outputs a 2 × e signal.

FIG. 22 shows a circuit diagram of the front-back bidirectional processing circuit 141. The forward / backward bidirectional processing circuit 141 is supplied with the output signals of the motion-compensated forward predictor 135 and the motion-compensated backward predictor 136, and performs forward / backward bidirectional motion-compensated prediction.

As shown in FIG. 22, the front-back bidirectional processing circuit 141 includes an adder 191, a multiplier 193, and a selector 1.
92 and 194. The adder 191 outputs the output signal of the forward processing system (the motion compensation forward predictor 13 in FIG. 14).
5) and the output signal of the backward processing system (the output signal of the motion compensation backward predictor 136 of FIG. 14) are added.

When the bidirectional motion compensation processing target / non-target flag specifies the processing target, the selector 194 selects the output signal of the adder 191, and selects the signal of the forward processing system and the signal of the backward processing system. Output the added value.

When the bidirectional motion compensation processing target / non-target flag designates non-target and the forward / backward flag designates forward, the signal of the forward processing system is selected by the selector 192 and the multiplier 193 is selected. After being doubled with selector 1
It is output from 94.

When the bidirectional motion compensation processing target / non-target flag specifies non-target and the forward / backward flag specifies backward, the signal of the backward processing system is selected by the selector 192 and the multiplier 193 is selected. After being doubled with selector 1
It is output from 94.

It should be noted that the multiplier 193 is the H.264 circuit of FIG. Two
This is for matching the output signal of the 61-loop filter 142 and the digit of the signal.

[0067]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, as shown in FIG. In the motion-compensated interframe predictor conforming to H.261 and MPEG, H.264 is used. The motion compensation prediction function with in-loop filter in H.261, the 1/2 pixel precision motion compensation prediction function in MPEG, and the bidirectional motion compensation prediction function in both directions are configured by separate circuits. Therefore, there is a problem that the circuit scale increases.

The present invention has been made in view of the above points. It is an object of the present invention to provide a motion compensation predictor that complies with H.261 and MPEG and that suppresses an increase in circuit scale.

[0069]

A motion-compensated predictor according to the present invention has a 1-2-1 type low-pass filtered motion-compensated predictive function, a front-back bidirectional motion-compensated predictive function, and a pixel interpolation function. A motion-compensated predictor in a decoder for a digital moving image selected by a control signal, wherein the bidirectional motion-compensated predictive function and the pixel interpolation function are selected,
The data of the forward frame and the data of the backward frame are integrated into one system of data and output. When the motion compensation prediction function with the 1-2-1 low-pass filter is selected, the forward frame Is supplied with the output signal of the first selecting unit 15 and the first selecting unit 15 for selecting and outputting the data of 1) and the horizontal processing of the pixel interpolation function and 1-2-1.
Horizontal processing means 16 for performing the horizontal processing of the motion compensation prediction function with a low pass filter and the forward and backward bidirectional motion compensation prediction function and the pixel interpolation function by the external control signal. When the signal of the horizontal processing result of the pixel interpolation function supplied from the means 16 is selected and output, and the motion compensation prediction function with the 1-2-1 type low-pass filter is selected by the external control signal, Second selecting means 17 for selecting and outputting the signal of the horizontal processing result of the motion compensation prediction function with the 1-2-1 type low-pass filter supplied from the horizontal processing means 16; A vertical direction processing unit 18 which is supplied with the output signal of the second selection unit 17 and performs a vertical direction process of the pixel interpolation function and a vertical direction process of the motion compensation prediction function with the 1-2-1 type low-pass filter. Above vertical direction The signal of the vertical processing result of the pixel interpolation function is supplied from the processing means 18, and the front-back bidirectional processing means 19 for performing the front-back bidirectional motion compensation prediction, and the front-back bidirectional motion compensation prediction function and the pixel interpolation function are selected by the external control signal. Then, the front-rear bidirectional processing result signal supplied from the front-rear bidirectional processing means 19 is selected and output, and the 1-2-1 type low-pass filter-equipped motion compensation prediction function is selected by the external control signal. Third selection means for selecting and outputting the signal of the vertical processing result of the motion compensation prediction function with the 1-2-1 low-pass filter supplied from the vertical processing means 18 when selected And 20.

[0070]

The first selecting means 15 of the present invention, when the forward and backward bidirectional motion compensation prediction function and the pixel interpolation function are selected,
The data of the forward direction frame and the data of the backward direction frame are integrated into one system data, and the horizontal direction processing means 16 and the vertical direction processing means 18 have a circuit for forward and backward bidirectional motion compensation prediction function and a pixel interpolation function and 1 The main part is shared with the circuit for the motion compensation prediction function with the 2-1 type low-pass filter. Therefore, it is possible to suppress an increase in circuit scale.

[0071]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention. This embodiment is based on H.264. It is a motion-compensated interframe predictor conforming to H.261 and MPEG. Read address creation unit 11
Generates an address to be supplied to the frame memory A12 and the frame memory B13 based on the screen size, the start address of the processing unit block, and the motion vector. The frame memory A12 stores forward data in time with respect to the current differential video signal supplied from the inverse DCT device. Inverse DCT in frame memory B13
Data is stored backward in time with respect to the current differential video signal supplied from the instrument.

MPEG / H. The 261 circuit 14 includes a selector 15 that is a first selecting unit, a horizontal processing circuit 16 that is a horizontal processing unit, and a selector 1 that is a second selecting unit.
7, a vertical processing circuit 18 which is vertical processing means, a front-back bidirectional processing circuit 19 which is front-back bidirectional processing means, and a selector 20.

MPEG / H. 261 circuit 14 is MPE
G / H. If the MPEG mode is selected by the H.261 flag, the coding mode identification flag specifies either forward prediction, backward prediction, or forward and backward prediction, or if the motion vector has 1/2 pixel accuracy, -MPEG-compliant motion-compensated prediction is performed on the signals supplied from the memory A12 and the frame memory B13.

In addition, the MPEG / H. H.261 flag.
261 mode is selected, and when the intra-frame / inter-frame identification flag enables inter-frame prediction, H.264 is applied to the signal supplied from the frame memory A12.
261 based motion compensation prediction is performed.

When the MPEG mode is selected and the coding mode identification flag specifies any of forward prediction, backward prediction, and forward and backward bidirectional prediction, the selector 15 selects
The forward frame data supplied from the frame memory A12 and the backward frame data supplied from the frame memory B13 are integrated into one system of data and output.

In addition, H. When the H.261 mode is selected and the intra-frame / inter-frame identification flag enables inter-frame prediction, the data of the forward frame supplied from the frame memory A12 is selected and output.

In the horizontal direction processing circuit 16, the horizontal direction processing circuit for the motion compensation prediction function conforming to the MPEG and the H.264 / AVC system are provided. Two
A horizontal direction processing circuit for a motion compensation prediction function conforming to H.61 shares a main part and is supplied with frame data from the selector 15 to perform horizontal direction processing in MPEG mode or H.264. The horizontal processing of the 261 mode is performed. In addition, MPEG
H. system output terminal The output terminals of the 261 system are independent.

The selector 17 receives a signal from the horizontal direction processing circuit 16 as a result of the horizontal direction processing in the MPEG mode, or an H.264 signal.
261 mode horizontal processing result signal is supplied, MP
EG / H. When the MPEG mode is selected by the 261 flag, the signal of the horizontal processing result of the MPEG mode is selected and output. In addition, MPEG / H. H.261 flag. When the H.261 mode is selected, the H.264 mode is selected. The signal of the horizontal processing result in the 261 mode is selected and output.

The vertical direction processing circuit 18 includes a vertical direction processing circuit for a motion compensation prediction function conforming to MPEG and an H.264 / AVC processing unit. Two
61 and the vertical processing circuit for the motion-compensated prediction function conforming to H.61 share a main part, and a signal of the horizontal processing result in the MPEG mode from the selector 17 or H.264. 261 mode horizontal processing result signal is supplied, MPEG mode vertical processing, or H.264. The vertical processing of the 261 mode is performed.
It should be noted that an MPEG-type output terminal and an H.264 standard. The output terminals of the 261 system are independent.

The front-rear bidirectional processing circuit 19 is supplied with the signal of the vertical-direction processing result of the MPEG mode from the vertical processing circuit 18, and performs the front-rear bidirectional motion compensation prediction. The front / rear bidirectional processing circuit 19 has one input terminal and handles data obtained by integrating the data of the forward frame and the data of the backward frame.

The bidirectional processing circuit 19 performs bidirectional motion compensation prediction when the coding mode identification flag specifies bidirectional prediction. Further, when the coding mode identification flag specifies forward prediction, the horizontal direction processing circuit 16
And a signal for forward motion compensation prediction obtained by the vertical direction processing circuit 18 is output. When the coding mode identification flag specifies backward prediction, the horizontal direction processing circuit 16
And a backward motion compensation prediction signal obtained by the vertical direction processing circuit 18 is output.

The selector 20 is an MPEG / H. H.261 flag. When the H.261 mode is selected, the H.264 mode is selected.
261 mode motion compensated prediction signal is selected and output,
When the MPEG mode is selected, the motion compensation prediction signal of the MPEG mode is selected and output.

In the adder 21, the difference from the inverse DCT device and the output signal of the selector 20 are added. The result of this addition is output as a video signal, while it is stored in the frame memory A12 to serve as a reference for the next screen.

H. In the H.261 mode, when the in-loop filter ON / OFF flag is ON, the horizontal direction processing circuit 16 and the vertical direction processing circuit 18 are set to H.264. 261 mode filtering is performed, but in-loop filter ON / OF
When the F flag is OFF, the horizontal processing circuit 16 and the vertical processing circuit 18 do not perform the filtering process.

In addition, the H. In 261 mode, in frame /
Output from the selector 15 when the inter-frame identification flag enables intra-frame prediction, or when the coding mode identification flag does not specify any of forward prediction, backward prediction, and forward and backward bidirectional prediction in MPEG mode. The signal becomes a logical zero (“0”), and the output signal of the selector 20 also becomes a logical zero (“0”). At this time, the adder 146 outputs the inverse DCT output as it is. This inverse DCT output is
While being output as a video signal, it is stored in the frame memory A12 to serve as a reference for the next screen.

Next, the horizontal processing circuit 16, the vertical processing circuit 18, and the front-back bidirectional processing circuit 19 of FIG. 1 will be described. FIG. 2 shows a circuit diagram of the lateral processing circuit 16 of FIG.
In FIG. 2, the circuit for horizontal processing in the MPEG mode includes delay elements XD31, XD32, an adder 33, a multiplier 34, a selector 35, and a multiplier 36. In addition, H. The circuit for the horizontal processing in the 261 mode includes delay elements XD31, XD32, an adder 33, an adder 38, a multiplier 37, a multiplier 39, and a selector 40.
Composed of and. The delay elements XD31 and XD32
Causes a delay of one pixel.

FIG. 3 is a circuit diagram of the vertical processing circuit 18 shown in FIG. In FIG. 3, the circuit for the vertical processing in the MPEG mode includes delay elements YD51, YD52, and an adder 5.
3, a multiplier 54, a selector 55, and a multiplier 56. In addition, H. The circuit for vertical processing in the 261 mode includes delay elements YD51, YD52, an adder 53, an adder 58, a multiplier 57, a multiplier 59, and a selector 60. The delay element YD51,
The YD 52 causes a delay of one row in the vertical direction.

As shown in FIG. 2, a circuit for horizontal processing in the MPEG mode, and an H.264 standard. The main part is shared with the circuit for the horizontal processing of the 261 mode. Further, as shown in FIG. The main part is shared with the circuit for the vertical processing of the 261 mode. Therefore, the increase in circuit scale can be suppressed.

FIG. 4 shows a circuit diagram of the front-back bidirectional processing circuit 19 of FIG. The front-back bidirectional processing circuit 19 includes a delay element Z
It comprises a D71, an adder 72, a selector 75, a selector 73, and a multiplier 74. The delay element ZD
Reference numeral 71 causes a delay corresponding to the time difference between the forward-direction processed data and the backward-direction processed data being supplied.

FIG. 5 shows an operation timing chart of the horizontal direction processing circuit 16 in the MPEG mode, and FIG.
7 shows an operation timing chart of the vertical direction processing circuit 18 in the MPEG mode. Further, FIG. 7 shows an operation timing chart of the bidirectional processing circuit 19 in the MPEG mode. The signals S1 to S20 are common to FIGS. 2, 3, 4, 5, 6, 7, 8, and 9.

Further, in FIGS. 5, 6 and 7, 1DX
X indicates the data from the frame memory A as it is, and 2DXX indicates the data from the frame memory B as it is. Further, 1fXX indicates that the data from the frame memory A has undergone horizontal processing, and 2fXX indicates
Indicates that the data from frame memory B has undergone lateral processing.

Further, 1FXX indicates that the data from the frame memory A has been subjected to the vertical processing, and 2FXX.
Indicates that the data from frame memory B has undergone vertical processing. In addition, FXX indicates data that has been subjected to front-back bidirectional processing. XX is a number indicating the order of reading from the frame memory.

First, FIG. 5 will be described. Figure 5
(B) shows the data from the frame memory A12,
FIG. 5C shows the data from the frame memory B13. In the case of MPEG, data from two frame memories, frame memory A12 and frame memory B13, may be used. Therefore, the two types of data are unified by the selector 15 of FIG.

The signal S1 in FIG. 5D is this unified data, and the data from the frame memory A12 and the data from the frame memory B13 are alternated for each clock of the clock M. In the MPEG mode, thereafter, the data is processed in a unified state as described above.

As described with reference to FIG. 18, the horizontal processing in MPEG is the addition of a pixel and the pixel immediately preceding it in the reading order from the frame memory. Therefore, in the horizontal direction processing circuit 16, as shown in FIG.
The signal S1 of (D) is changed to 1 like the signal S3 of FIG.
A process of adding the signals S1 and S3 is performed by delaying by a pixel.

Since the data from the frame memory A12 and the data from the frame memory B13 are alternated, the signal S1 is delayed by the delay element XD3 as shown in FIG.
1. The signal S3 is delayed by one pixel by the XD32. Further, the adder 33 adds the signal S1 and the signal S3.

The signal S4 (pixel interpolation processing target / non-target flag) in FIG. 5 (F) is a flag that specifies whether or not horizontal processing is to be performed. When the selector 35 of FIG. 2 is instructed to perform the horizontal processing by the signal S4, the signal S1
And the result of the addition of the signal S3 and the signal S3 is output.

In this embodiment, when the signal S4 is at low level ("L"), the horizontal processing is performed. As shown in FIG. 5 (F), the signal S4 becomes "L" and horizontal processing is performed during a period in which the significant periods of the signal S1 and the signal S3 overlap. During this period, the signal S5 of FIG. 5G is the result of addition of the signals S1 and S3.

The signal S4 is high level ("H").
When the horizontal processing is not performed, the selector 35 selects and outputs the output signal of the multiplier 34. Multiplier 3
The output signal 4 is the original pixel data (signal S3) doubled. Also, the multiplier 36
H. H.261 that is effective in the H.261 mode. This is for matching the digit with the value of the output signal of the 261 system (the output signal of the selector 40).

As described with reference to FIG. 18, the vertical processing in MPEG is the addition of a pixel and the pixel one row before in the reading order from the frame memory. Therefore, in the vertical direction processing circuit 18, as shown in FIG.
The signal S8 of (B) is changed to 1 like the signal S10 of FIG. 6 (C).
A process of delaying by a row and adding the signals S8 and S10 is performed.

In the MPEG mode, the data from the horizontal direction processing circuit alternates between the data from the frame memory A12 and the data from the frame memory B13. Therefore, as shown in FIG. 3, the signal S8 is delayed by one row by the delay elements YD51 and YD52 to form the signal S10. The adder 53 adds the signal S8 and the signal S10.

The signal S11 (pixel interpolation processing target / non-target flag) in FIG. 6D is a flag that specifies whether or not vertical processing is to be performed. The selector 55 of FIG. 3 receives the signal S8 when the vertical processing is designated by the signal S11.
And the result of the addition of the signal S10 is output as a signal S12.

In this embodiment, when the signal S11 is "L",
Performs vertical processing. As shown in FIG. 6D, the signal S11
Is "L" and vertical processing is performed during the period in which the significant periods of the signal S8 and the signal S10 overlap. this period,
The signal S12 in FIG. 6 (E) is the result of addition of the signals S8 and S10.

When the signal S11 is "H" and vertical processing is not performed, the selector 55 selects and outputs the output signal of the multiplier 54. The output signal of the multiplier 54 is
The data (signal S10) of the pixel of interest is doubled. In addition, the multiplier 56 is an H.V. H.261 that is effective in the H.261 mode. This is for matching the digit with the value of the output signal of the 261 system (the output signal of the selector 60).

As described with reference to FIG. 19, the forward / backward bidirectional processing in MPEG is addition of forward reference data and backward reference data. By the way, as described above, in the data supplied from the vertical processing circuit, the forward reference data and the backward reference data are alternated every one clock. Therefore, in the front-back bidirectional processing circuit 19, as shown in FIG.
The signal S15 of (B) is changed to 1 as the signal S16 of FIG.
A process of adding the signal S15 and the signal S16 by delaying by the clock is performed.

As shown in FIG. 4, the signal S15 is delayed by the delay element Z.
The signal S16 is delayed by one clock at D71, and the signal S15 and the signal S16 are added by the adder 72.

The signal S19 (bidirectional motion compensation processing symmetrical / non-symmetrical flag) in FIG. 7F is a flag that specifies whether or not bidirectional processing is performed. The selector 75 shown in FIG.
When it is specified by the signal S19 to perform the bidirectional processing, the result of addition of the signals S15 and S16 is output as the signal S20.

In this embodiment, when the signal S19 is "L",
Performs both forward and backward processing. As shown in FIG. 7 (F), the signal S19 becomes "L", and the front and rear bidirectional processing is performed by the signal S
In the period of 15 and the signal S16, the data having the same reading order from the frame memory is overlapped. This period, Figure 7
The signal S20 in (G) is the result of addition of the signals S15 and S16.

The signal S17 is a signal indicating which of the forward reference data and the backward reference data is significant when the bidirectional processing is not performed. In this embodiment, the forward reference data is significant when the signal S17 is "L", and the backward reference data is significant when the signal S17 is "H".

When the signal S19 is "H" and the bidirectional processing is not performed, the selector 75 selects and outputs the output signal of the multiplier 74. The output signal of the multiplier 74 is obtained by doubling either the forward reference data or the backward reference data selected by the selector 73 by the designation of the signal S17.

FIG. 9 shows an operation timing chart of the horizontal direction processing circuit 16 in the H.261 mode.
H. 8 shows an operation timing chart of the vertical direction processing circuit 18 in the 261 mode.

The signals S1 to S20 are common to FIGS. 2, 3, 4, 5, 6, 7, 8 and 9.

In FIGS. 8 and 9, DXX indicates the data from the frame memory A as it is, and fXX
Indicates that the data from frame memory A has undergone lateral processing. In addition, FXX is a frame memory A
Shows that the data from has undergone vertical processing. In addition,
XX is a number indicating the order of reading from the frame memory.

First, FIG. 8 will be described. H. 26
In the 1st mode, MPEG / H. With the 261 flag, the selector 15 selects the data from the frame memory A12. The signal S1 in FIG. 8C is the frame memory A
Data from 12 are shown. H. In the H.261 mode, only the data of the frame memory A12 is handled, and therefore, FIG.
As shown in FIGS. The clock H in the 261 mode has a half frequency of the clock M in the MPEG mode.

As described with reference to FIG. 261
In the horizontal direction processing in, the pixel and the pixel one pixel before the pixel in terms of the reading order from the frame memory are used.
It is the addition of the doubled pixel and the previous pixel. Therefore, in the horizontal direction processing circuit 16, the signal S1 shown in FIG.
The signal S2 of (D) is delayed by one pixel, and the signal S2 is further delayed by one pixel as shown by the signal S3 of FIG. 8 (E). The signal S1 and the signal S2 are doubled and the signal S3 is delayed. Performs addition processing.

As shown in FIG. 2, the signal S1 is delayed by the delay element X.
A signal S2 is delayed by one pixel at D31, and a signal S2 is delayed by one pixel by the delay element XD32. Further, the adder 33 adds the signals S1 and S3 together, and the adder 38 adds a value obtained by doubling the signal S2 to the added value of the signals S1 and S3.

The signal S6 (filtering target / non-targeting flag) shown in FIG. 8F is a flag for designating whether or not horizontal processing is to be performed. When the selector 40 of FIG. 2 is designated to perform the lateral processing by the signal S6, the signal S1
And the result of addition of twice the signal S2 and the signal S3
Output as.

In this embodiment, when the signal S6 is "L",
Performs lateral processing. As shown in FIG. 8 (F), the signal S6
Is "L" and horizontal processing is performed during a period in which the significant periods of the signals S1, S2 and S3 overlap.
During this period, the signal S7 in FIG. 8G is the signal S1 and the signal S2.
And the signal S3.

When the signal S6 is "H" and horizontal processing is not performed, the selector 40 selects and outputs the output signal of the multiplier 39. The output signal of the multiplier 39 is
The data (signal S2) of the pixel of interest is multiplied by the multiplier 37,
It is quadrupled by 39.

As described with reference to FIG. 261
In the vertical direction processing, the vertical processing in a certain pixel and the pixel one row before in the reading order from the frame memory
It is the addition of double and the pixel of the previous row. Therefore, in the vertical direction processing circuit 18, the signal S8 of FIG.
The signal S9 of (D) is delayed by one row, and the signal S9 is further delayed by one row as shown by the signal S10 of FIG. 9 (E). The signal S8 and twice the signal S9 and the signal S10 are delayed. Performs addition processing.

As shown in FIG. 3, the signal S8 is delayed by the delay element Y.
The signal S9 is delayed by one row at D51 to form the signal S9, and the signal S9 is delayed by one row by the delay element YD52 to form the signal S10. The adder 53 adds the signal S8 and the signal S10, and the adder 58 adds a value obtained by doubling the signal S9 to the added value of the signal S8 and the signal S10.

The signal S13 (filtering target / non-targeting flag) in FIG. 9F is a flag for designating whether or not vertical processing is to be performed. The selector 60 of FIG. 3 receives the signal S8 when the vertical processing is designated by the signal S13.
And the result of addition of twice signal S9 and signal S10 is signal S14
Output as.

In this embodiment, when the signal S13 is "L",
Performs vertical processing. As shown in FIG. 9F, the signal S13
Is "L" and the vertical processing is performed during a period in which the significant periods of the signals S8, S9 and S10 overlap.
During this period, the signal S14 in FIG. 9G is the signal S8 and the signal S9.
And the signal S10.

When the signal S13 is "H" and the vertical processing is not performed, the selector 60 selects and outputs the output signal of the multiplier 59. The output signal of the multiplier 59 is
The data (signal S9) of the pixel of interest is multiplied by the multiplier 57,
It is quadrupled by 59.

As described above, in the present embodiment, when the MPEG mode is selected, the data of the forward frame and the data of the backward frame are integrated into one system, and the MPEG
Circuits for mode and H.264. The main part is shared with the circuit for the 261 mode. Therefore, H.264. 261 and M
It complies with both PEG and can suppress an increase in circuit scale.

[0126]

As described above, according to the present invention, when the forward / backward bidirectional motion compensation prediction function and the pixel interpolation function are selected, the data of the forward frame and the data of the backward frame are converted into one system data. Since the circuit for the front-back bidirectional motion compensation prediction function and the pixel interpolation function and the circuit for the 1-2-1 type low-pass filter motion compensation prediction function are integrated, the circuit scale is reduced. The increase can be suppressed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a horizontal processing circuit of the present embodiment.

FIG. 3 is a circuit diagram of a vertical processing circuit of this embodiment.

FIG. 4 is a circuit diagram of a front-back bidirectional processing circuit of this embodiment.

FIG. 5 is an operation timing chart of the horizontal direction processing circuit in the MPEG mode.

FIG. 6 is an operation timing chart of the vertical direction processing circuit in the MPEG mode.

FIG. 7 is an operation timing chart of the bidirectional processing circuit in the MPEG mode.

FIG. 8: 27 is an operation timing chart of the horizontal direction processing circuit in the 261 mode.

9: H. 27 is an operation timing chart of the vertical processing circuit in the 261 mode.

FIG. It is a block diagram of a H.261 video decoding system.

11: H. It is a block diagram of a H.261 source decoder.

FIG. 12 is a configuration diagram of an MPEG video decoding system.

FIG. 13 is a block diagram of an MPEG video source decoder.

FIG. 14: H. It is a block diagram of the motion compensation inter-frame predictor based on H.261 and MPEG.

FIG. 15 is an explanatory diagram of processing in an in-loop filter.

FIG. 16 is a circuit diagram of a horizontal processing circuit in an in-loop filter.

FIG. 17 is a circuit diagram of a vertical processing circuit in an in-loop filter.

FIG. 18 is an explanatory diagram of ½ pixel precision motion compensation prediction.

FIG. 19 is an explanatory diagram of front-back bidirectional motion compensation prediction.

FIG. 20 is a circuit diagram of a horizontal direction processing circuit of a 1/2 pixel precision motion compensation predictor.

FIG. 21 is a circuit diagram of a vertical processing circuit of a 1/2 pixel precision motion compensation predictor.

FIG. 22 is a circuit diagram of a front-back bidirectional processing circuit.

[Explanation of symbols]

 11 read address creating unit 12 frame memory A 13 frame memory B 14 MPEG / H. 261 circuit 15 selector 16 horizontal direction processing circuit 17 selector 18 vertical direction processing circuit 19 front-back bidirectional processing circuit 20 selector 21 adder

Claims (2)

[Claims] 1. A digital moving image decoder in which a 1-2-1 type low-pass filter-equipped motion compensation prediction function, a front-back bidirectional motion compensation prediction function, and a pixel interpolation function are selected by an external control signal. In the motion-compensated predictor, when the front-back bidirectional motion-compensated prediction function and the pixel interpolation function are selected, the data of the forward frame and the data of the backward frame are integrated into one system of data and output. -2
When the motion compensation prediction function with -1 type low-pass filter is selected, first selecting means (15) for selecting and outputting the data of the forward frame, and the first selecting means (15) Is supplied with the output signal of
Lateral processing means (16) for performing the lateral processing of the pixel interpolation function and the lateral processing of the 1-2-1 type low-pass filter-equipped motion-compensated prediction function, and the front-back bidirectional motion-compensated prediction function by the external control signal. When the pixel interpolation function is selected, the signal of the horizontal processing result of the pixel interpolation function supplied from the horizontal processing means (16) is selected and output, and 1 is output by the external control signal.
When the 2-1 type low-pass filter-equipped motion compensation prediction function is selected, the 1-2-1 type low-pass filter-equipped motion compensation prediction function supplied from the horizontal direction processing means (16). A second selection means (17) for selecting and outputting a signal of the horizontal processing result of (1) and an output signal of the second selection means (17),
Vertical processing means (18) for performing vertical processing of the pixel interpolation function and vertical processing of the motion compensation prediction function with the 1-2-1 type low pass filter, and pixel interpolation from the vertical processing means (18). When the front and rear bidirectional processing means (19) for performing the front and rear bidirectional motion compensation prediction is supplied with the signal of the vertical processing result of the function and the front and rear bidirectional motion compensation prediction function and the pixel interpolation function are selected by the external control signal, , The front-rear bidirectional processing result signal supplied from the front-rear bidirectional processing means (19) is selected and output, and 1-2 is output by the external control signal.
When the type 1 low pass filter motion compensation prediction function is selected, the vertical direction of the 1-2-1 type low pass filter motion compensation prediction function supplied from the vertical direction processing means (18). A motion compensation predictor characterized by comprising a third selecting means (20) for selecting and outputting a signal of a processing result. 2. The horizontal direction processing means (16) and the vertical direction processing means (18) when the 1-2-1 type low-pass filter-equipped motion compensation prediction function is selected by the external control signal. , CCITT H .; When the motion compensation prediction function with in-loop filter 261 is satisfied and the front-back bidirectional motion compensation prediction function and the pixel interpolation function are selected by the external control signal, the horizontal direction processing means (16) and the vertical direction processing means ( 18), and bidirectional processing means (19)
Is a bidirectional motion compensation prediction function of ISO MPEG and 1
The motion-compensated predictor according to claim 1, wherein the motion-compensated predictive function of / 2 pixel accuracy is satisfied.