JPH06105756B2 - Placement decision method - Google Patents

Description

The present invention relates to an integrated circuit (IC, M) on a printed circuit board.
The present invention relates to an arrangement determination method for determining the arrangement of (SI, LSI) and the arrangement of logic gates on a VLSI chip in an extremely short time.

(Prior Art) Where to place a plurality of ICs, MSIs, and LSIs to be mounted on a printed circuit board in the design of a printed circuit board, or to design a VLSI chip to be mounted on the chip. The design process that decides the relative relationship between the individual logic gates is called the layout design on the printed circuit board and the layout design on the VLSI chip, respectively. This layout design has a great influence on the success or failure of a wiring design (a design process for obtaining a wiring path for connecting a given signal terminal in a given wiring layer) which is subsequently performed. In other words, if a good placement is given to a logic circuit in which 100% of the wiring paths can be found, and if the wiring design is performed based on the bad placement, it is often impossible to find the 100% of the wiring paths. It happens. Therefore, the layout design should be based on the printed circuit board or VL.
It is an important design process in SI chip design.

This layout design is often done manually,
In recent years, it has become more and more often done by a program using a computer in order to shorten the design time, improve the placement quality, and reduce the design error. When software is used to perform placement processing, it is processed based on various placement methods, but the placement method called the replacement improvement method (or successive improvement method) must be used to obtain high-quality placement. There are many. This method starts from a given initial placement and improves placement by swapping modules (ICs, MSIs, LSIs, logic gates, etc.) with each other.

As a standard for evaluating the quality of arrangement, a standard called total wiring length minimization is generally used. This is an evaluation criterion that, when evaluating a given layout, try wiring temporarily based on the logical connection relationship, and if the total length of these temporary wirings is short, it is considered good layout, and if it is long, it is considered bad layout. Is.

The pair exchange method attempts to replace modules one by one. For example, in the light of the above evaluation criteria for minimizing the total wiring length, if there is an improvement, actually replace the module pair and if there is no improvement, The arrangement is improved by repeating the operation of not exchanging for different module pairs.

Next, the above-mentioned pair exchange method will be described with reference to FIGS. 1 and 2.

FIG. 1 shows an example of the initial arrangement, here 4 × 4.
= 16 nodes (nodes represent modules such as ICs, MSIs, LSIs, logic gates, etc.) are arranged in a 4 × 4 array, and branches between the nodes represent wiring.

FIG. 2 shows a method of calculating the length of the temporary wiring. The tentative wiring length is defined as 1/2 of the length of the circumference of the smallest rectangle that encloses all nodes connected by a net (with signal wiring that should be electrically the same potential). The provisional wiring lengths of the branches 21, 22, 23 shown in FIG. 1 are 1/2 of the rectangles 31, 32, 33 shown in FIG. 2, respectively. If the distances to adjacent nodes in the vertical and horizontal directions are all “1”, the provisional wiring lengths of the branches 21, 22, and 23 are “3”, “3”, and “2”, respectively. Of these, the contribution of the node is “8”,
Similarly, the contribution of the node is "5".

FIG. 3 shows a state after the nodes are replaced with each other, and the contributions of the nodes and the nodes after the replacement are "7" and "3", respectively.

The decrease in the total tentative wiring length due to the replacement of nodes is canceled out because the contributions of other nodes remain unchanged before and after the replacement. It is a value obtained by subtracting the contribution of the node and the node, and is (8 + 5)-(7 + 3) = 3. Since the total provisional wiring length is reduced by the replacement, the node becomes a candidate for replacement with the node, and the degree of improvement is "3". Similarly, as the candidates for interchange with the node, the improvement degree of each of the nodes ,,, and "2",
"3", "1", "5" can be obtained. The actual implementation is the replacement with the node that gives the maximum improvement of "5".

FIG. 4 shows the arrangement state of the nodes after the nodes have been exchanged through the series of processes described above.
When there is no interchangeable candidate and after the interchange is performed, another node is focused instead of the node and the same process is performed. These processes are repeated a predetermined number of times to obtain the final solution.

In the above method, selecting as many pairs of nodes as replacement candidates as much as possible and attempting improvement improves the quality of the final arrangement.

It is possible to obtain the best placement when all nodes are targeted for making a pair of nodes, but the computer processing time is 2
Since it is proportional to more than the power, the processing time becomes extremely large even if the number of nodes is several hundreds or more, and it is prohibited to apply such a method on a general-purpose computer.

In such fields, it is possible to speed up by introducing a parallel processing method, but in the past, a parallel processing method that can target all nodes to create a pair of nodes has not been found, and a pair of nodes is created. A parallel processing method has been considered in which the target is limited to upper, lower, left, and right adjacent nodes, and a device suitable for it has been considered. FIG. 5 is a block diagram of a main part of a conventional device, in which 1 is a cell, 2 is an address decoding circuit,
3 is an address data line, 4 is a cell selection line, 5 is an inter-cell data path, 6 is a data path, 7 is a control unit, 8 is a data input / output line, and 9, 10, 11 and 12 are clock lines. Cell 1
Consists of multiple registers, arithmetic unit, control circuit, control storage, etc.
It has processing functions such as addition and subtraction and comparison, and is arranged in an array as shown. The address decoding circuit 2 decodes the address data given from the address data line 3 and drives the specific cell selection line 4 to select the specific cell 1. In the selected cell 1, both of the two input cell selection lines 4 are in the "1" state, and the unselected cell 1
At least one of the two cell selection lines 4 input to the cell is set to the "0" state, which makes it possible to identify which cell 1 is selected. The inter-cell data path 5 is a dedicated data path between the cells 1 that are vertically or horizontally adjacent to each other, and is used to transfer the data of the registers in the adjacent cells 1. The data path 6 is a bidirectional data path, and is used to transfer the register in the arbitrary cell 1 to the control unit 7 and conversely to transfer the data in the control unit 7 to the arbitrary cell 1. To be The control unit 7 includes a register, an arithmetic circuit, a control circuit, a control storage,
It consists of a clock generation circuit and controls the entire device. The data input / output line 8 is for exchanging data between this device and the outside. Clock line 9,10,11,12
Is composed of four phases and is wired so as to supply a specific clock phase signal to a specific cell row or cell column. This device is roughly divided into the following three phases. Initial placement phase, wiring length increase / decrease value calculation phase,
It is a replacement phase. 4th in the initial placement phase
The initial arrangement state is set in each cell 1 in the figure. Each cell 1
The information to be given to the node 1 is the node number assigned to the cell 1 and the node number and position to which the node is connected. These pieces of information are sent from the outside to the predetermined cell 1 via the control unit 7 and stored therein. The write control of the predetermined cell 1 is performed by supplying a cell address to the address decode circuit and setting both the cell selection lines 4 of the predetermined cell 1 to "1". In the wiring length increase / decrease value calculation phase, the wiring length decrease amount when the node is exchanged with the adjacent cell 1 is calculated based on the given information. Since each cell 1 has only the node number assigned to the cell 1 and the node number and the position information connected to the node, the information held by the adjacent cells is stored in the cell using the inter-cell data path 5. Take in and perform these calculations. In the replacement phase, a cell with a positive sign of the wiring length reduction amount is replaced with the adjacent cell, and when it is negative or 0, it is not replaced with the adjacent cell.
To replace the adjacent cell, the inter-cell data path 5 is used to send the number and position information of the node assigned in the cell 1 and the node connected to the node to the adjacent cell 1, This is done by updating those information in.

The initial placement phase only occurs once at the beginning of every process. In the wire length increase / decrease value calculation phase and the replacement phase, the opponents to be paired up, down, left, right, up, down,
Repeated many times, changing to left, right, and so on. The cell 1 is read in a predetermined order, the node number is sent to the outside, and a series of processing is completed.

As described above, according to the conventional technique, it has been prohibitively long time for a sequential computer to try to improve the placement by selecting as many pairs of replacement candidate nodes as possible. On the other hand, the method of limiting the pair of replacement candidate nodes to upper, lower, left, and right adjacent pairs is also practically used as software on a sequential computer, and a dedicated device is also considered. However, the quality of the final placement was lower in the case where the pairs of nodes that were candidates for replacement were limited, compared to those where they were not limited.

(Object of the Invention) The present invention solves the above problems, and an object of the present invention is to present a method for improving the placement of all nodes as replacement partners by using a parallel processing device, and to reduce the processing time. It is what

(Structure and Action of the Invention) FIG. 6 is a block diagram of an embodiment showing a structure of a main part of a parallel processing device used in the arrangement determining method of the present invention.
101 to 117 are processors, 118 is a switching unit, 119 is a control unit, 120 to 137 are data signal lines, 138 and 139 are control signal lines, and 140 is a data input / output line.

Here, the processors 101 to 117 have the same configuration and each are composed of a plurality of registers, an arithmetic unit and a control circuit, and have processing functions such as data transfer between registers, addition / subtraction, and coincidence determination, and the exchange unit 118. Can transfer information from any processor to any other processor based on a control circuit and a control signal from the control circuit, or can transfer information from any processor to all processors. 119 is a register, an arithmetic circuit,
It comprises a control circuit, a storage, a clock generation circuit, etc., and controls the entire apparatus. The storage stores a sequence of this apparatus drive command and processing control data. The data signal lines 120 to 136 are used for exchanging data between the processors 101 to 117 and the exchange unit 118,
The data signal line 137 is connected to the exchange unit 118 and the control unit 119.
Data is exchanged between them. A control signal line 138 sends a control signal from the control unit 119 to the exchange unit 118, a control signal line 139 sends a control signal from the control unit 119 to the processors 101 to 117, and a data input / output line 140 between the outside and this device. For sending and receiving data, and for sending a sequence of this device drive command to this device.

FIG. 7 is a block diagram of one embodiment showing details of the configuration of one of the processors shown in FIG. 6, for example, the processor 101, in which 201 is a register, 202 to 207 are register files, and 208 to 210 are Arithmetic circuit, 211 is a control circuit, 212
˜214 is a signal bus, 215 is a control signal line, and
216 to 218 are coincidence signal lines and 219 are coded bit lines.

The register 201 is used for exchanging data with the exchange unit 118 shown in FIG. The contents of the register 201 are divided into high-order, middle-order, and low-order bit parts, and the register file 202 or 203, 204 or 205, 206 or 2 is respectively set according to the instruction of the control signal line 215.
Store in 07. The arithmetic circuits 208, 209, 210 have a function of performing addition / subtraction and coincidence determination, and the arithmetic results of the arithmetic circuits 208, 209, 210 are sent to the signal buses 212, 213, 214, respectively, and then the register 2
01 or stored in the register files 202 to 207. The calculation result of the calculation circuit 209 can be sent to the signal bus 212.
The control circuit 211 inputs the signals of the control signal line 139, the coincidence signal lines 216 to 218, and the code bit line 219 from the control unit 119 of FIG. 6, and generates control signals to be supplied to each part of the processor 101. Further, the control circuit 211 is the control unit 119 of FIG.
It is also possible to determine whether or not the received processor identification number corresponds and generate a control signal reflecting this.

FIG. 8 is a block diagram of an embodiment showing a detailed configuration of the exchange unit 118 shown in FIG. 6, in which 301 is a control circuit, 302 is a control signal line, and 303 to 323 are controls from the control circuit 301. It is a switching element that connects and disconnects depending on the signal,
A binary tree-like circuit as shown in the drawing is constituted by these switching elements and wirings connecting them.

According to such a configuration, a specific processor is designated and the same information is transferred from all the processors 101 to 117, the information is transferred from the control unit to the specific processor, and the specific processor is transferred to the control unit. It is possible to transfer information. Furthermore, as long as the transfer paths do not overlap, multiple sets of data transfer can be performed in parallel. For example, processors 101,103,105,107,109,111,11
Data of 3,115 are processed by processors 102, 104, 106, 108, 110, 1 respectively.
Transferring to 12,116 can be done in parallel.

The operation of the arrangement determining method of the present invention will be described in detail below with reference to FIGS. 1 to 4 and 6 to 8.

This method is roughly divided into the following 6 phases.
(I) sequence of driving instructions and load phase of initial placement data and control data, (ii) replacement node setting phase, (iii) improvement degree calculation phase, (iv) replacement partner node calculation phase, (v) replacement phase,
(Vi) This is the output phase of the result.

(I) Sequence of driving instructions and load phase of initial arrangement data and control data Sequence of instructions, control data and initial arrangement for driving the control unit 119 of this device externally (host computer operating by connecting this device) Generate data. In this phase, these pieces of information are loaded, the sequence of instructions and control data are stored in the storage of the control unit 119, and the initial arrangement data are stored in the register files of the processors 101 to 117. The process after the loading is performed according to the sequence of instructions and the control data stored in the storage of the control unit 119. The control data includes the number of repetitions of the replacement node setting to the replacement phase, the upper limit of the number of repetitions, and the identification number of the processor including the replacement node. As the initial arrangement data, one set of the X coordinate, the Y coordinate indicating the position of the node, and the identification number of the net including the node is set, and the register files 202, 204,
It is stored in the same address of 206 respectively. If the set of the value x of the register file 202, the value y of the register file 204, and the value i of the register file 206 is represented by (x, y, i), (x, y, i) for the node in FIG. 2,2, X), (1,4,2
1), (3,2,22), (4,1,22), (3,3,23), and these values are stored in the processor 105. X is do n’t ca
Re means that any identification number is acceptable. (X, y, i) for a node is (1,3, X), (1,1,24), (2,1,
24) and (2,1,25), which are stored in the processor 112.

(Ii) Swap Node Setting Phase Swap is performed according to the “identification number of the processor including the swap node” (hereinafter, 105 is assumed) stored in the storage of the control unit 119. Processor 105
All placement data (2,2, X), (1,
4,21), (3,2,22), (4,1,22), (3,3,23) are transferred to all processors via the exchange unit, and X-coordinates are stored in the register files 203, 205, 207 of the respective processors. , y coordinate and net identification number are stored.

(Iii) Improvement degree calculation phase A procedure for calculating the improvement degree D (112) will be described below using the processor 112 as an example. The contribution B (5) of the node is calculated based on the total tentative wiring length before the replacement. The contribution of the node is calculated by subdividing the contribution of the net 21, the contribution of the net 22, and the contribution of the net 23. The contribution of the net 22 is (2,2, X), (1,4,21), (3,2,22), (4,1,2
2), (3,3,23) with the same net number are taken out, and (2,2, X), (3,2,22), (4,1,22) are obtained. The maximum value "4" of these X coordinates, the minimum position "2", the Y coordinate position "2", and the minimum position "1" are calculated (this corresponds to the calculation of the rectangle 32 in FIG. 2), and the X coordinate is further calculated. Maximum value-X coordinate minimum value,
And the maximum value of the Y coordinate-the minimum value of the Y coordinate is calculated,
Get "2" and "1" respectively. The same calculation is performed on the nets 21 and 23 to obtain "1" and "2" and "1" and "1". By sending these values “2”, “1”, “1”, “2”, “1”, “1” to the register file 202 sequentially and adding them, B (5) = “8” on the register file 203. Can be obtained. Since the processor 112 also has node arrangement data, the node contribution B (12) = “5” of the total tentative wiring length before replacement can be similarly obtained in the register file 203. The node contribution A (5) of the total tentative wiring length after replacement is (1,3,
X), (1,4,21), (3,2,22), (4,1,22), (3,3,2
From (3), the node contribution A (12) is (2,2, X), (1,1,
24), (2,1,24) and (2,1,25) are calculated by the same method, and "7" and "3" are obtained on the register file 202, respectively. The degree of improvement D (112) is B (5) + B (12) -A (5)
-A (12) is calculated, and the result "3" is stored in the register file 203.

The processors 101, 102, 103, ... Perform similar calculations in parallel to obtain D (101), D (102), D (103) ,.

(Iv) Replacement partner node calculation phase This will be described with reference to FIG. Improvement degree D (101), D (10
2), D (103), ... Are stored in the processors 101, 102, 103, respectively. By connecting the switching elements 303 to 311 and disconnecting the others, the degree of improvement D (101), D (103), D (105), ... Held by the processors 101, 103, 105 ,.
2), (4,1), (2,2), ... are processors 102, 104, 1 respectively
Transfer to 06, ... in parallel and store in each processor. Processors 102, 104 and 106 are D (101) and D (102), D (103) and D
Since it has (104), D (105) and D (106), ..., The arithmetic circuit 208 is used to compare the sizes, and the larger one is used as the new D (10).
2), D (104), D (106), ... Processor 102,10
4, 106 ... As node positions, D (101), D (103), D (1
05) ... and old D (102), old D (104),
Since there are those corresponding to the old D (106) ..., those corresponding to the new D (102), new D (104), new D (106) ,. Next, by connecting the switching elements 312 to 316 to each other and disconnecting the others, the same data is transferred in parallel from the processors 102, 106, 110, 114, ... To the processors 104, 108, 112, 116 ,. ~ 104,105 ~ 108,109 ~ 112,1
The node position corresponding to the maximum value of the improvement degree D of 13 to 116 can be obtained on the processors 104, 108, 112, 116 ,. By repeating the above, it is possible to obtain the node position (X _m , Y _m ) corresponding to the maximum value of the improvement degree D of all the processors on the processor 116. In this way, the node having the position (X _m , Y _m ) is selected as the replacement partner node.

(V) Interchange phase By connecting all the switching elements 303 to 323 of the exchange unit 118, (X _m , Y _m ) is transferred to all the processors. Since each processor has the position of the exchange node (2,2) and the position of the exchange partner node (X _m , Y _m ), until now (2,2)
The position information has a 2) (X _m, rewritten Y _m), rewritten until now (X _m, the position information was Y _m) to (2,2).

Next, the “identification number of the processor including the exchange node” and the “repetition number” stored in the storage of the control unit 119 are updated. If the number of repetitions is less than or equal to the upper limit,
Repeat (ii) to (v).

(Vi) Resulting output phase When the number of repetitions reaches the upper limit, the node position stored in each processor is the final arrangement. Therefore, set the switching elements 303 to 333 of the exchange unit appropriately,
The node positions are transmitted to the outside in order from the processors 101, 102, 103, ..., 117.

In the present invention, if the number of processors is equal to or larger than the number of nodes whose layout is to be determined, the maximum speed can be achieved, but there is also a method of sequentially allocating a plurality of nodes to one processor. The present invention is not limited to the above-described embodiments, and it goes without saying that various additions and modifications can be made.

(Effect) As described above, the present invention is a method for improving the arrangement by using a parallel processing device and replacing all the nodes with each other. The process of improving the placement of all the nodes as replacement partners is roughly divided into "a process of calculating the degree of improvement by replacement", "a process of calculating a replacement partner with the maximum improvement", and "a process of actually replacing". It In the process of calculating the degree of improvement due to replacement, one processor is assigned to one node for parallel processing, and the processing such as x-coordinate, y-coordinate, and net identification number is also performed in parallel within the processor. Parallel processing is performed. In the process of calculating the replacement partner with the maximum degree of improvement and the process of actually replacing, a switching unit having a binary tree structure is used, so that it is possible to perform communication between a number of processors in parallel, and to all cells. Since the transfer distance is short, it can be broadcast at high speed. Conventionally, these processes have been sequentially performed by a general-purpose computer, so that there is an advantage that the processing time is significantly shortened by this device.

Further, compared with the method of improving the placement by limiting the replacement partner node to the upper, lower, left, and right adjacent nodes, the method of the present invention makes all the nodes as replacement partners, and actually selects the pair with the largest improvement degree among the possible replacement pairs. Since the steepest descent method that replaces nodes is adopted, there is an advantage that a high quality final arrangement can be obtained.

[Brief description of drawings]

1 to 4 are explanatory views of the arrangement improvement processing procedure, and FIG. 5 is a block diagram showing a main configuration of a conventional device,
FIG. 6 is a block diagram of an embodiment showing a configuration of a main part of a processing device used in the present invention, and FIG. 7 is a block diagram of an embodiment showing details of the configuration of the processor shown in FIG. FIG. 8 is a block diagram of an embodiment showing a detailed structure of the exchange unit shown in FIG. 1 ... Cell, 2 ... Address decode circuit, 3 ... Address data line, 4 ... Cell selection line, 5 ... Inter-cell data path, 6 ...
Data path, 7 ... Control unit, 8 ... Data input / output line,
9-12 ... Clock line, 101-117 ... Processor, 118 ... Exchange unit, 119 ... Control unit, 120-137 ... Data signal line, 140 ... Data input / output line, 201 ... Register, 202-207
... register file, 208-210 ... arithmetic circuit, 211 ... control circuit, 212-214 ... signal bus, 215 ... control signal line, 216-21
8 ... Matching signal line, 219 ... Sign bit line, 301 ... Control circuit, 3
02 ... Control signal line, 303-323 ... Switching element,-
…node.

Claims (1)

[Claims] 1. An arithmetic circuit having both addition and subtraction and a coincidence determination function, a processor comprising a plurality of storage elements whose writing can be controlled by the output of the arithmetic circuit, and a vertex of a binary tree replaced by a switching element, An exchange unit having a configuration in which a branch is replaced with a wiring, a control unit for generating a control signal that defines the operation of the processor and the exchange unit and controlling the entire process, and between the plurality of processors and the exchange unit A data transfer line for transferring data between the control unit and the exchange unit, and a control signal line for transmitting a control signal from the control unit to the exchange unit and the processor. By using the processing device, the processor can pre-set the module and its module as initial placement data. The position of the module having a connection relationship with and the identification number of the connection signal line are stored, the state of the exchange unit is appropriately set based on the control signal from the control unit, and the module is transferred from one processor to all processors. The position of and the number of the connecting signal line are transmitted, and with this,
From the module position unique to each processor and the identification number of the connection signal line, calculate the reduction amount of the evaluation value when the module is replaced using the arithmetic circuit according to a predetermined evaluation reference calculation method, and set the replacement unit appropriately. Then, the evaluation value decrease amount and the module position are transferred to other processors in a binary tree form, and the evaluation value decrease amount and the evaluation value decrease amount specific to each processor are compared using the arithmetic circuit. The module position corresponding to the maximum evaluation value decrease amount is calculated by repeating the process of selecting the larger evaluation value decrease amount and the position of the module to be given to it, and the replacement unit is re-set appropriately and the module position is changed. To all processors and repeat the process of exchanging the module position and the position of the module notified to all processors at the beginning of the series of processes. Arrangement determination method characterized by obtaining data.