JPH06105285A - Reproducer - Google Patents

Abstract

PURPOSE:To attain a reproduction by letting alternating components be '0' and decoding only direct current components at the time of reproduction. CONSTITUTION:Reproduction data turned into a format are inputted from an input port 21, and recorded once in an FRAM 22. Next, the data recorded in the FRAM 22 are separated between the direct current components and the alternating components, and recorded in a DRAM 23 and an ARAM 29. At the time of recording the alternating components recorded in the FRAM 22 in the ARAM 29, when the code words of undefined words are detected by an undefined word detector 1, the code words are held by a selector 2 and registers 3 and 4 until the DRAM 23 and the ARAM 29 are read. The held output signal of the register 4 and the alternating components of the sampling signals of the direct current components generated from a control part 6 are turned to '0' by using the control signal of a selector 5, only the direct current components are decoded by a variable length decoding part 31, inverse quantized by an inverse quantizing part 32, and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for reproducing data recorded by variable-length coding image information and audio information.

[0002]

2. Description of the Related Art In recent years, digital recording / reproducing devices for image signals and audio signals have been demanded in the market. However, since the image signal has a very large data amount, high-efficiency coding is often used to reduce the data amount when transmitting or recording. High-efficiency coding is a means for compressing the amount of data by removing the redundant component of the image signal. As a high-efficiency encoding method, there is a method in which an input sample value is first divided into blocks composed of a plurality of adjacent pixels, orthogonal transformation is performed for each block, and encoding is performed for each orthogonal transformation. In these high-efficiency coding methods, generally, the orthogonal components are quantized and variable-length coded for transmission.

The variable length coding is a method of coding a signal having a high frequency of occurrence into a code word having a small number of bits and coding a signal having a low frequency of occurrence into a code word having a large number of bits. This makes it possible to transmit data with a small number of bits on average. Therefore, in the conventional apparatus for recording or transmitting an image signal or an audio signal, the variable length coding as described above is used to reduce the data amount before recording / reproducing.

However, when variable-length coding is used, if even one bit error occurs, code synchronization is lost, and it becomes impossible to decode the variable-length code words thereafter. Therefore, in the conventional device, the influence of the transmission path error is very large, and a large amount of error correction code and reset signal are required to prevent it.

Therefore, a method for improving such a problem by a format at the time of recording has been proposed by the inventors (Japanese Patent Application No. 2-404863). FIG. 4 is an explanatory diagram of a format in which even if an error occurs, the error does not affect other small blocks. FIG. 4 shows DCT (Di
The small block corresponds to the basic unit (DCT block) for executing DCT. FIG. 4A shows the ratio of the data amount after the components of the three small blocks after the conversion are subjected to the variable length coding. Since the amount of data after variable length coding depends on the input information, the amount of data is different for each block as shown in FIG. Therefore, if an error occurs in the first small block and the variable-length code synchronization is lost, the head positions of the second and third small blocks cannot be detected, and the data of all three small blocks cannot be decoded. On the contrary,
In FIG. 4B, first, the data area after variable length coding is divided into three fixed recording blocks. Then, from the DC component (DC component) of each DCT block to the variable length code word representing the low frequency band of the AC component (AC component), writing is sequentially performed from the beginning of the corresponding recording block. When the number of remaining bits of each recording block becomes smaller than the maximum code length of the variable length coding used therein, writing is once stopped there. By doing this,
A series of variable-length codewords written from the beginning of the recording block will not be divided in the middle of the codewords.
Next, at this stage, the variable-length codeword not written in the recording block is recorded in the remaining area including other recording blocks. Therefore, only the code word representing a high frequency band that is not visually significant is written in a recording block other than the corresponding recording block (a portion indicated by "H" in FIG. 4B). With this format, 1
Even if an error occurs in one small block, the other small blocks can resume decoding from the beginning of the recording block, so that the influence of the error can be minimized.

By the way, as a means for realizing the above format, the inventors have proposed in the invention of Japanese Patent Application No. 4-54936. A brief description of this means is as follows.

FIG. 5 is a block diagram for realizing the above format. In FIG. 5, reference numeral 21 is a reproduction data input port, 22 is a first memory, FRAM, 2
3 is a second memory D for storing the DC component
RAM, 24 is a switch, 25 is a shifter, 26 is a selector, 27 is a register, 28 is a code length detector, and 29 is A.
ARA, which is the third memory for storing the C component
M and 30 are selectors, 31 is a variable length decoding unit, 32 is an inverse quantization unit, 33 is a control unit, and 34 is an output port. For the sake of simplicity, the maximum code length of the variable length code is set to 16 bits and the input / output bit width of FRAM and ARAM is set to 16 bits. Similarly, the bit width of the DC component is set to 11 bits, and the input / output bit width of the DRAM described below is set to 11 bits. In addition, as the processing described above, three recording blocks (DCT1, DCT) shown in FIG.
2, DCT3) is treated as one large block, the large block unit is called a video segment, and the signal indicating the start of processing of the video segment is the video segment start. Here, when the video segment start is "0", the head of the large block is input from the input port 21. Therefore, the data formatted as shown in FIG. 4B is separated for each DCT block and the DRAM 23 is separated.
And to write to ARAM29, first write FRA once.
Writing to M22 Next, the data written to the FRAM22 is stored in the DRAM component for the DC component and ARA for the AC component.
Write to M29. As a writing procedure, the DC component is first written, and then the low frequency part of the AC component is written.
When the writing of all the low-frequency parts of the AC components is completed in the block, the high-frequency part is separated next, and AR is set for each DCT block.
It is necessary to write in AM29. Each RA in Figure 6
The timing of the process of writing to M is shown. In the figure,
(A) is video segment start, (b) is FRAM
22 input, (c) output of FRAM22, (d) D
It is an output of the RAM 23 and the ARAM 29. As shown in FIG. 6, the reproduction data input from the input port 21 is once recorded in the FRAM 22 in synchronization with the first video segment start signal generated from the control unit 33, and is synchronized with the second video segment start signal. FRAM2
Data is output from 2.

FIG. 7 shows a schematic diagram of the FRAM 22. Figure 7
The following will be described using the data of the FRAM 22 shown in FIG. First, the operation of transferring the DC component from the FRAM 22 to the DRAM 23 will be described. As shown in FIG. 7, the DC component (hatched portion) is
It is 11 bits from the beginning of each recording block. That is, by connecting the lower 11 bits of the FRAM 22 to the input terminal of the DRAM 23 and controlling the writing of the DRAM 23 by the control unit 33, the data of the FRAM 22 is transferred to the DRAM 23.
Can be realized.

Next, the operation of moving the low-frequency part of the AC component from the FRAM 22 to the ARAM 29 will be described. By switching the switch 24, the data in the FRAM 22 is input to the register 27 via the shifter 25 and the selector 26. However, since the 11-bit DC component is recorded at the beginning of each recording block, when the beginning of each recording block is read, the first codeword (P) of the AC component is recorded.
Starts from the 12th bit of FRAM22. Therefore, the code word (P) is the least significant bit (LS) of the register 27.
It is the data from the 12th bit counted from B). Therefore, in order to detect the code length, the code length detection unit 28 can detect the code length by extracting 16 bits from the 12th bit. The head of the next code word (Q) can be detected by adding the detected number of code lengths to the point (the 12th bit) that has started to be extracted in order to detect the code length. That is, by similarly extracting 16 bits from that point, it is possible to detect the code length of the variable length codeword at each time. At the same time, the code length detected by the code length detection unit 28 detects up to which position in the recording block the data is read in variable length codeword units. In this way, the sequence of variable-length codewords in the register 27 is 1
When the number of bits exceeds 6 bits, the upper 16 bits of the register 27 are written in the ARAM 29. When the code length detection unit 28 detects that the number of remaining bits of the recording block becomes smaller than 16 bits (when the code word R is written), the upper 16 bits of the register 27 are set to the ARAM 29.
To the DCT block, and the processing of the low frequency part for the DCT block is finished. By executing such processing for each DCT block, it is possible to transfer the low-frequency part of the AC component from the FRAM 22 to the ARAM 29.

Next, the operation of moving the high frequency part of the AC component from the FRAM 22 to the ARAM 29 will be described. In order to move the high-frequency part of the AC component from the FRAM 22 to the ARAM 29, it is necessary to mix the low-frequency part variable-length codeword and the high-frequency part variable-length codeword in one word (16 bits) on the ARAM 29. . Therefore, it is necessary to first take out the last code word of the variable length code word representing the low frequency band which is currently written in the ARAM 29, connect the variable length code representing the high frequency band without a space behind it, and then write it in the ARAM 29 again. is there. Therefore, by switching the switch 24, the FRAM
The data 22 is input to the register 27 via the shifter 25 and the selector 26. In the shifter 25, the register 2
The variable length code word representing the high band that has been input is shifted so that the variable length code word representing the low band already stored in 7 can be connected without a gap. The shifted variable-length codeword is mixed with the variable-length codeword representing the low frequency output from the register 27 by the selector 26 and input to the register 27. Further, similarly to the above-described writing in the low-frequency part, the code length is detected by the code length detection unit 28, and it is detected to which position of the recording block the data has been read in variable length codeword units.
Data is written in the RAM 29. In this way, the same processing is repeated until the remaining space in each recording block is exhausted. Further, when all the variable length code words for a certain DCT block are written in the middle of the processing, the processing is once stopped and the high frequency variable length code word of the next DCT block is written by the same method. In this way, the AC component data separated for each DCT block is recorded on the ARAM 29.

Therefore, the DC component and the AC component for each DCT block can be separated from the FRAM 22 by the above-described method, and can be recorded in the DRAM 23 and the ARAM 29.
As described above, the DC component and the AC component separated for each DCT block are output from the DRAM 23 and the ARAM 29 in synchronization with the third video segment start signal, and the variable length decoding unit 31 outputs the variable length using the selector 30. The data is decoded, inversely quantized by the inverse quantizer 32, output from the output port 34, and reproduced.

[0012]

However, the FRAM2
If there is an error in the data recorded in 2, ARAM
When transferring the AC component to 29, an undefined codeword may be detected. That is, an error occurs in the code length detection unit 28, and AC component data for each DCT block is not correctly recorded in the ARAM 29. Therefore, even when reproduction is performed by the above-mentioned means, when an error occurs in one small block, decoding can be restarted from the head of another small block, but the block after the error is defined The codeword that has not been encoded is the variable length decoding unit 31.
It will be decoded with and the block will have noise.
Therefore, flicker is noticeable in the reproduced image, which is a visual problem.

An object of the present invention is to solve the problems of the conventional reproducing apparatus.

[0014]

In order to solve the above conventional problems, the reproducing apparatus according to the present invention has the following configuration. That is, a plurality of pixels of image or audio signals are collected to form a small block, the inside of the small block is frequency-converted, and the DC component (DC) obtained by the frequency conversion is obtained.
Component) and alternating-current component (AC component) are quantized respectively, and then variable length coding is performed to reproduce the variable length code word from a recording medium recorded according to a predetermined format, and a predetermined number of the blocks. Playback means for collecting and playing back the variable length codewords, undefined word detection means for determining whether the played back variable length codewords are defined variable length codewords, and definition by the undefined word detection means When an undefined codeword is detected, at least the entire small block in which the undefined codeword is detected or the AC corresponding to the codeword in the small block after the undefined codeword is detected It is characterized by comprising a decoding means for setting a component to a predetermined value.

[0015]

According to the present invention, when a code word not defined by the above configuration is input, it is detected by the undefined word detector and the AC component (AC component) is forcibly set to "0", and the DC component (DC component). Only decrypt.

[0016]

1 is a block diagram of a reproducing apparatus according to an embodiment of the present invention. In the present embodiment, the operation in the case of the defined code word is almost the same as that of the conventional device described above, and therefore the blocks having the same functions as those described below are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, 1 is an undefined word detector, 2 is a selector, 3 is a register, 4 is a register, 5 is a selector, 6 is a control unit, 21 is a reproduction data input port, and 22 is a first memory FRAM. , 23
Is a second memory for storing the DC component, DR
AM, 24 is a switch, 25 is a shifter, 26 is a selector, 27 is a register, 28 is a code length detector, and 29 is AC.
ARAM, a third memory for storing the components,
Reference numeral 31 is a variable length decoding unit, 32 is an inverse quantization unit, and 34 is an output port. The following description shows the case where an undefined code is input. By the way, when an undefined code word is detected, the flicker of the reproduced image can be reduced by setting the AC component to a predetermined value. Here, a method of forcibly setting the AC component to “0” and reproducing only the DC component when an undefined codeword is detected will be described.

AC component is transferred from FRAM 22 to ARAM 29
When moving to, by switching the switch 24,
The data in the FRAM 22 is input to the register 27 via the shifter 25 and the selector 26. At the same time, the code length detector 2
At 8, the code length of the variable length codeword is detected from the data of the register 27 at each time, and the undefined word detector 1 determines whether or not the variable length codeword is defined. If the code word is an undefined word, "1" is output. Once an undefined variable-length codeword is detected, subsequent ARA
An error occurs in the AC component recorded in M29. Therefore, when "1" is output from the undefined word detector 1, it is input to the register 3 via the selector 2 and held at "1" until the third video segment start occurs. The signal output from the register 3 is delayed by one video segment in the register 4 in order to match the timing.

FIG. 2 shows the above timing. In the figure, (a) is the system clock, (b) is the video segment start, (c) is the output of the undefined word detector 1,
(D) is the output of the register 3, and (e) is the output of the register 4. By the way, the output of the register 4 shown above is
The timings match the outputs of the DRAM 23 and the ARAM 29 shown in FIG. Therefore, by using the control signal of the selector 5, the AC component output from the ARAM 29 can be forcibly set to "0".

FIG. 3 shows the control of the selector 5. In FIG. 3, (a) is a schematic diagram of the selector 5, and (b) is the selector 5.
It is the figure which showed the logic of. As shown in FIG. 3B, the control signal D (output of the register 4) and E (DC component sampling signal: output from the control unit 6) determine which signal is selected. As can be seen from the logic of FIG. 3B, when the control signal E is "1", the DRAM 2 is always
Select the output value of 3. When the control signal E is "0", the output of the ARAM 29 is selected,
At this time, if the control signal D is "1", that is, the undefined word detector 1 has detected an undefined word. Therefore, by selecting the input signal C (GND),
This is the same as forcibly setting the output of the ARAM 29 to "0". That is, the code word indicating the AC component is forcibly set to "all 0". Further, the variable length decoding unit 31
If the code word is "all 0", the signal to be decoded outputs "0". Therefore, the reproduced signal output through the dequantization unit 32 has an AC component of "0", that is, a DC component.

As described above, according to this embodiment, when a variable length code word of an undefined word is detected during reproduction,
By providing the undefined word detector 1, the AC component is forcibly set to “0” and only the DC component is decoded,
If an error occurs in two small blocks, the flicker of the reproduced image can be reduced.

In the present embodiment, the case where the maximum code length of the variable length code is 16 bits has been described, but the present invention can be applied to a variable length code having any other maximum code length. At the same time, regarding the format,
It can be applied to formats other than (b), and can also be realized for an arbitrary number of small blocks. In addition, in the actual circuit configuration, various configurations other than the above of the present invention are possible.

[0022]

According to the present invention, when an error occurs in one small block, the AC component is forcibly set to "0" and D
By decoding only the C component, it is possible to prevent the reproduced image from flickering, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a reproducing apparatus of the present invention.

FIG. 2 is a timing chart of registers 3 and 4 when a variable length codeword of an undefined word is detected by an undefined word detector.

FIG. 3 is a diagram showing control of a selector 5.

FIG. 4 is a distribution diagram of an explanatory diagram of formatting.

FIG. 5 is a block diagram of a conventional playback device.

FIG. 6 is a diagram showing write and read timings of FRAM, DRAM, and ARAM.

FIG. 7 is a schematic diagram of FRAM.

[Explanation of symbols]

 1 undefined word detector 2 selector 3 4 register 5 selector 6 control unit 22 FRAM 23 DRAM 24 switch 25 shifter 26 selector 27 register 28 code length detection unit 29 ARAM 31 variable length decoding unit

Claims (1)

[Claims] 1. A small block is formed by collecting a plurality of pixels of image or audio signals, frequency conversion is performed in the small block, and a DC component and an AC component obtained by the frequency conversion are respectively quantized and then a variable length is obtained. Reproducing means for reproducing the variable length code word from a recording medium which is encoded and recorded in accordance with a predetermined format; reproducing means for collecting a predetermined number of the blocks to reproduce the variable length code word; Undefined word detection means for determining whether the variable length codeword is a defined variable length codeword, and at least an undefined code when a codeword not defined by the undefined word detection means is detected The AC component corresponding to the entire small block in which the word is detected or the code word in the small block after the undefined code word is detected is set to a predetermined value. Reproducing apparatus, comprising the Goka means.