JPH06103374A - Picture scaling device - Google Patents

Abstract

PURPOSE: To provide a picture scaling device in which the scaling of a picture can be efficiently operated in a real time. CONSTITUTION: This is a picture scaling device 10 provided with a scaler circuit 14 which receives a picture signal (IM) indicating a pixel array and plural scaling parameters, operates the pixel array, and supplies the operated pixel array as a scaled picture, and a scaler control circuit 12 which supplies the plural scaling parameters based on a desired scaling ratio.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to multimedia computer systems, and more particularly to scaling of image signals used in multimedia computer systems.

[0002]

2. Description of the Related Art A multimedia computer system is an information processing system that combines the information processing characteristics of conventional computer systems with high quality video and audio representations. The video representation is provided by the video display device and the audio representation is provided by the audio output device.

A multimedia computer system has a media source that produces a media signal. The media signal includes an audio signal supplied to the audio output device and an image signal supplied to the video display device. The image signal may include a graphic signal, a text signal, an animation signal and a moving image signal. The image signal is converted into a video representation by the display device. The display device receives the image signal and scans it as a raster pattern on the screen of the display device.

The speed at which the display device scans the image is called the sweep speed. The display screen has a horizontal resolution and a vertical resolution that define the display screen coordinates of the display device. Each coordinate of the display device is one pixel. A representation that consists of one complete scan of the screen is called a frame, or
Or in the case of interlaced scanning, it is called a field.
To provide a single moving image representation, the display device generates multiple frames per second.

Scaling of the image represented by the image signal is often required to display (window) the image on a portion of the display screen. Image scaling allows that image to be displayed simultaneously with other images. An example of a system that uses a scaling device is the multimedia system disclosed in US patent application Ser. No. 07 / 625,564 filed Dec. 11, 1990.

It is well known to scale an image by removing some pixels from the image signal. For example, U.S. Pat. No. 4,412,252 discloses a method of removing pixels along a line to reduce the width of an image and a method of removing multiple lines to reduce the height of an image. As another example, a method of scaling an image by performing multiplication on an image signal using an image extraction sequential circuit is well known.

[0007]

Conventionally, in order to perform efficient image scaling in real time (that is, image refresh rate), a complicated circuit configuration has been required.

The object of the present invention is real-time (that is, image refresh rate) with a simple hardware configuration.
In order to efficiently scale the image in, it is to provide a scaling device which receives an array of pixels and performs a plurality of operations on these pixels according to a predefined reduction parameter.

[0009]

To achieve the above object, the scaling device of the present invention includes a scaler circuit,
The circuit receives an image signal representing a pixel array and a plurality of scaling parameters, and operates the pixel array based on these parameters to provide a manipulated pixel array representing a scaled image.

It would be further advantageous to have a scaler control circuit configured to provide a plurality of scaling parameters based on the desired scaling rate.

[0011]

A plurality of scaling parameters are supplied by the scaler control circuit by inputting one pixel array corresponding to a desired scaling rate and one image to the image scaling device configured as described above,
Inputting a plurality of said scaling parameters and a pixel array into a scaling circuit outputs an engineered pixel array representing a scaled image.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a scaling device 10 for scaling a monochrome image signal (IM) comprises a scaler control circuit 12 and a horizontal component scaling circuit 14 (h) and a vertical component scaling circuit which will be collectively referred to as a component scaling circuit 14 below. 14 (v). Scaler control circuit 1
2 receives control information and provides scaling control signals. These scaling control signals include scaling parameters based on the desired scaling rate.
The scaling parameters are generated, for example, by a look-up table. The control information includes timing information as well as desired scaling rate information. The scaler control circuit 12 supplies a scaling parameter corresponding to the scaling rate to the horizontal component reduction circuit 14 (h) and the vertical component reduction circuit 14 (v) as a part of the control information. The horizontal scaling circuit 12 (h) also receives an IM image signal containing the pixel array of the image to be scaled. The array has rows and columns of pixels. The horizontal scaling circuit 14 (h) operates a row of IM signals by performing a plurality of operations on the IM image signals based on the scaling parameters, and further scales an intermediate image signal (HSIM) in the horizontal direction. Is supplied to the vertical component scaling circuit 14 (v). The vertical component scaling circuit 14 (v) operates on a column of pixels of the HSIM signal by receiving the HSIM signal and performing a plurality of operations on the HSIM signal based on the scaling parameters to further indicate an array of manipulated pixels. Providing a scaled image signal (SIM). The array of manipulated pixels corresponds to a scaled representation of the IM signal. In FIG. 2, the horizontal component scaling circuit 14 (h) receives an input circuit 20 for receiving and synchronizing an image signal to be scaled with a clock signal related to the image signal, and a scaling parameter from the scaler control circuit 12 from the input circuit 20. A control circuit 22 for receiving a clock signal and generating a signal operation control signal
A signal manipulation circuit 24 for manipulating the synchronous image signal based on the signal manipulation control signal supplied from the control circuit 22 and an output circuit 26 for appropriately conditioning the scaled image signal to provide a suitable output modality. Including and The output circuit 26 of the horizontal component scaling circuit 14 (v) includes a driver for driving a horizontally scaled image signal to the vertical component scaling circuit 14 (v).

The vertical component scaling circuit 14 (v) is
It is structurally similar to the horizontal component scaling circuit 14 (h). However, the output circuit 26 of the vertical component scaling circuit 14 (v) has a digital-to-analog converter (not shown) to convert the scaled image signal into a suitable format for display on a display device. .

In FIG. 3, the control circuit 22 has a parameter control circuit 30 which receives a plurality of scaling control signals as input control signals from the scaler control circuit 12.
The input control signal is a pixel clock signal (PIXE).
L CLK), a load register signal (IOW), an enable signal (F) that enables the read / write signal based on decoding of the load address, and two address selection bits (A0) indicating the least significant bit of the load address.
And A1) and a blanking signal which is a timing signal indicating that the display device is in a blanking period.
Further, the control circuit 22 includes a deletion circuit 32, a holding circuit 34,
It has a dual circuit 36 and a quad circuit 38 which receive the delete control signal, the hold control signal, the dual control signal and the quad control signal, respectively, simultaneously with the PIXEL CLK signal from the control circuit 12. Delete, hold, dual and quad signal scaler control circuit 1
2 is the scaling parameter supplied by. The deletion circuit 32 has a deletion register 40 and a deletion counter 41. The holding circuit 34 has a deletion register 42 and a holding counter 43. The dual circuit 36 has a dual register 44 and a dual counter 45. The quad circuit 38 has a quad register 40 and a quad counter 47. Registers 40, 42, 4
Reference numerals 4 and 46 are ordinary 8-bit registers. Counter 4
1, 43, 45, 47 are normal loadable 8-bit
It is a down counter.

The deletion circuit 32 is a parameter control circuit 30.
An 8-bit deletion count signal (DROP CNT) as an input control signal to the deletion feedback signal (DROP CNT) indicating when the DROP CNT signal becomes equal to 0.
Z) is supplied. The holding circuit 34 holds an 8-bit holding count signal (KEEP CNT) as an input control signal to the parameter control circuit 30 and a holding feedback signal (KEEP) indicating when the KEEP CNT signal becomes equal to 0.
Z) is supplied. The dual circuit 36 receives the 8-bit dual count signal (DUAL CNT) as an input control signal to the parameter control circuit 30, and the dual circuit 36.
A dual feedback signal (DUALZ) is provided which indicates when the CNT signal is equal to zero. The quad circuit 38 is
As an input control signal to the parameter control circuit 30, a quad feedback signal (QUAD) indicating when the count supplied by the counter portion of the quad circuit 38 is equal to zero.
Z) is supplied.

The parameter control circuit 30 includes a deletion circuit 3
2. Provides a plurality of output signals including counter initialization signals (INITCTR) supplied to counters 41, 43, 45 and 47 of holding circuit 34, dual circuit 36 and quad circuit 38. The other output signal provided by the parameter control circuit 30 is the delete register load signal (L
DDR), a delete counter decrement signal (DECDC) supplied to the delete circuit 32, and a holding register load signal (LDK).
R), a holding counter decrement signal (DECKC) supplied to the holding circuit 34, a dual register load signal (LD
DAR), a dual counter decrement signal (DECDAC) provided to the dual circuit 36, a quad register load signal (LDQAR), and a quad counter decrement signal (DECQAC) provided to the quad circuit 38.

The parameter control circuit 30 also outputs a passage instruction signal (PASS) for instructing when a pixel can pass through the signal operation circuit 24, and a 2-bit output for controlling the operation of the signal by the signal operation circuit 24. Selection signal (OU
TSEL) and a valid output pixel signal (VALI) which indicates when the next processing, supplied with the scaled image signal, can read this scaled image signal.
A plurality of signal manipulation output signals, including D).

Parameter control circuit 30 includes a plurality of programmable array logic integrated circuits (PALs) that provide output signals based on input signals. The PAL is programmed by PAL equations, each PAL equation corresponding to a circuit that produces a particular output signal. In the PAL equation, "/" indicates a logical inversion, "=" indicates an asynchronous equal sign, and ": =" indicates a signal synchronized by a flip-flop that operates using the pixel CLK signal as a clock signal. Specifically, the PAL equation for the INITCTR signal is as follows.

INITCNT = (BLNK AND / A AND / B) OR (DR
OP1 AND KEEPZAND DUALZ AND QUAD AND / A AND / B) OR
(DROPZ ANDKEEP1 AND DUALZ AND QUADZ AND / A AND / B)
OR (DROPZAND KEEPZ AND DUALZ AND QUADZ AND / A AND
/ B) OR (DUAL1 AND QUADZ AND / A AND / B) OR (QUADZ A
ND A AND / B); where DROP1 = / DROP CNT (7) AND / DROP CNT (6) AND / DROPCNT
(5) AND / DROP CNT (4) AND / DROP CNT (3) AND / DROPCNT
(2) AND / DROP CNT (1) AND DROP CNT (0); KEEP1 = / KEEP CNT (7) AND / KEEP CNT (6) AND / KEEPCNT
(5) AND / KEEP CNT (4) AND / KEEP CNT (3) AND / KEEPCNT
(2) AND KEEP CNT (1) AND KEEP CNT (0); DUAL1 = / DUAL CNT (7) AND / DUAL CNT (6) AND / DUALCNT
(5) AND / DUAL CNT (4) AND / DUAL CNT (3) AND / DUALCNT
(2) AND / DUAL CNT (1) AND DUAL CNT (0); A: = B AND DUALZ AND / QUADZ; and B: = (DUALZ AND / QUADZ AND / A AND / B) OR (/ BLNK AN
DDROPZ AND KEEPZ AND / DUAL AND / A AND / B) OR (/ BLNK
AND DROPZ AND KEEPZ AND / QUADZ AND / A AND / B).

The PAL equation for the LDDR signal is LDDR = IOW AND F AND A1 AND A0.

The PAL equation for a DECDC signal is DECDC = / BLNK AND / DROPZ AND / A AND / B, where A and B are as defined above.

The PAL equation for the LDKR signal is LDKR = IOW AND F AND A1 AND / A0.

The PAL equation for the DECKC signal is DECKC = / BLNK AND / KEEPZ AND DROPZ AND / A AND / B, where A and B are as defined above.

The PAL equation for the LDDAR signal is LDDAR = IOW AND F AND / A1 AND A0.

The PAL equation for the DEC DAC signal is DECDAC = / A AND B AND / DUALZ, where A and B are as defined above.

The PAL equation for the LDQAR signal is LDQAR = IOW AND F AND / A1 AND / A0.

The PAL equation for the DECQAC signal is DECQAC = A AND B, where A and B are as defined above.

The PAL also controls the generation of signal manipulation control signals. Therefore, the PAL equation for the PASS signal is PASS = A AND B.

The PAL equation for the OUTSEL (1) signal is OUTSEL (1) = A AND / B.

The PAL equation for the OUTSEL (2) signal is OUTSEL (2) = / A AND B AND / DUALZ.

The PAL equation for the VALID signal is VALID: = A AND / B OR / DUALZ AND / A AND / B OR / BLNK
ANDDROPZ AND / KEEPZ AND / A AND / B.

The control circuit 22 operates together with the signal operation circuit 24 based on the states of the signal operation control signal and the clock signal. 4, the signal operation circuit 24 includes an adder circuit 50 that receives an IM signal synchronized with a clock, and an adder circuit 5.
Output from 0 and parameter control circuit 3 of control circuit 22
Shifter circuit 5 for receiving OUTSEL control signal from 0
2 and the output signal from the shifter circuit 52 and PIXEL
It includes a register circuit 54 for receiving the CLK clock signal and a zeroing circuit 56 for receiving an output signal synchronized with the clock from the register circuit 54 and a PASS control signal.
The zeroing circuit 56 supplies a second input to the adding circuit 50.

In FIG. 1, scaler control circuit 12 receives control information indicating the rate at which the image should be scaled (ie, the scaling rate) in operation. The scaler control circuit 12 supplies four scaling parameters to the component scaling circuits 14 (h) and 14 (v) based on the desired scaling rate: delete parameter, hold parameter, dual parameter, and quad parameter. For example, if the desired scaling ratio is 3/4 of the original image, the scaling parameters are DROP = 0, KEEP = 2, DUAL = 1.
And QUAD = 0. If the desired scaling ratio is 1/5 of the original image, the scaling parameters are DROP = 1, KEEP = 0, DUA
L = 0 and QUAD = 1. If the desired scaling ratio is 2/3 of the original image, the scaling parameters are DROP = 0, KEEP = 1,
DUAL = 1 and QUAD = 0. The component scaling circuit 14 is also an IM which is a pixel array of one image.
Receive the signal in pixels. The horizontal component scaling circuit 14 (h) receives the IM signal, scales this signal horizontally, and supplies the horizontally scaled image signal HIM to the vertical component scaling circuit 14 (v). The vertical component scaling circuit 14 (v) receives the horizontally scaled image signal and vertically scales the signal to provide a scaled image signal SIM indicative of the manipulated pixel array.

Each component scaling circuit 14 scales along the axis of the array of pixels by performing a combination of four operations on a plurality of pixels on that axis.
That is, the horizontal component scaling circuit 14 (h) scales the abscissa and the vertical component scaling circuit scales the ordinate. The four operations are delete operation, hold operation,
Includes dual operation and quad operation. With a single delete operation, the component scaling circuit 14 deletes one received pixel. With one holding operation, the component scaling circuit 14 holds one pixel received. With a single dual operation, the component scaling circuit 14 averages the two pixels received. With one quad operation, the component scaling circuit 14 averages the four pixels received. Any combination of these four operations can represent any reduction. The frequency with which the operation is performed corresponds to four scaling parameters.

More particularly with reference to FIGS. 1 and 5, the horizontal component scaling circuit 14 (h) is enabled by the scaler control circuit 12 when scaling the horizontal axis of an image. Registers 40, 42, 44, 46
As shown in the initial parameter setting block 79,
They are loaded with delete parameters, retention parameters, dual parameters and quad parameters respectively. More specifically, the delete parameter is loaded into register 40 as a delete count signal when the LDDR signal is active. The hold parameter is loaded into register 42 as a hold count signal when the LDKR signal is active. The dual parameter is loaded into register 44 as the dual count signal when the LDDAR signal is active. The quad parameter is loaded into register 46 as a quad count signal when the LDQAR signal is active. Control is then passed to the blanking signal decision block 80.

When the blanking signal determination block 80 determines that the BLNK signal has become inactive, control is passed to the parameter setting block 82. In the parameter setting block 82, the delete parameter, the hold parameter, the dual parameter, and the quad parameter are loaded into the counters 41, 43, 45, 47, respectively. This is done when an active INTCNT signal is provided by the control circuit 22. Once the scaling parameters are loaded into these counters, the component scaling circuit 14 (h) is ready to begin scaling the image. If the BLNK signal is active, indicating that the display device scan is inactive, the component scaling circuit 14 (h) enters a wait state, ie, loops until the BLNK signal becomes inactive. Counter 4
After 1, 43, 45, 47 have been loaded, control is passed to the delete module 84. The delete module 84 transfers control to the holding module 86 or returns control to the blanking signal determination block 80. The holding module 86 transfers control to the dual module 88 or returns control to the blanking signal decision block 80. The dual module 88 transfers control to the quad module 90 or returns control to the blanking signal decision block 80. Control is returned from the quad module 90 to the blanking signal decision block 80.

More specifically, when control is passed to the delete module 84 in FIGS. 3 and 6, the delete module 84 first determines by the delete count decision block 100 whether the delete count is zero. If the delete count is 0, it indicates that a pixel delete operation should not occur, so the holding module 8
Control is returned to 6.

If the delete count is not 0, it indicates that a pixel delete operation should occur.
Control is passed to the delete operation execution block 102. In the delete operation execution block 102, the parameter control circuit 30
Supplies an active DECDC signal to counter 41 causing counter 41 to decrement the delete count signal. The parameter control circuit 30 sets the VALID signal to inactive, and the pixel counter
Set to the next pixel value in the signal. When an inactive VALID signal is provided by the control circuit 22, the pixel is effectively deleted because it is not read in the next process before the next pixel is provided to the component scaling circuit 14. The signal operation circuit 24 is
If a given pixel is deleted, then no operation is performed on this pixel.

The delete operation execution block 102 passes control to the blanking decision block 104, which determines whether the BLNK signal is active. If the BLNK signal is active, control leaves the delete module 84 and returns to the blanking signal decision block 80. If the BLNK signal is inactive, control is returned to the delete count decision block 100. If the delete count signal is equal to 0,
Control is passed to the holding module 86, or control is passed to the delete operation execution block 102.

Referring to FIGS. 3, 4 and 7, the holding module 86 is controlled when control is passed to the holding module 86.
First, the hold count determination block 110 determines if the hold count is zero. If the hold count is equal to 0, it indicates that a hold operation should not be performed and control is passed to dual module 88.

If the hold count is not 0, it indicates that a pixel hold operation should be performed.
Control is passed to the hold operation execution block 112. In the holding operation execution block 112, the parameter control circuit 30
Supplies an active DECKC signal to the counter 43. In this way, the hold count signal is decreased for the counter 43, and the parameter control circuit 30 receives P
The ASS signal is activated and the VALID signal is activated. When the active VALID signal is provided by the output circuit 26 along with the active PASS signal, the pixel is actually held as it is read in the next process before the next pixel is provided to the component scaling circuit 14.

In the signal manipulation circuit 24, if a pixel is held, that pixel is provided as the first input to the summing circuit 50 and is used as the second input by the nulling circuit 56 when the PASS signal is active. It is added to the supplied zero. The output signal of adder circuit 50 is provided to register circuit 54 where it is provided as an output when the VALID signal becomes active.

The control is from the holding operation block 112 to BLN.
The K signal is passed to the blanking decision block 114 which determines if the K signal is active. If the BLNK signal is inactive, control is returned to the blanking signal decision block 80. If the BLNK signal is inactive, control is passed to the hold count determination block 110. If the hold count signal is equal to 0, control is passed to dual module 88 or control is passed to hold operation block 112.

In FIG. 8, when control is passed to dual module 88, dual module 88 first determines in dual count decision block 120 whether the dual count signal is zero. If the dual count signal is equal to 0, it indicates that no dual operation should be performed and control is passed to the quad module 90.

If the dual count signal is not 0, it indicates that a dual pixel operation should be performed and control is passed to the shift right execution block 122. In the right shift block 122, two consecutive input pixels are added and the sum is shifted to the right. In this way an average of two pixels is created. The right shift block 122 then passes control to the pre-hold processing block 124. In the hold preprocessing block 124, the parameter control circuit 30 supplies the active DECDAC signal. In this way, the dual count signal is reduced to V
Activate the ALID signal. Active VAL
When the ID signal is provided by the output circuit 26, the averaged pixels are read in the next process.

The signal manipulation circuit 24 manipulates the input pixel when the right shift portion of the dual operation is performed. More specifically, the first pixel is supplied to the adder circuit 50, passes through the adder circuit 50 and the shifter circuit 52, and is stored in the register circuit 54. The second consecutive pixel is then fed to the summing circuit 50. Since the PASS signal is inactive, the first pixel stored in the register circuit 54 passes through the zeroing circuit 56 and is supplied to the adding circuit 50 as a second addition input signal. The adder circuit 50 adds the two pixels, and the sum is supplied to the shifter circuit 52. The shifter circuit shifts the sum to the right by one bit based on the state of the OUTSEL signal. This effectively divides by two. However, the remainder from the shifter is truncated.

Dual preprocessing block 124 passes control to blanking decision block 126, where BLNK
Determines if the signal is active. If the BLNK signal is active, control is returned to the blanking signal decision block 80. If the BLNK signal is inactive, control is passed to the dual count decision block 120. If the dual count signal is 0, control is passed to the quad module 90, or control is passed to the right shift execution block 122. Figure 3,
4 and 9, when control is passed to the quad module 90, the quad module first of all determines in a quad count determination block 130 whether the quad count signal is zero. If the quad count signal is equal to 0, it indicates that the pixel quad operation should not be performed and control is returned to the blanking signal decision block 80.

If the quad count signal is not equal to 0, it indicates that a pixel quad operation should be performed and control is passed to the shift right twice shift block 132. The shift right twice execution block 132 adds the inputs of four consecutive pixels and adds the sum to the right by 2
The four pixels are averaged by being bit-shifted. The shift twice right block 132 then passes control to the quad preprocessing block 134. In quad preprocessing block 134, parameter control circuit 30 provides an active DECQAC signal, thereby decrementing the quad count signal and setting the VALID signal.
When one active VALID signal is provided by the output circuit 26, the next process reads the averaged pixel.

The signal manipulation circuit 24 manipulates the input pixel during the double right shift portion of the quad operation. More specifically, the first pixel is supplied to the adder circuit 50, passes through the adder circuit 50 and the shifter circuit 52, and is stored in the register circuit 54. The second adjacent pixel is provided to summing circuit 50. Since the PASS signal is inactive, the first pixel stored in the register circuit 54 passes through the zero circuit 56 and is supplied to the adding circuit 50 as a second input signal. The adder circuit 50 adds the two pixels and supplies the sum to the shifter circuit 52. The shifter circuit passes the sum to the register circuit 54 based on the state of the OUTSEL signal. Since the PASS signal is inactive, the first two pixels stored in the register circuit 54 pass through the zeroing circuit 56 and are supplied to the adding circuit 50 as a second input signal. The adder circuit 50 adds the sum of the first two pixels and the third pixel and supplies the sum to the shifter circuit 52. OU
Based on the state of the TSEL signal, the shifter circuit passes the sum to register circuit 54. Since the PASS signal is inactive, the sum of the first three pixels stored in register circuit 54 passes through zeroing circuit 56 and is provided to summing circuit 50 as a second summing input signal. The adder circuit 50 adds the sum of the first three pixels and the fourth pixel and supplies the sum to the shifter circuit 52. O
Based on the state of the UTSEL signal, the shifter circuit shifts the sum of four pixels to the right by 2 bits. This effectively divides the sum of the four pixels by four and averages the four pixels. The result of this operation is the register circuit 54.
And the result is read from the register circuit when the VALID signal becomes active. However, the remainder from the shifter is truncated.

Quad pre-processing block 124 is BLNK
Determines if the signal is active. What if BLNK
If the signal is active, control is returned to the blanking signal decision block 80. If the BLNK signal is inactive, the quad count decision block 120
Control is passed to. If the quad count signal is equal to 0, control is passed to the blanking signal decision block 80, or right shift execution block 122.
Control is passed to.

When control is passed to the blanking signal determination block 80, if the BLNK signal is still inactive, control is passed to the parameter setting block 82.
When the BLNK signal becomes active, it indicates that one horizontal scan line is completed. Therefore, the horizontal component scaling circuit 14 (h) continues until the BLNK signal becomes inactive again, that is, the next line of the pixel array is A wait state is entered until it is shown to be present for the horizontal component scaling circuit 14 (h).

Referring again to FIG. 1, the horizontal component scaling circuit 14 (h) supplies the horizontally scaled image represented as an HSIM signal to the vertical component scaling circuit 14 (V). The vertical component scaling circuit 14 (V) performs vertical scaling as well as horizontal scaling of the image. More specifically, the input circuit 2 of the vertical component scaling circuit 14 (V)
0 is the HSI from the horizontal component scaling circuit 14 (h).
Receive M signal. Vertical component scaling circuit 14
The (V) input circuit 20 stores the HSIM signal as some pixel rows corresponding to some display rows. When a sufficient number of rows have been stored to manipulate multiple pixels along the vertical axis, the signal manipulation circuit 24 and control circuit 22 manipulate those pixels. The manipulated pixels are provided to the output circuit of the vertical component scaling circuit 14 (V), where the manipulated pixels are assembled in memory to display a screen of scaled display. The scaled output signal SI when the screen is fully assembled, as shown by the vertical blanking signal.
M is supplied to the display device on which the scaled image is displayed.

FIG. 10 shows an alternative scaler circuit that can be used to scale a color image. Further, for example, although the embodiments of the present invention have been described as being realized by hardware, the scaler device according to the present invention may be realized by software which realizes the method shown in the flowcharts of FIGS. 5 to 9. It is possible to

[0054]

According to the present invention, an image can be efficiently scaled in real time (that is, an image refresh rate) with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a scaling device according to the present invention.

2 is a block diagram of a horizontal component scaling circuit of the scaling device of FIG. 1. FIG.

FIG. 3 is a block diagram of a control circuit of the component scaling circuit of FIG.

FIG. 4 is a block diagram of a signal manipulation circuit of the component scaling circuit of FIG.

5 is a flowchart of the operation of the scaling device of FIG.

6 is a flowchart of the operation of the deletion module of the apparatus shown in FIG.

7 is a flowchart of the operation of the holding module of the device shown in FIG.

8 is a flowchart of the operation of the dual module of the apparatus shown in FIG.

9 is a flowchart of the operation of the quad module of the apparatus shown in FIG.

FIG. 10 is a block diagram showing an alternative embodiment of a scaling device according to the present invention.

Claims (15)

[Claims] 1. An apparatus for scaling an image represented by a pixel array, the scaler control circuit configured to provide a plurality of scaling parameters based on a desired scaling factor, said scaler control circuit comprising: A scaled image that receives a plurality of scaling parameters and the pixel array and provides a manipulated pixel array by performing different operations on the plurality of subsets of the pixel array based on the plurality of scaling parameters. And a scaler circuit configured to provide the manipulated pixel array as. 2. A control circuit configured to receive the plurality of scaling parameters and provide a plurality of signal manipulation control signals based on the scaling parameters; and responsive to the plurality of signal manipulation control signals. The scaling device of claim 1, comprising a signal manipulation circuit configured to manipulate the pixel array. 3. A parameter counter circuit configured to receive a given scaling parameter and to provide the parameter control circuit with a parameter count signal and a control signal indicating that the parameter count is equal to zero. Receiving an input control signal including a timing control signal and a scaling enable signal, and a parameter count signal from the parameter count circuit and a control signal indicating that the parameter count is equal to 0, and based on the input control signal the signal operation control The scaling device of claim 2, comprising a parameter control circuit configured to provide a signal and to provide the timing control signal to the parameter counter circuit. 4. The control circuit, based on the scaling parameters and the timing control signal, indicates to the parameter control circuit a plurality of parameter count signals and a plurality of signals indicating that the parameter count is equal to zero. And a plurality of parameter counter circuits for supplying the parameter count signal and the parameter count circuit as an input control signal.
The scaling device of claim 3, configured to receive the plurality of signals indicating equal to. 5. A delete circuit configured to receive a delete scaling parameter and provide a delete count signal to the parameter control circuit and a control signal indicating that the delete count is equal to zero. The scaling device according to claim 4. 6. A holding circuit configured to receive a holding scaling parameter and provide a holding count signal and a control signal indicating that the holding count is equal to 0 to the parameter control circuit. The scaling device according to claim 4. 7. The dual parameter counter circuit is configured to receive a dual scaling parameter and provide a dual count signal and a control signal to the parameter control circuit to indicate that the dual count is equal to zero. The scaling device according to claim 4, which is a circuit. 8. A quad configured for the parameter counter circuit to receive a quad scaling parameter and to provide a quad count signal and a control signal to the parameter control circuit indicating that the quad count is equal to zero. The scaling device according to claim 4, which is a circuit. 9. An adder circuit configured to receive the image signal as a first adder input signal and provide an adder output signal, the signal manipulating circuit, the adder output signal and the first adder output signal. A shifter circuit configured to receive a signal manipulation control signal and provide a shifter output signal, the shifter output signal corresponding to a second adder input signal,
The scaling device according to claim 2, wherein the adder output signal corresponds to a sum of the first adder input signal and the second adder input signal. 10. A register circuit configured to receive the shifter output signal and provide a synchronized shifter output signal, the signal manipulation circuit, the synchronized shifter output signal and a second signal manipulation control signal. 10. The scaling device of claim 9 including a zero circuit configured to receive and to provide a second adder input signal based on the second signal manipulation control signal. 11. The scaler circuit is further configured to provide an input circuit configured to receive an image signal representative of the pixel array and the manipulated pixel array as the scaled image signal. The scaling device according to claim 2, further comprising an output circuit. 12. The scaling device of claim 1, wherein the plurality of different operations includes a delete operation that removes a pixel from the pixel array when providing the manipulated pixel array. 13. The scaling device of claim 1, wherein the plurality of different operations includes a holding operation that continues to hold one pixel of the pixel array when providing the manipulated pixel array. 14. The scaling device of claim 1, wherein the plurality of different operations comprises a dual operation that averages two pixels from the manipulated pixel array. 15. The scaling device of claim 1, wherein the plurality of different operations comprises a quad operation that averages four pixels from the manipulated pixel array.