JPH06100984B2 - Microprocessor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory of a data processing device, and more particularly to a microprocessor supporting a multiprocessor system in which communication is performed by a shared memory or similar means. Also, the present invention relates to a cache memory control circuit suitable for a microprocessor in a system in which the data access frequency is biased.

[Background of the Invention]

A problem that occurs when a cache memory is provided in each processor in a multiprocessor system in which a plurality of processors are combined for load distribution will be described below.

For example, a block diagram of FIGS. 1 and 2 shows an example of a system in which processing is performed while transferring a message between two processors. FIG. 1 shows a processor dedicated local memory 2 and 2'for each processor 1 and 3, respectively.
FIG. 3 is a block diagram of a system including a shared memory 4 for message communication. Normally, each processor 1 or 3 performs processing using the local memory 2 or 2'of its own processor, but when the processor 1 requests the processor 3 to process, the processor 1 is required for processing content and processing. Data is written in a predetermined area of the shared memory 4, and the processor 7 is interrupted. When an interrupt occurs, the processor 3 reads the contents of the shared memory 4 and performs the requested processing. When the processing is completed, the processor 3 writes the result in the shared memory 4 to contact the processor 1, and interrupts the processor 1. afterwards,
Processor 3 continues the previous processing. Processor 1
Receives the processing result from the shared memory 4 by the interrupt from the processor 3 and continues the processing. While the processing requested by the processor 3 is being executed, the processor 1 can perform other processing using the local memory 2.

FIG. 2 is a block diagram of a system in which two processors 1 and 3 are connected to a common system bus 100 and share a main memory 2. Each processor is
The main memory 2 is accessed independently of each other, but when one processor is accessing the main memory 2, the access request of the other processor is controlled to be waited. In this system, the message communication between the processors is performed using a specific area of the main memory 2, and the system shown in FIG. 1 is used except that the area for writing the message is the specific area in the main memory 2. A similar scheme is used.

In these two systems, if the processors 1 and 3 are provided with general cache memories 6 and 7, for example, when the processor 1 writes in the message communication area,
The value of the cache memory 6 of the processor 1 is updated at the same time as writing, but even if the value of the same address is stored in the cache memory 7 of the processor 3, the processor 3 does not update the value of the same address. Even if the area is accessed, the information in the cache memory 7 is read out, which causes a problem that the message from the processor 1 cannot be correctly received.

[Object of the Invention]

An object of the present invention is to solve the above problems, and in a data processing device adopting a multiprocessor system configured by a microprocessor or the like,
Providing a cache memory control circuit that can perform data processing consistently even if a cache memory is provided to improve performance, and a microprocessor that can access a storage device outside the cache memory at high speed Especially.

[Outline of Invention]

When using a microprocessor with a cache memory, like the message communication area in the shared memory in the multiprocessor system, for example, data changes due to a specific factor such as a device other than the microprocessor,
In addition, if the microprocessor does not store the data on the storage means, which is difficult for the microprocessor to detect the change of data, in the cache memory, the microprocessor does not access the cache memory and the external memory is not stored. Since the means is accessed, the latest data can always be obtained.

Next, in the shared memory in the multiprocessor system, when a portion including the message communication area of the shared memory fails, the faulty portion is separated and a part of the remaining shared memory is changed to be used as the message communication area. If it is possible, the processing can be restarted although the performance may be lowered due to the decrease in the memory capacity.

Based on the above consideration, the present invention is connected to a storage device,
A microprocessor including at least a cache memory for holding a part of data in the storage device, wherein the microprocessor is an address of a specific area of the storage device in which the data changes due to a factor of a device other than the microprocessor. Detecting whether storage means for holding range information and an access address to the storage device or cache memory by the microprocessor are within the address range of the specific area held in the storage means And a detecting means for accessing the storage device or the cache memory by the microprocessor within the address range of the specific area held in the storage means, the storage device at the time of the access. The data in the specified area is the cache memo Rewriting in response to the detection output of the detection means, the access mechanism holds the access address to the storage device or the cache memory by the microprocessor in the storage means. The operation of detecting whether or not it is within the address range of the specified area is performed by determining that the data corresponding to the access address to the storage device or the cache memory by the microprocessor is the cache address.
It is characterized in that it is performed in parallel with the operation of detecting whether or not it is in the memory. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG.

The microprocessor 1 includes an instruction control circuit 10 that analyzes instructions and controls execution, an arithmetic unit 11, a register 12 that can be used for general purpose for each instruction, a register 13 that holds write data, and read data (including instructions). A register 14 for holding, a register 15 for holding an address for reading / writing, a register 16 for holding a lower limit address of the cache write prohibited area, and a register for holding an upper limit address of the prohibited area.
17, a comparison circuit 19 for comparing and judging the address signal 116 with the lower limit address and the upper limit address, an associative memory 20 using the address signal 116 as search data, and a selector for switching between the output signal and the data signal 121 read from the outside. 1
8. Selector 3 for selecting the data to write in the associative memory 20
0 and other control circuits, address signal 116,
It is connected to the system bus 100 by a read data signal 121, a write data signal 122, a read signal 114, a write signal 111 and an ACK signal 113. In this case, the ACK signal indicates the end of operation. The output of the arithmetic unit 11 can be written in the registers 12, 13, 15, 16 and 17 via the signal 133, and this control is performed by the instruction control circuit 10.

An operation when reading is performed in the above configuration will be described. The address to be read is calculated by the arithmetic unit and set in the register 15. As a result, the address signal 11
The read address is output to 6. The associative memory 20
The address signal 116 is used for association, and whether or not the corresponding data is stored is output to the signal 118. That is, the signal 118 is turned on when the corresponding data is present. The value of signal 118 is stored in flip-flop 22, then instruction control circuit 10 turns signal 112 on and directs reading. When the corresponding data exists in the associative memory 20, the output signal 119 of the flip-flop 22 is on, so the read signal 114 remains off due to the operation of the inverter 28 and the AND gate 29. Further, the signal 110 is turned on by the operation of the AND gate 26 and the OR gate 23 to notify the instruction control circuit 10 of the end of reading. When the reading is completed, the instruction control circuit 10 writes the value of the signal 120 in the register 14. Since the selector 18 selects the output of the associative memory 20 when the signal 119 is on, the corresponding data read from the associative memory is written in the register 14.

On the other hand, when the corresponding data does not exist in the associative memory 20, the signal 119 is off, so when the signal 112 is turned on, the read signal 114 is turned on by the operation of the inverter 28 and the AND gate 29, and an external memory not shown. Is instructed to read. In parallel with this, the comparator 19 compares the address signal 116 with the values of the registers 16 and 17, and when the address is between the lower limit value and the upper limit value held in the register, the signal 115 is turned off. To be done.

When the external memory finishes reading, it outputs the read data to the read data signal 121 and turns on the ACK signal 113. ACK
When the signal 113 is turned on, the signal 110 is turned on via the OR gate 23, and the instruction control circuit 10 writes the read data in the register 10 and completes the operation. If the address is not within the cache write-protected area, the signal 115 is on, so that when the ACK signal 113 is turned on, the signal 117 is turned on by the action of the OR gate 24 and the AND gate 25 to instruct the associative memory 20 to write. When writing is instructed with the signal 119 turned off, the associative memory 20 writes the address signal 116 in the associative portion of the row position indicated by the output of the counter 21 and the output of the selector 30 in the data portion. Selector for reading
39 selects the read data signal 121. Counter 21
Is counted up because the output of the AND gate 27 is turned on. The data thus read is written in the associative memory 20. If the read address is within the cache write inhibit area, the signal 115 is off, so the signal 117 is not on and the associative memory is not written.

Next, the operation for writing will be described. The write address calculated by the arithmetic unit 11 is written in the register 15, and then the write data is calculated by the arithmetic unit 11 and written in the register 13. After that, the write signal 111 is turned on to instruct writing. At this time, it is assumed that the data at the corresponding address is held in the associative memory 20 as in the reading, and the result is output to the signal 119. Further, the comparator 19 also compares the addresses and outputs the result as a signal 115. When the write signal 111 is turned on, the external memory circuit writes the value of the write data signal 122 to the address indicated by the address signal 116, turns on the ACK signal 113, and when the ACK signal 113 is turned on, the signal 110 is sent via the OR gate 23. Is turned on, and the instruction control circuit ends the write operation.

When the write address is not in the write-protected area, the signal 115 is on, so when the ACK signal 113 is turned on, the signal is turned on by the action of the OR gate 24 and the AND gate 25 and the writing to the associative memory 20 is instructed. It The same address as the write address is associative memory
If it is stored in 20, the signal 119 is turned on, and in this case, only the data part corresponding to the corresponding address is rewritten. If the same address is not stored, the signal 119 is off and the associative memory 20
The associative part and the data part of the row position indicated by the counter 21 are simultaneously written. In either case, the written data is the value of the write data signal 122 selected by the selector 30.

When the write address is in the cache write prohibition area, the signal 115 is in the off state, the signal 117 is not turned on, and writing to the associative memory 20 is not performed.

In the embodiment described above, the lower limit address and the upper limit address of the message communication area between processors are registered.
If you write in 16,17, the data in this area is not stored in the cache memory, so when you perform a fetch, the message communication area on the main memory is directly accessed, and there is no inconsistency in terms of data matching. .

Also, in the case of a single processor configuration, if the lower and upper addresses of the area that is accessed less frequently are written in registers 16 and 17, the data in this area will not be held in cache memory and As a result, it is possible to improve the cache rate.

〔The invention's effect〕

According to the present invention, when a processor accesses a storage means including a specific area whose stored content changes depending on a specific factor, such as an intercommunication area in a multiprocessor system, if the access is to the specific area, By prohibiting holding that data in cache memory,
You can prevent inconsistencies in the accessed data.

Further, since the address of the specific area can be reset arbitrarily, even if a failure occurs in the specific area, the processing can be continued by resetting the alternative area as the specific area.

As a result, it is possible to take advantage of the multiprocessor system aiming at load distribution, and further, it is possible to improve the overall performance by using the cache memory while maintaining the tolerance against failures and the availability. .

In addition, in the case of a single processor configuration, there are areas that are rarely accessed repeatedly. If access to this area is prohibited, holding that data in the cache memory prevents unnecessary data from being cached. The rate of being held in the memory can be lowered, and the cache memory rate as a whole can be increased.

In addition, even if the data corresponding to the access address is not in the cache memory, it can be accessed in parallel.
Since it is detected whether or not the address is within the address range of the specific area held in the storage means, when the access address is within the address range of the specific area held in the storage means, the specific area of the storage device is detected. There is an effect that the operation of prohibiting the writing of the above data into the cache memory can be performed at high speed and the storage device can be accessed at high speed.

[Brief description of drawings]

1 and 2 are block diagrams of a multiprocessor system having a shared memory, and FIG. 3 is a diagram showing an embodiment of the present invention. 1.3 ... Microprocessor, 2.2 '... main memory, 4
... Shared memory, 5.8 ... Processor main body, 6.7 ... Cash memory, 100/101 ... System bus, 10 ... Instruction control circuit, 11 ... Calculator, 12,13,14,15,16,17 ... Register , 18 ... Selector, 19 ... Comparison circuit, 20 ... Associative memory, 21
... counter, 22 ... flip-flop, 113 ... ACK signal, 11
1 ... write signal, 114 ... read signal, 116 ... address signal, 121, 122 ... data signal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masaru Matsumura 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside Hitachi, Ltd. (56) References JP-A-58-48289 (JP, A)

Claims (3)

[Claims] 1. A microprocessor, which is connected to a storage device and includes at least a cache memory for holding a part of data in the storage device, wherein the microprocessor is a device other than the microprocessor. Storage means for holding information on an address range of a specific area of the storage device in which the memory area changes, and an access address to the storage device or the cache memory by the microprocessor, the specific area held in the storage means. Detecting means for detecting whether or not the address is within the address range, and an access address to the storage device or the cache memory by the microprocessor is within the address range of the specific area held in the storage means. At certain times, the specified area of the storage device at the time of the access And a prohibition mechanism for prohibiting the writing of the data in the area to the cache memory in response to the detection output of the detection means, the access device accessing the storage device or the cache memory by the microprocessor. The operation of detecting whether or not the address is within the address range of the specific area held in the storage means is performed when the data corresponding to the access address to the storage device or the cache memory by the microprocessor is cache·
A microprocessor characterized by being performed in parallel with the operation of detecting whether or not it is in memory. 2. The multi-processor, wherein the device for changing data in the specific area of the storage device is another microprocessor different from the microprocessor, and the specific area of the storage device is a message communication area between processors. The microprocessor according to claim 1, wherein the microprocessor supports the system. 3. The microprocessor according to claim 1, wherein the cache memory is an associative memory.