JPH0594699A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up access time to e.g. 100ns level by speeding up a read operation of an EEPROM adapting a HAND cell structure or the like while stabilizing the operation. CONSTITUTION:A sense amplifier SA like the EEPROM is constituted of a ECL type or a cascode type differential amplifier circuit consisting of a bipolar circuit or a bipolar CMOS circuit. Dummy cells QD in multiples of normal memory cell QC are serially connected to the memory array MARY, and dummy bit line DB imparting a prescribed reference potential to the sense amplifier SA is provided. Thus, the amplification factor of the sense amplifier SA is remarkably raised, the amplification operation is speeded up, the stabilized reference potential is generated by means of a dummy bit line DB, and the operation of the sense amplifier SA is stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, an EEPROM (Electrically Erasa) having a so-called NAND type cell structure.
ble and Programmable Read O
The present invention relates to a technique which is particularly effective when used for nly Memory).

[0002]

2. Description of the Related Art There is a NAND cell structure EEPROM having a basic structure of a memory array in which a predetermined number of memory cells capable of reading, erasing and programming of stored data are connected in series in a column direction. The EEPROM includes a sense amplifier for amplifying a read signal output from a designated memory cell.

An EEPROM having a NAND cell structure is described in, for example, "ISSC: International" dated February 16, 1989.
alSolid-State Circuits Co
nference) digest of technical
Papers (Digest Of Technical)
Papers), pp. 134-135 and 314.

[0004]

In the conventional EEPROM described above, the sense amplifier is a CMOS.
The bit line, which is composed of a dynamic amplifier composed of a (complementary MOS) circuit and to which the sense amplifier is connected, has a capacity of about 20 μA (micrometer) provided that the data held in the selected memory cell is logic "1". A minute read current of about (ampere) can be obtained. As is well known, C
The dynamic amplifier composed of the MOS circuit has a relatively slow operation speed, which causes the access time of the EEPROM to be extended to about 1.6 μs (microsecond).

An object of the present invention is to speed up the read operation of an EEPROM having a NAND type cell structure, and speed up the access time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the EE adopting the NAND type cell structure
A sense amplifier such as a PROM is basically constructed by an ECL type or cascode type differential amplifier circuit composed of a bipolar circuit or a bipolar CMOS circuit, and dummy cells in multiples of normal memory cells are connected in series to the memory array. A dummy bit line that provides a predetermined reference potential to the amplifier is provided.

[0008]

According to the above means, the amplification factor of the sense amplifier can be remarkably increased and the amplification operation can be speeded up, and a stable reference potential can be generated by the dummy bit line to stabilize the operation of the sense amplifier. As a result, particularly, the read operation of the EEPROM or the like having the NAND type cell structure can be stabilized and speeded up, and the access time can be speeded up to, for example, 100 ns (nanosecond).

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an EEPRO to which the present invention is applied.
A block diagram of one embodiment of M is shown. Based on the figure, first, an outline of the block configuration and operation of the EEPROM of this embodiment and its features will be described. The circuit elements forming each block in FIG. 1 are formed on one semiconductor substrate such as single crystal silicon. In addition, a MOS with an arrow added to its channel (back gate) part
FET (metal oxide semiconductor field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor) is a P-channel type and is shown separately from an N-channel MOSFET without an arrow. Be done.

Referring to FIG. 1, the EEPROM of this embodiment
Has as its basic structure a memory array MARY which occupies most of the surface of the semiconductor substrate. This memory array M
ARY is m memory cells QC arranged in the same column.
Of n bit lines B1 to Bn arranged in the vertical direction to connect in series and the gates of n memory cells QC arranged in the same row are arranged in the horizontal direction to be commonly connected.
The word lines W1 to Wm are included. Bit lines B1 to Bn
One end of each of the n memory cells QC coupled to each of the memory cells is connected to a corresponding N-channel type selection MOSFE of the Y switch circuit YS.
It is coupled to the common data line CD via TQ1 to Q3, and the other ends thereof are N-channel type control MOSFETs Q5 to Q.
Via 7 to the ground potential of the circuit. The gates of the selection MOSFETs Q1 to Q3 of the Y switch circuit YS have Y
The corresponding bit line selection signal Y from the address decoder YD
1 to Yn are respectively supplied. In addition, the memory array M
An internal control signal SG is supplied to the ARY control MOSFETs Q5 to Q7 from a timing generation circuit (not shown). Here, the internal control signal SG is at a low level such as the ground potential of the circuit when the EEPROM is in the erase mode or the read mode, and is at a high level such as +5 V when the EEPROM is in the program mode. The memory cell QC is a so-called MNOS (Me
tal Nitride Oxide Semiconductor
). The common data line CD is coupled to the non-inverting input terminal of the sense amplifier SA and the output terminal of the write amplifier WA.

In this embodiment, the memory array MAR
Y further includes a dummy bit line DB including 2m dummy cells QD connected in series. Dummy bit line D
One end of the 2m dummy cells QD forming B is connected to the N-channel selection MOSFET Q4 of the Y switch circuit YS.
Through the dummy common data line DD, and the other end is coupled to the ground potential of the circuit through the N-channel type control MOSFET Q8. The gate of the selection MOSFET Q4 of the Y switch circuit YS is supplied with the internal control signal CE from the timing generation circuit. Here, the internal control signal CE is set to a high level at a predetermined timing when the EEPROM is selected in the read mode.
The internal control signal SG is supplied to the gate of the control MOSFET Q8 of the memory array MARY, and the dummy cell Q
The two gates of D are commonly coupled to each other and then coupled to corresponding word lines W1 to Wm. The dummy cell QD
The storage data of logical "1" is written in advance. Further, the dummy common data line DD is coupled to the inverting input terminal of the sense amplifier SA.

By the way, between the power supply voltage of the circuit and the common data line CD and the dummy common data line DD, P-channel type precharge MOSFETs Q11 and Q12 which receive the internal control signal PC at their gates are provided. Here, the internal control signal PC is normally + 5V or + 17V or + 22V, such as the precharge MOSFET Q1.
1 and Q12 are set to a predetermined high level so as not to be turned on, and are set to a low level like the ground potential of the circuit when the EEPROM is initially selected in the read mode. As a result, the common data line CD and the dummy common data line DD are precharged to a high level like the power supply voltage of the circuit immediately before the read operation of the EEPROM is started.

The word lines W1 to Wm are coupled to the X address decoder XD and selectively set to a selected level or a non-selected level under a predetermined condition. The X address decoder XD has
I-bit X through the address input terminals AX1 to AXi
An address signal is supplied and a timing control circuit supplies a mode control signal (not shown). On the other hand, the bit line selection signal lines Y1 to Yn are coupled to the Y address decoder YD and selectively set to a selection level or a non-selection level under a predetermined condition. The Y address decoder YD is supplied with a j-bit Y address signal via the address input terminals AY1 to AYj, and the mode control signal is supplied from the timing generation circuit.

The X address decoder XD is based on the X address signal supplied via the address input terminals AX1 to AXi and the mode control signal supplied from the timing generation circuit, and the word lines W1 to Wm of the memory array MARY.
Is a predetermined selection level or a non-selection level in a predetermined combination. Further, the Y address decoder YD sets the bit line selection signals Y1 to Yn to a predetermined value based on the Y address signal supplied via the address input terminals AY1 to AYj and the mode control signal supplied from the timing generation circuit. A predetermined selection level or a non-selection level is combined.

That is, when the EEPROM is in the erase mode, the X address decoder XD sets all the word lines W1 to Wm to a high level such as + 17V, and the Y address decoder YD outputs all the bit line selection signals Y1.
~ Yn is set to a high level such as + 17V. At this time, the common data line CD is set to a low level like the ground potential of the circuit by the write amplifier WA, and the internal control signal S
G is a high level such as + 5V. However, Y
In the switch circuit YS, the selection MOSFETs Q1 to Q3 are turned on all at once, and in the memory array MARY, the control M
The OSFETs Q5 to Q7 are turned on all at once. As a result, all the memory cells QC forming the memory array MARY are set to a so-called enhanced mode with the threshold voltage set to about 2 V, and all stored data are erased.

Then, following the erase mode, EEPRO
When M is set to the program mode, the X address decoder XD decodes the X address signal to set the corresponding word line and the word line older than this word line to the low level like the ground potential of the circuit and designated. The word line that is younger than the word line is set to a high level such as + 22V. Also, the Y address decoder YD decodes the Y address signal and selectively outputs the corresponding bit line selection signal +.
It is set to a high level such as 22V and the other bit line selection signals are set to a low level such as the ground potential of the circuit. At this time, if the write data input from the write amplifier WA via the data input / output terminal DIO is a logic "1", a high level such as + 22V is output to the common data line CD, and a logic "0" is output. If there is, a low level such as + 11V is output. The internal control signal SG is at a low level like the ground potential of the circuit. As a result, the selection MOSFETs Q1 to Q3 are alternatively turned on in the Y switch circuit YS, and the control MOSs in the memory array MARY.
FETs Q5 to Q7 are both turned off. As a result, one designated memory cell QC of the memory array MARY is set to the depletion mode having a threshold voltage of about −3 V when the corresponding write data is logic “1”, and the corresponding write data is A logic "0" leaves the enhanced mode with a threshold voltage of approximately 2V.

On the other hand, when the EEPROM is set to the read mode, the X address decoder XD selectively sets the word line designated by the X address signal to the low level such as the ground potential of the circuit, and the other word lines + 5V. To a high level. Also, the Y address decoder Y
D selectively sets the bit line selection signal designated by the Y address signal to a high level such as + 5V, and sets the other bit line selection signals to a low level such as the ground potential of the circuit. At this time, the internal control signal SG is set to a high level such as + 5V. As a result, the selection MOSFETs Q1 to Q3 are alternatively turned on in the Y switch circuit YS, and the control MOSFETs in the memory array MARY.
Q5-Q7 are turned on all at once. As a result, when the data held in one designated memory cell QC of the memory array MARY is logical "1", in other words, the corresponding bit lines B1 to Bn are stored in the memory array MA.
Provided that the memory cell QC designated by RY is in the depletion mode having a threshold voltage of about -3 V, a minute read current of about 20 μA is selectively obtained, and the corresponding voltage signal is common. It is output to the data line CD. When the data held in the designated memory cell QC is logic "0", in other words, when the designated memory cell QC is in the enhanced mode having a threshold voltage of about 2V, the corresponding bit lines B1 to No read current is passed through Bn.

As described above, the EEPROM of this embodiment
Memory array MARY is provided with 2m dummy cells QD in which storage data of logic "1" is written in advance, and these dummy cells QD correspond to corresponding word lines W1 to W1.
By selectively setting Wm to the low level, two of them are simultaneously selected. Therefore, the memory array MARY
In accordance with the read operation of the selected memory cell QC, the corresponding two dummy cells QD are set to the selected state,
A read current according to the data held in the selected dummy cell QD is output to the dummy bit line DB. This read current becomes a corresponding voltage signal, and the Y switch circuit Y
It is supplied to the inverting input terminal of the sense amplifier SA through the S selection MOSFET Q4 and the dummy common data line DD. The value of the read current output to the dummy bit line DB is selected because the data held in all the dummy cells QD is logic "1" and two dummy cells QD are simultaneously selected. One half of the read current of the bit lines B1 to Bn, that is, about 10 when the data held in the normal memory cell QC is logic "1"
It becomes about μA. However, at the inverting input terminal of the sense amplifier SA, a stable reference potential, which is an intermediate level of the read signal when the data held in the selected memory cell QC is logic “1” and logic “0”, is obtained, This stabilizes the read operation of the EEPROM.

FIG. 2 is a circuit diagram of a first embodiment of the sense amplifier SA included in the EEPROM of FIG. The specific circuit configuration, operation, and characteristics of the sense amplifier SA of this embodiment will be described with reference to FIG. In the circuit diagrams below, all illustrated transistors (bipolar transistors are simply referred to as transistors in this specification) are NPN type transistors.

In FIG. 2, the sense amplifier SA of this embodiment includes a differential circuit including a pair of differential transistors T2 and T3. Of these, the base of the transistor T2 is coupled to the inverting input terminal of the sense amplifier SA, that is, the dummy common data line DD via the input emitter follower circuit including the transistor T1 and the constant current source S1, and the base of the transistor T3 is connected to the transistor T4. And a non-inverting input terminal of the sense amplifier SA, that is, the common data line CD, via an input emitter follower circuit including a constant current source S3. The collectors of the differential transistors T2 and T3 are coupled to the circuit power supply voltage via the corresponding load resistors R1 and R2, and their commonly coupled emitters are coupled to the circuit ground potential via the constant current source S2. .. The power supply voltage of the circuit is a positive power supply voltage such as + 5V. Thereby, the differential transistors T2 and T3
Together with the load resistors R1 and R2 and the constant current source S2, so-called ECL (Emitter Coupled) that receives a read signal as a voltage signal to each base.
A Logic) type differential amplifier circuit is configured. At this time, the collector of the transistor T2 becomes the inverting output node of this differential amplifier circuit, and the collector of the transistor T3 becomes its non-inverting output node.

Clamping diodes D1 and D2 are provided between the power supply voltage of the circuit and the collectors of the differential transistors T2 and T3, respectively. The collector of the transistor T2, that is, the inverting output node of the differential amplifier circuit is coupled to the base of the transistor T5 that constitutes the output emitter follower circuit together with the constant current source S4, and the collector of the transistor T3, that is, the non-inverting output of the differential amplifier circuit. The node is coupled to the base of a transistor T6 that forms an output emitter follower circuit with the constant current source S5. The emitter potentials of the transistors T5 and T6 are supplied to the data output buffer DOB at the subsequent stage as the inverted output signal RDB and the non-inverted output signal RD of the sense amplifier SA, and further, the internal control signal OE is set to the high level. , Is output to the outside from the data input / output terminal DIO. When the sense amplifier SA is a bipolar circuit, each of the constant current sources S1 to S5 is composed of a bipolar that receives a predetermined constant voltage at its base and its emitter resistance, and the sense amplifier SA is a bipolar CM.
When it is composed of an OS circuit, it is composed of an N-channel MOSFET that receives a predetermined constant voltage at its gate.

When the data held in the selected memory cell QC of the memory array MARY is logic "1", a read current of about 20 .mu.A is obtained on the corresponding bit lines B1 to Bn and a common data line CD is obtained. A corresponding low level voltage signal is obtained. At this time, the dummy bit line DB
A read current of about 10 μA is output to the dummy common data line DD, and a corresponding intermediate level voltage signal, that is, a reference potential is obtained on the dummy common data line DD. The potential difference between the common data line CD and the dummy common data line DD is rapidly amplified by the differential amplifier circuit including the differential transistors T2 and T3,
It is transmitted to the non-inverting and inverting output terminals of the sense amplifier SA. As a result, the non-inverted output signal RD of the sense amplifier SA
Is set to a predetermined high level which is lower than the power supply voltage of the circuit by the base-emitter voltage of the transistor T6, and its inverted output signal RDB has an operating current supplied from the constant current source S2, the resistance value of the resistor R1 and the transistor T5. It is set to a predetermined low level determined by the base-emitter voltage.

On the other hand, if the data held in the selected memory cell QC of the memory array MARY is logic "0", no read current will flow through the corresponding bit lines B1 to Bn, which corresponds to the common data line CD. A high level voltage signal is obtained. At this time, a read current of about 10 μA is also output to the dummy bit line DB, and a corresponding intermediate level reference potential is obtained on the dummy common data line DD. Common data line CD and dummy common data line DD
The potential difference between the sense amplifier SA and the sense amplifier SA is rapidly amplified by the differential amplifier circuit including the differential transistors T2 and T3.
Are transmitted to the non-inverting and inverting output terminals of the. As a result, the non-inverted output signal RD of the sense amplifier SA changes to the constant current source S2.
Is set to a predetermined low level that is determined by the operating current given by the above, the resistance value of the resistor R2 and the base-emitter voltage of the transistor T6, and its inverted output signal RDB is
It is set to a predetermined high level which is lower than the power supply voltage of the circuit by the base-emitter voltage of the transistor T5.

As described above, the EEPROM of this embodiment
Has a NAND type cell structure, and the designated memory cell QC
The value of the read current output from each of the bit lines to the corresponding bit lines B1 to Bn is as small as about 20 μA. However, in the EEPROM of this embodiment, the sense amplifier SA for amplifying the read signal is basically constructed by an ECL type differential amplifier circuit including a pair of differential transistors and having a relatively large amplification factor. Therefore, the read operation of the EEPROM is significantly faster than the conventional EEPROM using the CMOS dynamic amplifier as the sense amplifier SA, and the access time is shortened to 100 ns.

FIG. 3 is a circuit diagram of a second embodiment of the sense amplifier SA included in the EEPROM of FIG.

In FIG. 3, in the sense amplifier SA of this embodiment, each emitter is coupled to the non-inverting output terminal of the sense amplifier SA, that is, the common data line CD or the inverting output terminal of the sense amplifier SA, that is, the dummy common data line DD. A pair of differential transistors T7 and T8 are included. The collectors of the transistors T7 and T8 are coupled to the circuit power supply voltage via the corresponding load resistors R3 and R4, and their emitters are further coupled to the circuit ground potential via the corresponding constant current sources S7 and S8. .. Diodes D3 and D4 are provided at the bases of the transistors T7 and T8.
A predetermined bias voltage is applied by the bias circuit including the constant current source S6. Thus, the transistors T7 and T8 form a cascode type differential amplifier circuit together with the resistors R3 and R4 and the constant current sources S7 and S8. At this time, the collector of the transistor T7 becomes the inverting output node of this differential amplifier circuit,
The collector of 8 becomes its non-inverting output node.

Clamping diodes D5 and D6 are provided between the power supply voltage of the circuit and the collectors of the differential transistors T7 and T8, respectively. The collector of the transistor T7, that is, the inverting output node of the differential amplifier circuit is coupled to the base of the transistor T9 that forms the output emitter follower circuit together with the constant current source S9, and the collector of the transistor T8, that is, the non-inverting output of the differential amplifier circuit. The node is coupled to the base of a transistor T10 that forms an output emitter follower circuit with the constant current source S10. The emitter potentials of the transistors T9 and T10 are used as the inverted output signal RDB and the non-inverted output signal RD of the sense amplifier SA, and the data output buffer D in the subsequent stage
It is supplied to the OB and is sent to the outside from the data input / output terminal DIO on condition that the internal control signal OE is set to the high level.

When the data held in the selected memory cell QC of the memory array MARY is logic "1", the common data line CD, that is, the emitter of the transistor T7, is supplied with about 20 .mu.A through the corresponding bit lines B1 to Bn. Read current is obtained. At this time, a read current of about 10 μA is obtained through the dummy bit line DB in the dummy common data line DD, that is, the emitter of the transistor T8. The difference between these read currents is amplified by a cascode type differential amplifier circuit centered on the differential transistors T7 and T8, and becomes a voltage signal at the collectors of the transistors T7 and T8. As a result, the sense amplifier S
The non-inverted output signal RD of A is set to a predetermined high level, and its inverted output signal RDB is set to a predetermined low level.

On the other hand, if the data held in the selected memory cell QC of the memory array MARY is logic "0", no read current is passed through the common data line CD, that is, the emitter of the transistor T7. At this time, the dummy common data line DD, that is, the emitter of the transistor T8,
After all, a read current of about 10 μA can be obtained through the dummy bit line DB. The difference between these read currents is
It is amplified by the cascode type differential amplifier circuit and becomes a voltage signal at the collectors of the transistors T7 and T8.
As a result, the non-inverted output signal RD of the sense amplifier SA is set to a predetermined low level and its inverted output signal RDB is set to a predetermined high level.

As described above, the sense amplifier S of this embodiment is
Since A is based on a cascode type differential amplifier circuit including a pair of differential transistors and having a relatively large amplification factor, the read operation of the EEPROM is the same as that of the first embodiment.
As in the previous embodiment, it is significantly faster and its access time is correspondingly shortened.

As shown in the above embodiments, by applying the present invention to an EEPROM having a NAND cell structure,
The following effects can be obtained. That is, (1) by constructing a sense amplifier such as an EEPROM having a NAND cell structure based on an ECL type or cascode type differential amplifier circuit composed of a bipolar circuit or a bipolar CMOS circuit, the amplification factor of the sense amplifier is significantly increased. It is possible to obtain the effect that the read signal can be increased and the amplification operation of the read signal can be speeded up. (2) In the above item (1), a dummy bit line is provided in the memory array of the EEPROM, the dummy cells being a multiple of the number of normal memory cells connected in series to provide a sense amplifier with a dummy bit line. The effect that the stable reference potential is supplied to and the amplification operation can be stabilized is obtained. (3) According to the above items (1) and (2), particularly, the read operation of the EEPROM or the like having the NAND type cell structure is stabilized and speeded up, and its access time is, for example, 100 n.
The effect that the speed can be increased up to s is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, referring to FIG. 1, an EEPROM memory array MAR
The memory cells QC forming Y can be combined with a predetermined number of memory cells in a serial form as a unit, or may be composed of other than MNOS. The memory array MARY can be divided into a plurality of similar memory mats or sub memory arrays. EE
The PROM may have a so-called multi-bit configuration that inputs or outputs a plurality of bits of stored data at the same time, and its block configuration and word lines and bit line selection signals as well as logic levels of internal control signals and the like. Its absolute value is not limited by this embodiment. Further, various embodiments such as a specific configuration of the sense amplifier SA shown in FIGS. 2 and 3, conductivity types of transistors and MOSFETs, and polarities and absolute values of power supply voltages can be adopted.

In the above description, EE, which is the field of application of the invention mainly made by the present inventor, was the background.
Although the case of application to a PROM has been described, the present invention is not limited to this, and for example, a mask ROM (Rea
d Only Memory) and EPROM (UV E
rasable and ProgrammableRe
It is also applicable to ad only memory). The present invention can be widely applied to read-only semiconductor memory devices in which at least the memory cell is basically composed of MOSFET and the read signal level is relatively small.

[0034]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, E which adopts the NAND type cell structure
A sense amplifier such as an EPROM is basically configured by an ECL-type or cascode-type differential amplifier circuit including a bipolar circuit or a bipolar CMOS circuit, and dummy cells in multiples of normal memory cells are connected in series to the memory array. By providing a dummy bit line that gives a predetermined reference potential to the amplifier, the amplification factor of the sense amplifier can be significantly increased and its amplification operation can be speeded up, and a stable reference potential is generated by the dummy bit line to improve the sense amplifier operation. Can be stabilized. As a result, particularly, the read operation of the EEPROM or the like having the NAND type cell structure is stabilized and speeded up, and the access time can be speeded up to, for example, 100 ns.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an EEPROM to which the invention is applied.

FIG. 2 is a circuit diagram showing a first embodiment of a sense amplifier included in the EEPROM of FIG.

3 is a circuit diagram showing a second embodiment of the sense amplifier included in the EEPROM of FIG.

[Explanation of symbols]

MARY ... memory array, YS ... Y switch circuit, XD ... X address decoder, YD ... Y address decoder, WA ... write amplifier, SA ... sense amplifier, DIB ... data Input buffer, DOB
... Data output buffer. QC ... memory cell, Q
D ... Dummy cell, Q1 to Q8 ... N channel M
OSFET, Q11 to Q12 ... P-channel MOS
FET. T1 to T10 ... NPN type bipolar transistors, D1 to D6 ... Diodes, R1 to R4 ...
-Resistance, S1 to S10 ... Constant current source.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 29/792 8225-4M H01L 29/78 371 (72) Inventor Katsuyuki Sato 2326 Imai, Ome, Tokyo Address Hitachi, Ltd. Device Development Center (72) Inventor Kazuyuki Miyazawa 2326 Imai, Ome, Tokyo Metropolitan Area Hitachi, Ltd. Device Development Center

Claims (5)

[Claims] 1. A memory array in which memory cells that can be read only or read and programmed or erased and programmed are arranged in a grid, and a sense amplifier including a bipolar circuit or a bipolar CMOS circuit. And semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the sense amplifier is an ECL type sense amplifier including a pair of differential transistors and receiving a read signal as a voltage signal at the base of the differential transistor. .. 3. The semiconductor memory device according to claim 1, wherein the sense amplifier is a cascode type sense amplifier including a pair of differential transistors and receiving a read signal as a current signal in an emitter of the differential transistor. .. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an EEPROM having a NAND cell structure. 5. The semiconductor memory according to claim 4, wherein the EEPROM includes a dummy bit line in which a plurality of dummy cells of a normal memory cell are connected in series and which applies a predetermined reference potential to the sense amplifier. apparatus.