JPH0588983A - Method for dynamic address conversion of channel equipment - Google Patents

Abstract

PURPOSE:To reduce the fetching frequency of a segment table and a page table from a main storage device and to speed up address conversion processing by providing a channel equipment with a page table storing part. CONSTITUTION:A fetch judging circuit 12 in the channel equipment judges whether the page table entry of a page number included in a logical address exists in the page table storing part 7 or not. At the time of judging the absence of the page table entry, a fetch control part 6 issues a fetch request. A transfer control device 2 obtains the segment table entry specified by the fetch request and plural page table entries from the main storage device 1 and sends these entries to the equipment 3. A real address is formed in a register 14 based upon a page address included in the page table entry stored in the storing part 7 and intra-page deformation included in a logical address stored in a register 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conversion system for dynamically converting an address from a logical address to a real address in data transfer of a channel device.

In recent large- and medium-sized computer systems, a disk array device is provided in an external storage device for high-speed and large-volume data communication. Therefore, the amount of input / output data at one time is increasing, and high-speed data transfer between the channel device and the main storage device is required. At present, the bus width is being expanded and store-no-fetch requests are being parallelized, and the speed of data transfer is increasing.

On the other hand, the dynamic address translation process in the channel during data transfer is in the order of several KB in order to maintain compatibility with the conventional system and consistency with the dynamic address translation mechanism in the CPU.
It needs to be executed every time the boundary of a very small page is reached. In addition, the address conversion process needs to be performed sequentially as the input / output data is transferred. Due to the above reasons, the overhead of the address translation processing by the dynamic address translation mechanism of the channel device is relatively large, and the performance of the computer system is degraded.

[0004]

2. Description of the Related Art FIG. 4 is a diagram showing a data transfer process of a channel device. In FIG. 4, the main storage device 40 holds input / output data. The transfer control unit 41 uses the main storage device 4
Controls data transfer to 0. The channel device 42 performs a data transfer process of input / output data. The disk array device 43 stores input / output data. Prior to data transfer, the channel device 42 performs address conversion processing.
This address conversion process needs to be performed every time a small page boundary is reached, as shown in the figure.

The dynamic address conversion processing from the logical address to the real address in the conventional channel device has been performed as follows. First, when it is detected that the data address reaches the page boundary, the segment table entry stored in the main memory is fetched using the segment number and the segment table starting point. Next, the page table entry stored in the main memory is fetched using the page number and the page table starting point in the segment table entry. Since the page table entry has a page address, a real address can be obtained by adding an in-page displacement to this.

[0006]

As described above, the dynamic address translation process in the conventional channel device requires access to the main memory device twice each time the page boundary is reached. Further, since this continuous access is sequentially performed with the transfer of input / output data, there is a problem that the overhead is very large.

In view of the above conventional problems, the present invention eliminates access to the main storage device in the dynamic address translation process when a page boundary is reached in the data transfer of the channel device, thereby eliminating the problem of the channel device. The purpose is to speed up the dynamic address translation process in.

[0008]

According to the invention, the above mentioned objects are achieved by the means recited in the patent claims. That is, the present invention provides a page table storage for storing a plurality of page table entries in a channel device which has a dynamic address translation mechanism from a logical address to a real address and transfers input / output data to / from a main storage device. And a step of referring to a page table entry existing in the page table storage unit when a page address is obtained, and a plurality of page tables from the main storage device when the target page address cannot be obtained even by the step. A dynamic address translation method for a channel device, comprising: fetching an entry; and storing a plurality of fetched page table entries in the page table storage unit.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the main storage device 1 has a segment table 4 and a page table 5. Upon receiving the fetch request from the channel device 3, the transfer control device 2 receives the main storage device 1
The segment table entry and the page table entry are fetched from and the transfer is controlled. The fetch control unit 6 issues a fetch request to the transfer control unit 2 when the fetch determination circuit 12 determines that the fetch of the segment table entry and the page table entry is necessary. Page table storage unit 7
Has a capacity for storing a plurality of page table entries, and stores a plurality of page table entries sent by the transfer control device 2.

The pointer 8 points to a certain page table entry held by the page table storage unit 7, and the indicated value is incremented by an adder 9 which operates based on the logics of the NOT circuit 11 and the AND circuit 10. To go. The boundary arrival determination circuit 13 determines whether or not the data address reaches the page boundary.
The DAT control bit stored in the register 16 indicates whether the channel device 3 operates in the real address mode or the logical address mode. A real address is generated in the register 14 from the page address in the page table entry in the page table storage unit 7 pointed to by the pointer 8 and the in-page displacement at the logical address stored in the register 15.

When the page table entry of the page number at the logical address is not in the page table storage unit 7, the pointer 8 is reset and a plurality of new page table entries are fetched, and the page table storage unit 7 fetches them. Store in 7. On the other hand, when the target page table entry is in the page table storage unit 7, it is not necessary to access the main storage device 1, so that the real address can be generated at high speed.

[0012]

FIG. 2 is a diagram showing a configuration example of a boundary arrival determination circuit. In FIG. 2, the boundary arrival determination circuit 20 reads the DAT control bit indicating the logical address mode from the register 21 and the in-page displacement of the logical address from the register 22, respectively. The operation instruction circuit 23 gives an operation instruction to each part of the boundary arrival determination circuit 20 when the DAT control bit indicates the logical address mode.

Register 24 stores the page size, which is one input to adder 25. Adder 2
The other input of 5 is the complement of the intra-page displacement at the logical address. Therefore, the value up to the page boundary is set in the register 26 that stores the addition result of the adder 25. The comparator 28 compares the value up to the page boundary with the value of the counter 27 that counts the number of transfer data. When the comparison results match, the page boundary is reached.

FIG. 3 is a diagram showing an embodiment of the present invention.
In FIG. 3, the channel device 32 performs address conversion processing prior to data transfer. In the conversion processing, it is first determined whether the data address is represented by a logical address or a real address. In the case of a real address, it is not necessary to perform the conversion process, and the conversion process is ended as it is. In this case, the DAT control bit indicates off.

When the DAT control bit is turned on and the data address is a logical address, it is determined in the next step whether or not the page table entry of the page number of the logical address is in the page table storage unit 36. .. If it is determined that there is no page table entry, the segment table and page table are fetched. At this time, the fetch control unit 35 issues a fetch request to the transfer control device 31.

The transfer control device 31 obtains the segment table entry and the plurality of page table entries indicated by the fetch request from the segment table 33 and the page table 34 of the main memory device 30, and sends them to the channel device 32. In the fetch request, for example, a request for a plurality of 2 ⁿ page table entries from page numbers {m × 2 ⁿ } to {(m + 1) 2 ⁿ −1} is made.

A plurality of page table entries received from the transfer control device 31 are stored in the page table storage section 36. At this time, the pointer 37 is reset.
On the other hand, when it is determined that the page table entry of the page number at the logical address is already in the page table storage unit 36, the pointer 37 is set to point to the page table entry next to the page table entry related to the previous address conversion. Proceed.

Finally, the real address is generated from the page address in the page table entry pointed to by the pointer 37 and the in-page displacement at the logical address. When requesting fetch of 2 ⁿ page table entries as described above, the page number in the logical address is a multiple of 2 ⁿ when determining whether the required page table entry exists in the page table storage unit 36. You can check whether or not At this time, if it is not a multiple of 2 ⁿ , it is stored in the page table storage unit 36,
If it is a multiple of 2 ⁿ , it is necessary to fetch.

[0019]

As described above, according to the present invention,
In particular, in the dynamic address translation process by the channel device in a large amount of data transfer, the number of times the segment table and the page table are fetched from the main storage device can be greatly reduced, which has the advantage of greatly contributing to the improvement of the data transfer rate. is there.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a boundary arrival determination circuit.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing a data transfer process of a channel device.

[Explanation of symbols]

 1, 30, 40 Main storage device 2, 31, 41 Transfer control device 3, 32, 42 Channel device 4, 33 Segment table 5, 34 Page table 6, 35 Fetch control unit 7, 36 Page table storage unit 8, 37 Pointer 9, 25 Adder 10 AND circuit 11 NOT circuit 12 Fetch determination circuit 13, 20 Boundary arrival determination circuit 14-16, 21, 22, 24, 26 Register 23 Operation instruction circuit 27 Counter 28 Comparator 43 Disk array device

Claims (1)

[Claims] 1. A page table storage unit for storing a plurality of page table entries in a channel device having a dynamic address translation mechanism from a logical address to a real address for transferring input / output data to / from a main storage device. And a step of referring to the page table entry existing in the page table storage unit when obtaining the page address, and a plurality of page table entries from the main storage device when the target page address cannot be obtained even by the step. And a step of storing the plurality of fetched page table entries in the page table storage unit.