JPH0588020B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method in a data communication network, and more particularly to a data transfer delay time selection method for a multiprocessor system.

[Conventional technology]

Conventionally, variations in delay time selection in a data transfer delay time selection method have been realized by controlling priority and non-priority data transfer within the same processor.

[Problem that the invention seeks to solve]

Therefore, there are two priority rankings for various data transfer delay time request sources, so depending on the traffic amount of the priority data transfer request source,
Since the data transfer delay time fluctuates, there is a drawback that it is difficult to guarantee the desired data transfer delay time to the requesting source.

The aim of the invention is to eliminate the above-mentioned drawbacks.

[Means for solving problems]

According to the present invention, there is provided a multiprocessor system in which the function of data transfer delay time selection is realized by a load distribution configuration using a plurality of first processors, wherein at least one second processor for load distribution selection control is used. is provided in the multiprocessor system and the plurality of first processors perform load distribution. The processor classifies the plurality of first processors into two or more classes in advance according to the required value of data transfer delay time, determines in advance the first processor corresponding to each class, and The second processor is characterized in that when a request for data transfer delay time selection is received, the processor selects one first processor of the class corresponding to the request, thereby realizing the request for data transfer delay time selection. A data transfer delay time selection method for a multiprocessor system is obtained.

That is, in the data transfer delay time selection method of the multiprocessor system of the present invention, the second processor classifies various required data transfer delay times into two or more classes, and selects one or more for each class. 1st
The processors are associated with each other in advance, and when a request for data transfer delay time is made, one first processor is selected from the above correspondence, thereby providing the desired data transfer delay time.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 shows the network configuration of a packet switching network to which the present invention is applied. The terminal TA requesting the data transfer delay time is accommodated in the A station, and the communication partner terminal TB is accommodated in the B station. There are four transmission lines a1, a2, b, and c as inter-office transmission lines between the A station and the B station.

FIG. 1 is a diagram of the multiprocessor system configuration of station A in FIG. 2. A plurality of first processors (hereinafter referred to as load distribution processors) P1, P2, P3, and P4 that perform load distribution are connected to the optical bus 10, and these load distribution processors P1 to P4 are connected to inter-office transmission lines a1, a2, b, c, respectively, and the inter-office transmission lines a1, a2, b,
It corresponds to c. The optical bus 10 is further connected to a second processor Pa for load distribution selection control (hereinafter referred to as load distribution selection control processor).

Figure 3 shows the load information transfer method, and the load distribution processors P1, P2, P3, P4
Each of them transmits its own load information (transmission path, buffer memory, and CPU usage rate) to the load distribution selection control processor Pa via the optical bus 10 as signals 11, 12, 13, and 14 at regular intervals. Transfer via. The load distribution selection control processor Pa can grasp the load fluctuation status by receiving load information from each load distribution processor at regular intervals.

FIG. 4 is a block diagram of the load distribution selection control processor (Pa in FIG. 3). Load information is optical bus 10
The signal is captured by the receiver 23 via the signal analyzer 2.
5, the load information signal is determined and stored in the load information control section 32. Terminal (terminal in Figure 1)
The data transfer delay time request from the TA) is displayed in the call request packet in the packet switching network, but the classification based on the request value is
4. In this classification process, for example, when the delay time is set to three stages: high speed, medium speed, and low speed, if the required value of the delay time is high, load distribution processor P4 in FIG. This is done by providing a correspondence relationship in advance and obtaining class information so that load distribution processor P3 or P1 in the figure is selected. The CPU 44 sends a load distribution processor selection request to the transmission control section 38 via the signal line 35 together with the class information. The transmission control section 38 requests the load distribution processor selection request signal to the load information control section 32 via the signal line 33.

The detailed functions of the load information control section 32 are shown in FIG. The explanation will be given with reference to FIG. 5 apart from FIG. 4. When the reception control unit 72 receives the load information from the load distribution processor via the signal line 31,
The processing unit 75 is notified. The arithmetic processing unit 75 determines the load distribution processor from the class information and updates the load information of the corresponding load distribution processor. Load information 51, 5 in storage memory 50
2, 53, 54 and the four types of information 61, 62, 63, 64 of the regulation memory 60 correspond to the four load distribution processors P1, P2, P3, P4 shown in FIG. The arithmetic processing unit 75 updates the storage memory 50 based on this correspondence. The storage memory 50 stores LINE, buffer memory usage rate BUF, and processor usage rate indicating the transmission path usage rate as load information types for each load distribution processor.
Remember CPU. The regulation memory 60 stores regulation values in a fixed manner, and corresponds to the load information type of the storage memory 50, and for each type, the data transfer delay time from the request source (terminal TA) is determined under conditions below the regulation value. Determine whether the request is possible. These determinations are made by the arithmetic processing unit 75.

Here, the explanation will be returned to FIG. 4. The load information control unit 32 determines whether the data transfer delay time request can be accepted, and notifies the transmission control unit 38 of the result via the signal line 33. The transmission control unit 38 notifies the CPU 44 of the above-mentioned acceptance/rejection result via the signal line 34. If the result is negative, the load distribution selection control processor displays a disconnection packet and notifies the terminal (FIG. 1). If the result is OK, the CPU 44 can transmit the above-mentioned call request packet to station B (FIG. 2). The call request packet information is sent to CPU4.
4 to transmission control unit 38, transmission buffer control unit 4
0, the driver 42, and the optical bus 10 to the target load distribution processor, and further transmitted to the B station (FIG. 2) via the interoffice transmission line.

In Figure 2, station B sends a call request packet to A.
When received from the station, the incoming call packet is sent to the terminal TB, and the terminal TB transmits the incoming call acceptance packet to the terminal.
The terminal TA receives the connection completion packet and completes the call setup. After this, the terminal
Communication is performed between the TA and the terminal TB using a communication path provided by the packet network that guarantees the required value of data transfer delay time. Note that in station B in FIG. 2, a load distribution processor connected to the load distribution processor of station A is performing data transfer processing, so it can be easily inferred that the load amounts are the same.

In FIG. 4, 27 is a reception buffer control section, 29 is a reception control section, and 37 is a control bus.

〔Effect of the invention〕

As explained above, in the present invention, the second processor (load distribution selection control processor) divides various requested values of data transfer delay time into two or more classes, and for each class, the first processor (load distribution selection control processor) By defining the correspondence with the first processor (distributed processor), it is possible to flexibly respond to a wide range of requests for data transfer delay time, and by setting load restrictions for the first processor (load distribution processor), it is possible to respond flexibly to a wide range of requests for data transfer delay time. This also has the effect of guaranteeing data transfer delay time.

[Brief explanation of the drawing]

FIG. 1 is a load distribution configuration diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a diagram showing the network configuration of a packet switching network to which the present invention is applied, and FIG. Load information transfer diagram of load balancing processors in a multiprocessor system,
Figure 4 shows the load distribution selection control processor in Figure 1.
FIG. 5 is a block diagram of the load information control section 32 of FIG. 4. P1 to P4...Load distribution processor (first processor), Pa...Load distribution selection control processor (second processor), 10...Optical bus, TA,
TB...terminal, a1, a2, b, c...transmission line.

Claims (1)

[Claims] 1 The data transfer delay time selection function is
A multiprocessor system realized by a load distribution configuration using a plurality of processors, wherein at least one second processor for load distribution selection control is provided in the multiprocessor system, and the plurality of second processors for load distribution are provided in the multiprocessor system. The first processor notifies the second processor of load information regarding its own data transfer delay time at regular intervals, and the second processor transmits load information regarding the data transfer delay time to the plurality of processors in advance based on the requested data transfer delay time. The first processor is divided into two or more classes, the first processor corresponding to each class is determined in advance, and the second processor, when requested to select a data transfer delay time, A data transfer delay time selection method for a multiprocessor system, characterized in that a request for data transfer delay time selection is realized by selecting one first processor of a class that corresponds to the request.