JPH0582802A - Capacitor of semiconductor integrated circuit and nonvolatile memory using same - Google Patents

Abstract

PURPOSE:To provide a capacitor for a semiconductor integrated circuit, which can accumulate an enough quantity of signal charge and can shorten the switching time, and a nonvolatile memory using this capacitor. CONSTITUTION:A ferroelectric capacitor of such structure that a plurality of capacitors of small area are connected seemingly in series is constituted by stacking a lower electrode 31, which has comb-shaped stripe structure, a ferroelectric film 33, and an upper electrode 32, which has comb-shaped stripe structure crossing the stripe structure of the lower electrode 31, on the source region 13a of a field effect transistor 10 in that order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a capacitor used in a semiconductor integrated circuit, and more particularly to a capacitor using a ferroelectric substance and a non-volatile memory using the capacitor.

[0002]

2. Description of the Related Art Conventionally, as this type of non-volatile memory,
For example, a memory cell as described in JP-A-3-304796 is known. FIG. 5 shows an electrically equivalent circuit diagram of this memory cell, and FIG. 6 shows its element structure. The memory cell shown in FIG. 5 includes a field effect transistor 10 as a switching element and a capacitor 20 for storing a signal charge using a ferroelectric substance. The field effect transistor 10 includes a gate electrode 11, a drain electrode 12,
The gate electrode 11 is connected to the word line WL, and the drain electrode 12 is connected to the bit line BL. The capacitor 20 is provided with two electrodes 21 and 22 arranged to face each other, and a ferroelectric thin film 23 is interposed between both electrodes 21 and 22. One electrode 21 is
Connected to the source electrode 13 of the field effect transistor 10,
The other electrode 22 is connected to the ground line V _SS or the drive line DL. Here, as the ferroelectric thin film 23, lead zirconate titanate or the like generally called PZT is used.

The element structure of the above-described memory cell will be briefly described with reference to FIG. A field oxide film 2 obtained by selectively oxidizing the surface of the silicon substrate 1 forms an element formation region separately, and an oxide film 3 is formed in this region.
A field effect transistor 10 including a gate electrode 11, a drain region 12a, and a source region 13a covered with is formed. On the source region 13a, the lower electrode 21,
A capacitor 20 is formed by stacking the ferroelectric thin film 23 and the upper electrode 22 in that order. Then, the metal wiring 4 forming the bit line BL is formed on the drain region 12a, and the metal wiring 5 forming the ground line V _SS or the drive line DL is formed on the upper electrode 22.

Next, the charge storage action of the ferroelectric capacitor used in the conventional nonvolatile memory described above will be described with reference to FIGS. 7 and 8. FIG. 7 is a schematic view showing an extracted conventional capacitor formed on a semiconductor substrate. Symbols a and b in the figure are terminals of the capacitor. FIG. 8 shows a change in the amount of charge accumulated in the ferroelectric thin film 23 between the electrodes 21 and 22 when a voltage is applied between the terminals a and b. In the figure, the horizontal axis represents the electric field strength E,
The vertical axis represents the polarization amount P. The polarization amount of the ferroelectric thin film 23 is 0 → A → B → C → D with respect to the voltage change between the terminals a and b.
→ E → F → G → B, that is, a hysteresis characteristic.

Now, the electric field strength between the electrodes 21 and 22 is E ₀
After raising to a sufficiently large E _sat beyond E, and returning it to 0, a polarization amount P _S (this is called spontaneous polarization) remains in the ferroelectric thin film 23. Similarly, the electrodes 21, 22
When the electric field strength between them is reduced to -E _sat and then returned to 0, the polarization amount -P _S remains in the ferroelectric thin film 23.
Such positive and negative spontaneous polarization P s is _calculated as the data “1”,
By associating with the written state of "0", the read signal charge Q represented by the following equation is finally obtained from the capacitor 20. Q = 2P _S · S [Coulomb] In the above equation, S is the capacitor area. Note that spontaneous polarization P
_S is determined by the composition and thickness of the ferroelectric thin film 23.

[0006]

However, the conventional example having such a structure has the following problems. That is, as shown in FIG. 9, generally, the switching time of a capacitor using a ferroelectric substance such as PZT becomes shorter as the electrode area becomes smaller, and this point becomes smaller with the integration. However, as shown in FIG. 10, the inversion charge density (corresponding to 2Ps in the above equation) decreases rapidly as the electrode area decreases, which makes it difficult to read the signal charge Q. There is.

The present invention has been made in view of such circumstances, and a capacitor of a semiconductor integrated circuit capable of accumulating a sufficient amount of signal charges and shortening a switching time, and a capacitor thereof. An object of the present invention is to provide a non-volatile memory using.

[0008]

The present invention has the following constitution in order to achieve such an object. That is, a capacitor of a semiconductor integrated circuit according to a first aspect of the present invention is a capacitor of a semiconductor integrated circuit formed by laminating a lower electrode, a ferroelectric thin film, and an upper electrode in that order on a semiconductor substrate. Each electrode is formed in a comb-teeth-shaped stripe structure, and the upper and lower electrodes are arranged so as to intersect each other. A nonvolatile memory according to a second aspect of the present invention uses the capacitor according to the first aspect as a capacitor for storing signal charges.

[0009]

In the capacitor according to the present invention, the upper and lower electrodes are formed in a comb-teeth stripe structure, and the stripe structures of the electrodes are arranged so as to intersect with each other. It has a structure in which a plurality of capacitors are connected in parallel. Since the switching time of the capacitor is determined by the area of one small area capacitor, the switching time is shortened. Moreover, since a plurality of capacitors are connected in parallel, a sufficient amount of signal charges can be stored.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an electrical equivalent circuit diagram of a non-volatile memory using a capacitor according to the present invention, and FIG. 2 is a sectional view showing its element structure. In FIGS. 1 and 2, the portions designated by the same reference numerals as those in FIGS. 5 and 6 are the same components as those in the conventional example. As shown in FIGS. 1 and 2, the lower electrode 31 of the capacitor 30 according to this embodiment is connected to the source electrode 13 of the field effect transistor 10, and the upper electrode 32 is connected to the ground line V _SS or the drive line DL, respectively. There is. In this embodiment, an N-type MOS transistor will be described as an example of the switching element.
As another switching element, for example, a P-type MOS transistor, a JFET made of GaAs semiconductor, or a bipolar transistor can be used.

3A and 3B are views showing the capacitor portion extracted, in which FIG. 3A is a plan view and FIG. 3B is a line A- in FIG.
A sectional view taken along arrow A, and (c) is a sectional view taken along arrow BB in (a). As shown in FIG. 3, the capacitor 30 includes the upper and lower electrodes 3.
1 and 32 each have a comb-teeth-shaped stripe structure, and the electrodes 31 and 32 are arranged so that the stripe structures intersect. A ferroelectric thin film 33 is interposed between these electrodes 31 and 32. That is, the capacitor 30
1 has a structure in which a plurality of small area ferroelectric capacitors are connected in parallel as shown in FIG.

The element structure of the non-volatile memory shown in FIG. 1 will be specifically described below with reference to FIG. First, an element formation region is formed separately on the P-type silicon substrate 1 by the field oxide film 2, and subsequently, the gate electrode 11, the N ⁺ drain region 12a, and the N ⁺ source region 13a are formed.
Such a field effect transistor 10 can be manufactured by the well-known self-alignment. Further, the field effect transistor 10 may have an LDD (Lightly-Doped Drain) structure in order to solve the problem of hot electrons due to the miniaturization of elements. Although the gate electrode 11 is formed of polysilicon doped with phosphorus (P), it may be formed of silicide or a metal which is a compound of polysilicon and refractory metal such as tungsten (W) or molybdenum (Mo). it can.

The silicon substrate 1 on which the field effect transistor 10 is formed is covered with an insulating film such as a silicon thermal oxide film 3. Next, in order to form the lower electrode 31 of the capacitor 30 on the source region 13a, the oxide film 3 on the electrode portion is removed by anisotropic etching such as plasma etching. A metal thin film of platinum or the like is deposited thereon by sputtering or the like, and is patterned into a comb shape by a photo-etching method to form the lower electrode 31.

After forming the lower electrode 31, a ferroelectric substance is spin-coated by a sol-gel method or a MOD (Metal Orga) method.
nic Decomposition) method, or sputtering method, M
OCVD (Metal Organic Chemical Vapor Deposition)
Method, laser ablation method, and photo-etching method to form a ferroelectric thin film 33. The preferred ferroelectric substance used here is
Lead zirconate titanate, commonly called PZT, and P
LZT is called (Pb _X La _1-X ) (Zr _y T
i _1-y ) O ₃ is exemplified. Similar to the lower electrode 31, the comb-shaped upper electrode 32 is formed on the ferroelectric thin film 33 so as to intersect with the stripe structure of the lower electrode 31.

After forming the ferroelectric capacitor as described above, necessary contact regions are formed, and a metal thin film for forming the metal wiring 4 and the metal wiring 5 is deposited by sputtering or the like. As this type of conductive material,
Al-based alloy (for example, Al-Si, Al-Si-Cu
Etc.) is used, but it is also possible to use a conductive nonmetal such as phosphorus-doped polysilicon.
After depositing the above metal thin film, the metal wiring 4 to be the bit line BL and the metal wiring 5 connected to the ground line V _SS or the drive line DL are patterned by photoetching. As described above, the nonvolatile memory having the element structure shown in FIG. 2 is formed.

FIG. 4 is a sectional view showing an element structure of a nonvolatile memory according to another embodiment of the present invention. The parts designated by the same reference numerals as those in FIG. 2 are the same parts as those in the above-described embodiment, and therefore detailed description thereof will be omitted here. The feature of this embodiment is that the lower electrode 31 has a comb-teeth-shaped stripe structure.
The capacitor 30 in which the ferroelectric thin film 33 and the comb-shaped upper electrode 32 arranged so as to intersect the stripe structure of the lower electrode 31 are stacked is arranged above the gate electrode 11. In this embodiment, the upper electrode 32 is connected to the source region 13a by the metal wiring 5, and the lower electrode 31 is connected to the ground line V _SS or the drive line DL. Reference numeral 6 in the drawing is an insulating film interposed between the capacitor 30 and the metal wiring 5.

In the above embodiments, the case where the ferroelectric capacitor according to the present invention is used as the capacitor for storing the signal charge of the non-volatile memory has been described as an example.
Of course, the present invention is not limited to this, and can be applied as a general capacitor used in an integrated circuit.

[0018]

As is apparent from the above description, according to the capacitor of the semiconductor integrated circuit of the present invention, the upper and lower electrodes of the capacitor using the ferroelectric substance are formed in a comb-shaped stripe structure, The striped structures of the electrodes are arranged so as to intersect with each other, and apparently, a plurality of small area ferroelectric capacitors are connected in parallel, so that the switching time of the capacitors can be shortened. In addition to being able to do so, it is possible to store a sufficient amount of signal charges. Further, when the capacitor according to the present invention is used as a capacitor for storing signal charges of a non-volatile memory, it is possible to realize a high-performance memory cell having a short switching time and a large reading margin of signal charges.

[Brief description of drawings]

FIG. 1 is an electrical equivalent circuit diagram of a nonvolatile memory using a capacitor according to the present invention.

FIG. 2 is a cross-sectional view showing an element structure of the nonvolatile memory shown in FIG.

FIG. 3 is a diagram showing a structure of a ferroelectric capacitor according to an example.

FIG. 4 is a cross-sectional view showing an element structure of a nonvolatile memory according to another example.

FIG. 5 is an electrical equivalent circuit diagram of a conventional nonvolatile memory.

6 is a cross-sectional view showing an element structure of the nonvolatile memory shown in FIG.

FIG. 7 is a schematic view of a conventional ferroelectric capacitor.

8 is a characteristic diagram showing the relationship between the electric field between the electrodes of the capacitor shown in FIG. 7 and the polarization amount of the ferroelectric substance.

FIG. 9 is a characteristic diagram showing a relationship between an electrode area of a ferroelectric capacitor and a switching time.

FIG. 10 is a characteristic diagram showing the relationship between the electrode area of a ferroelectric capacitor and the inversion charge density.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Field oxide film 3 ... Oxide film 4 ... Metal wiring (bit line) 5 ... Metal wiring 6 ... Insulating film 10 ... Field effect transistor 11 ... Gate electrode 12 ... Drain electrode 12a ... Drain region 13 ... Source electrode 13a ... Source region 30 ... Ferroelectric capacitor 31 ... Lower electrode 32 ... Upper electrode 33 ... Ferroelectric thin film

[Procedure amendment]

[Submission date] April 13, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art Conventionally, as this type of non-volatile memory,
For example, the memory cell is known as described in JP-A-2 -304796. FIG. 5 shows an electrically equivalent circuit diagram of this memory cell, and FIG. 6 shows its element structure. The memory cell shown in FIG. 5 includes a field effect transistor 10 as a switching element and a capacitor 20 for storing a signal charge using a ferroelectric substance. The field effect transistor 10 includes a gate electrode 11, a drain electrode 12,
The gate electrode 11 is connected to the word line WL, and the drain electrode 12 is connected to the bit line BL. The capacitor 20 is provided with two electrodes 21 and 22 arranged to face each other, and a ferroelectric thin film 23 is interposed between both electrodes 21 and 22. One electrode 21 is
Connected to the source electrode 13 of the field effect transistor 10,
The other electrode 22 is connected to the ground line V _ss or the drive line DL. Here, as the ferroelectric thin film 23, lead zirconate titanate or the like generally called PZT is used.

Claims (2)

[Claims] 1. A capacitor of a semiconductor integrated circuit, which is formed by laminating a lower electrode, a ferroelectric thin film, and an upper electrode in this order on a semiconductor substrate, wherein each electrode is formed in a comb-shaped stripe structure. A capacitor of a semiconductor integrated circuit, wherein the stripe structures of the upper and lower electrodes are arranged to intersect with each other. 2. A non-volatile memory, wherein the capacitor according to claim 1 is used as a capacitor for signal charge storage.