JPH0581224A - Parallel processor - Google Patents

Abstract

PURPOSE:To efficiently drive plural jobs by reducing the network frozen due to a parity error during the transfer of a message through the network as less as possible. CONSTITUTION:This parallel processor is provided with a judging means 201 for judging information relating to routing in a message which is necessary for determining the route of the message in the network 101, and when a parity error is generated by the information relating to the routing in the message, the message is frozen as a machine check by the means 201. When a parity error is generated by information other than the information concerned in the message, no machine check is executed by the means 201 and the message is transferred to a receiving destination PE 102. The PE 102 executes the parity checks of all messages, and when a parity error is generated, executes machine check interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor, and more particularly to a parallel processor network suitable for error control when a data error occurs during message transfer in a network.

[0002]

2. Description of the Related Art Conventionally, error control of a data structure including error detection by parity is discussed in Kayashima, "System Design of Computers", pages 216 to 218. Here, all data is transferred with parity for each byte. The logic of parity check is
It should be set in consideration of making it possible to identify the location of the error as finely as possible and detecting the error as much as possible before rewriting the necessary data so that it can be re-executed when the error is detected. The result of the parity check is held in the flip-flop, and the error state is saved as accurately as possible. At this time, the timing pulse of the entire system is stopped to prevent the influence on the normal logic. This operation is called freezing. By stopping this timing pulse, the execution of the processor is frozen, the frozen state is taken out as a record, and it is provided for identifying the error occurrence location.

[0003]

When the above-mentioned conventional technique is applied to a network of parallel processors, the entire network is frozen due to the occurrence of a parity error, and message transfer in the network cannot be performed at all. This is because if a parallel processor connects multiple processing elements (hereinafter PE) to a network that can transfer data between arbitrary PEs and multiple jobs can be executed between the PEs, the network error will occur. Is not directly related to, that is, does not use the route of the error, it affects the execution of another job.

If, instead of freezing the entire network, only the place where a parity error occurs is frozen, the network is composed of multistage crossbar switches and the route of the error place is concentrated in other message transfer. If it has been used, the output of the switch at the preceding stage is blocked due to freezing, and the input of the switch at the preceding stage cannot be accepted. Furthermore, the output of the switch connected to the input of the switch at the preceding stage is blocked, and eventually, even a message not related to the route cannot be transferred.

In the prior art, no consideration has been given to the above points, and there is a problem in that when a parity error occurs during message transfer in the network and the network freezes, even messages unrelated to the route cannot be transferred. ..

It is an object of the present invention to provide a parallel processor which minimizes freezing due to a parity error during message transfer in a network and operates a plurality of jobs efficiently.

[0007]

The above object is to provide information necessary for determining the route of a message in the network, instead of performing error detection on all data of the message in the message transfer of the network and freezing as a result. This is achieved by freezing only if an error occurs in. This is because PEs that are completely irrelevant cannot be correctly routed if this information is incorrect.
This is because it is transferred to the computer and causes a malfunction. On the other hand, if there is an error other than that information, the route of the message can be correctly determined, so there is no need to freeze it.
May be forwarded to.

Therefore, the error detecting means for detecting an error in the message transferred in the network, the holding means 1 for holding the error detection result for all data of the message, and the result of the error detecting means are held, If it is an error, the instruction means 2 indicating that the message is frozen and the determination means that determines that the information relating to the routing of the message has been transferred and that instructs the holding means 2 to set the result of the error detecting means. To provide. Further, each PE is provided with the same error detecting means and holding means 1 as the network.

[0009]

When the message is transferred in the network, the determining means determines that the information related to the routing of the message has been transferred. When the information related to the routing is transferred, the error detecting means detects an error in the information and instructs the holding means 2 to hold the result. When the output of the holding means 2 indicates an error, the information related to it is frozen. If it is not wrong, no action is taken. When information other than routing-related information is transferred, the result of the error detecting means at that time is not held in the holding means 2. In addition, regardless of whether or not the network is frozen, error detection is performed on all data of the message, and the holding unit 1 that holds the result can specify the fault location as in the conventional case.

On the other hand, when a message is transferred to each PE, the error detecting means detects an error in all the data of the message and holds the result in the holding means 1. The output of this holding means indicates that an error has occurred.

Thus, in detecting an error during the transfer of a message in the network, not all the data of the message is frozen due to the error, but only the information necessary for determining the route of the message in the network is frozen. it can.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. The parallel processor here has a configuration in which a plurality of processing elements (hereinafter referred to as PEs) are connected to a network capable of data transfer between arbitrary PEs, and a plurality of jobs can be executed between the PEs. This parallel processor has, for example, a configuration as shown in FIG.
2. A network 101 that enables arbitrary data transfer between PEs, a host 103 that controls job allocation, activation, termination, etc., and network 101, PE1
02, a service processor (hereinafter referred to as SVP) 104 that supports the configuration control and maintenance / diagnosis functions of the host 103.

This parallel processor can simultaneously process a plurality of jobs requested by the user in parallel. Therefore, the host accepts a plurality of jobs requested by the user, and PEs to which no jobs are assigned or PEs with a light load
For example, jobs are assigned to them via the network 101, and execution of parallel processing is started. As a result, each PE 102 starts execution of parallel processing. Each PE
102 has a memory and can operate independently of other PEs. When data transfer is required between the PEs 102, the data transfer is performed via the network 101. When each PE 102 finishes executing the parallel processing, it notifies the host 103 via the network 101. The host 103 notifies the user that the job has ended when all the plurality of PEs 102 related to the job report. Further, the network may have any configuration such as a multistage crossbar switch. Furthermore, the host is PE
The same configuration may be used. On the other hand, the SVP is connected to the network 101, the PE 102, and the host 103 using a dedicated path, and reads out the status when a failure occurs,
Perform analysis of re-execution.

Next, message transfer will be described.
FIG. 4 shows information transferred between PEs. This information includes a reception PE number 401 indicating a PE that receives the information, a transfer control 402 indicating a network transfer method, a transmission PE number 403 indicating a PE that sent the message, and a reception PE.
When the transfer data 406 arrives at the transfer data 406
Of the transfer data storage address 404 for writing into the memory in the PE 102, the transfer data length 405 indicating the length of the transfer data 406, and the transfer data 406. Here, it is the reception PE number 401 and the transfer control 402 that are necessary to determine the route of this information in the network.

If the transfer length becomes long, the length of this information may exceed the physical limit in mounting and may not be realized. For this reason, in this embodiment, this information is divided into units of a certain length, for example, one or a plurality of bytes, and transferred as a plurality of partial messages. FIG. 5 shows such a partial message sequence. Each partial message includes a message start signal 122,
It is divided into four, a message end signal 123, a data signal 124, and a data error signal 125.

The message start signal 122 becomes 1 when the top partial message is transferred. Message end signal 12
3 becomes 1 only when the last partial message is transferred when the message is divided and transferred. Data error signal 118
Indicates whether or not there is an error in the data signal 124 in the partial message being transferred, and becomes 1 when an error occurs.
Here, it is assumed that transfer of the message is started from the left side of FIG. 4, that is, from the reception PE number 401.

The network 101 determines the route of the partial message sequence sent from a certain PE 102 using the reception PE number 401 or transfer control 402 in the first partial message, and arrives at the target reception PE. Here, the transfer control 402 is constituted by information indicating whether or not the partial message sequence is transferred to all PEs (so-called transfer), information for determining the priority order in the case of message collision, and the like. .. Receiving PE that received the partial message string
Then, the transfer data 406 in the partial message string is written to the memory in the PE according to the transfer data storage address 404.

In the following, for simplification, a partial message group or each partial message may be referred to as a message.

The network in this embodiment may have any configuration such as a crossbar switch and a multistage switch.

FIG. 1 shows the configuration of a network 101 using crossbar switches. The network 101 temporarily holds a message sent from the PE 102 or the like connected to the network 101, and extracts the message in response to a request from the message transmission control 130. The message reception control 110 and the reception PE number 401 of the message. And the transfer control 402 determine whether to output to its own port, determine the priority of the request from each message reception control 110, and provide a message transmission control 130 for transmitting a message to each port corresponding to each port. A port number register 140 that holds a port number indicating which port the message transmission control 130 is connected to, and an S that interfaces with the SVP 104
The VP adapter 150, the basic clock generation circuit 160 that generates the basic clock of the entire network 101, and the basic clock generation circuit 160 that is provided for each port.
The clock distribution circuit 161 receives the clock from the input port and distributes the clock to the circuit in the corresponding port.

The message reception control 110 reads a message held in the buffer 111, a buffer 111 for temporarily holding the message, and sends a set condition signal for setting the message to the register 113, and a set condition signal 114. A delay latch 115 for delaying and storing the data, a parity check 116 for checking the parity of the message held in the register 113, a freeze instruction latch 117 for holding the result of the parity check 116 according to an instruction from the parity check set condition circuit 201, a parity check The parity check set condition circuit 201 creates conditions for the failure point latch 119 and the freeze instruction latch 117 that hold the result of 116 according to the instruction of the delay latch 115.

In such a network, a message transfer procedure will be described first. In the message reception control 110, the buffer read control 112 confirms that the EMPTY signal 120 output from the buffer 111 is 0, sends out the read strobe 121, and reads the message held in the buffer 111. The EMPTY signal 120 is 1 when no data is stored in the buffer 111, and is 0 otherwise. The message read from the buffer 111 is held in the register 113 by the set condition signal 114. The register 113 has a message start signal 122, a message end signal 123, a data signal 124 and a data error signal 1.
It is stored separately in 25.

In the message sending control 130, whether the message is sent to the port from the received PE number 401 in the message read from each message receiving control 110 by the priority control 131 and the port number in the port number register 140. Decide whether or not. In the transmission of this message, when the messages are simultaneously transmitted from the message reception controls 110, the priority control 131 determines the transmission order among the message reception controls 110, the corresponding message is selected by the selector 135, and the PE of the transmission destination is selected. Write the message to the internal buffer (not shown). Here, the priority control 131 is the FULL signal 13 output from this buffer (not shown).
Make sure that 2 is 0, then write strobe 133
To write a message to the destination buffer.
The FULL signal 132 is 1 when the destination buffer is full and cannot receive one data, and is 0 otherwise. Further, in the priority control 131, when the transfer of the message is not completed by sending the message once, each time the message is sent, the corresponding buffer read control 112 is instructed by the signal 134 to read the next data from the buffer 111, and the message is transferred. Do.

Next, error control in the network will be described. Buffer 1 by buffer read control 112
The message read from 11 is held in the register 113. The parity of the content of the data signal 124 of the register 113 is checked by the parity check 116. The result of the parity check 116 is input to the freeze instruction latch 117. The freeze instruction latch 117 allows the parity check set condition circuit 20 so that the parity check can be performed only on the message information necessary for determining the message route in the network.
The check latch set condition signal 235 which is the output of 1 becomes the set condition.

This parity check set condition circuit 20
1 is shown in FIG. Parity check set condition circuit 20
1 receives the message start signal 122 held in the register 113 (FIG. 1) and the bit condition delay signal 126 from the delay latch 115 (FIG. 1) that delays and stores the set condition signal 114 (FIG. 1). , A counter circuit 202 and a condition generation circuit 203. In the counter circuit 202, 1 is selected by the selector 221 by the message start signal 122, and the register 222 is initialized to 1 by using the set condition delay signal 126 as a set condition. After that, when partial messages are sequentially sent, that is, when any partial message is set in the register 113, the message counter 222 is incremented by one. In the condition generation circuit 203, the contents of the routing counter 231 and the message counter 222 are compared by the comparator 232. Here, the routing counter 231 represents the information of the message necessary for determining the route of the message in the network by the number of times set in the data signal 124, and indicates how many messages continue from the start. This routing counter 231
Has been set up in advance by the SVP 104 or the like. When the output of the comparator 232 is 1, it indicates that the message information is necessary for determining the route of the message in the network, and the set condition delay signal 126
AND with a delay latch 233 that delays
Is taken. At this time, the check latch set condition signal 23
5 becomes 1 and the output of the parity check 116 is held in the freeze instruction latch 117. The output of the comparator 232 is 0
If it is, the check latch set condition signal 235 becomes 0, and the freeze instruction latch 117 does not hold it.

The freeze indication latch 117 is set to 1 when a parity error occurs in the message information needed to route the message. Freezing instruction latch 1
The output of 17 is connected to the SVP adapter 150,
The adapter 150 reports a failure occurrence to the SVP 104. When the freeze instruction latch 117 is set to 1, the clock distribution circuit 16 of the corresponding port
A 1 stops the clock in the corresponding port and freezes only that port. The other ports can operate normally.

The result of the parity check 116 also serves as an input condition for the fault location latch 119. The set condition of the failure point latch 119 is the output 125 of the delay latch 115 so that the parity check of all the data signals 124 of the message can be performed. Failure point latch 1
The input of 19 performs the parity check of all the data signals 124 of the message, and ANDs the results of the data error signal 125 and the parity check 116 by the AND circuit 128. Here, the AND circuit 128 indicates that the data error signal 128 is 0, that is, indicates that the data signal 124 has no error when the data is transferred from the transmitting side, and the parity check 116 performs the data signal 124.
It becomes 1 when an error occurs. This is to prevent the error from being detected again on the receiving side when the error is already detected on the transmitting side when the data is transmitted on the transmitting side, and to identify the location where the data error is detected. Is. Also, for this purpose, a parity check 116
The result 127 is also output to the message sending control 130, and the data error signal 125 is transferred to the next receiving side. In the configuration of FIG. 1, since the transmitting side is the PE, if the data is not checked at the time of transmission, the data error signal 125
May always be sent as 0.

When the message information necessary for determining the message route is sent in a divided manner as shown in FIG. 5, the route is controlled by the transmission inhibiting circuit 136 in the message transmission control 130. Until all the information is sent, the sending suppression circuit 136 holds it, and the priority control 131 controls it so as not to send it to the receiving side. Whether all the route information has been sent indicates that the route information is being sent while the check latch set condition signal 235, which is the output of the parity check set condition circuit 201, is 1. It may be determined by.

FIG. 8 shows a 2-input-2 output crossbar switch 101 as another example of a network to which the present invention is applied.
8 shows an 8-input-8-output Benes network using the. The host and SVP are not shown here. 2-input-2 output crossbar switch 1 in 8-input-8-output Benes network
The crossbar switch 101 is the same as the network of FIG. 1 except that the number of inputs and outputs is different from that of the network of FIG. In this way, the parity check (PC in the figure) is provided at the input of each crossbar switch 101.

Next, FIG. 3 shows the structure of a PE used with the network of FIG. 1 or 8. The PE 102 is a transmission device 301 that transmits a message to the network 101.
A data processing device 302 for executing instructions and the like, and a receiving device 30 for receiving messages from the network 101.
3. Memory device 304 for storing instructions and data, SVP
A basic clock generation circuit 160 that generates a basic clock for the adapter 305 and the PE 102, and a clock distribution circuit that is provided for each device and that receives a clock from the basic clock generation circuit 160 and distributes the clock to the circuits in the corresponding device. 161. Transmitting device 301
Is a memory device 3 according to an instruction from the data processing device 302.
DM the data necessary to compose the message from 04
It is read by the A (direct memory access) controller 311. The read data is transmission control 31
Network 101 assembled into messages by 0
Sent to.

The receiving device 303 delays the buffer 331 that temporarily holds the message, the buffer read control 332 that reads the message held in the buffer 331 and sets it in the register 333, and the set condition signal 334 that sets it in the register 333. Parity check 33 for checking the parity of the message held in the delay latch 335 and the register 333 to be stored
6 and a machine check latch 337 that holds the result of the parity check 336.

In the receiving device 303, the buffer read control 332 confirms that the EMPTY signal 340 output from the buffer 331 is 0, and the read strobe 3
41 is sent out, and the message held in the buffer 331 is read out. The message read from the buffer 331 is held in the register 333 by the set condition signal 334. The register 333 has a message start signal 34
2, the message end signal 343, the data signal 344, and the data error signal 350 are stored separately. When the message is held in the register 333, the DMA controller 338 follows the contents of the message and stores the memory device 304.
Write the transfer data to. In addition, the DMA controller 33
When the reading of all the messages is not completed by reading the register 333 once, the reference numeral 8 instructs the corresponding buffer read control 332 by the signal 345 to read the next data from the buffer 331 every time the reading of the message is completed. .. Further, the DMA controller 33
8 stores the transfer data of one message in the memory device 304
When the writing is completed, the data processing device 302 is interrupted by the signal line 346 to notify that the message has arrived.

Next, error control when a PE receives a message will be described. The message read from the buffer 331 by the buffer read control 332 is held in the register 333. The parity of the contents of the data signal 344 of the register 333 is checked by the parity check 336. The result of this parity check and the data error signal 350 are logically ORed by the OR circuit 339 and become the input to the machine check latch 337. The set condition of the machine check latch 117 is a delay latch 335 that delays and stores the set condition signal 334. As a result, the buffer read control 33
The parity check of the message is performed every time the data is read from 2 to the register 333. At this time, if a parity error occurs in the message information, the machine check latch 337 is set to 1. The output of the machine check latch 337 is connected to the data processing device 302, and if it is 1, it becomes a machine check interrupt factor and a machine check interrupt is generated in the data processing device 302.
The data processing device 302 accepts this machine check interrupt and performs interrupt processing. This interrupt processing reports that a failure has occurred in the host via the SVP. In accordance with the report, the host notifies the PE group executing the related job of the stop of the execution and cancels the job. In SVP, system reconfiguration is performed. Furthermore, this machine check latch 33
When the output of 7 is 1, the clock of the receiver 303 is stopped by the clock distribution circuit 161 and freezes. However, the buffer read control 332 is controlled to receive a message. At this time, buffer reading control 3
32 does not set the message read from the buffer 331 in the register 333 in order not to destroy the contents of the register in which a data error has occurred.

Network 101 as described in FIG.
Has a port number register 140 that holds a port number indicating which port each message sending control 130 is connected to. Such configuration control information is used, for example, to distinguish the same LSI or the like repeatedly when configuring the network, and is set up in advance by SVP or the like.
Once set, it is unlikely to change. But,
For example, if the port number register 140 is set incorrectly,
Although the message is correct, it is transferred to a PE that has nothing to do with it, causing a malfunction. For this reason, it is necessary to have a function of checking whether the message has reached the PE correctly. FIG. 7 shows the configuration of the PE including that function. This function is realized by the message comparison circuit 701 and is otherwise the same as the PE described in FIG.

The message comparison circuit 701 comprises a PE counter circuit 702 and a PE condition generation circuit 703. The PE counter circuit 702 receives the message start signal 3
At 42, the selector 721 selects 1 and the PE message counter 722 is initialized to 1 by using the output of the delay latch 355 as a set condition. After that register 3
When the data signal 344 is set to 33, PE
The message counter 722 increases.

In the PE condition generation circuit 703, the PE routing counter 731 and the PE message counter 722 are used.
Are compared by the counter comparator 732. In addition, the contents of the data signal 344 held in the register 333 and the contents of the comparison data register 733 are the message comparator 73.
Compared in 4. PE routing counter 73
1 is the comparison data register 7 in the message comparator 734.
33 shows which information in the message to be transmitted is compared with the content of 33, and is represented by the number of times set in the data signal 344, similarly to the routing counter 231 of the network 101, and is set up in advance by the data processing device 302. ing. In addition, the comparison data register 73
Reference numeral 3 is information to be compared with the content of the message, which is set up in advance by the data processing device 302. The message comparator 734 becomes 1 when the two inputs match, and its output becomes the input of the external interrupt latch 735. The output of the counter comparator 732 is 1, that is, the PE routing counter 731 and the PE message counter 722.
When the contents of are equal, the output and the set condition signal 334
Delay latch 335 and AN for delaying and storing
D is taken and the external interrupt latch 735 is set. When the external interrupt latch 735 becomes 1, the output of the external interrupt latch 735 is connected to the data processing device 302, which causes an external interrupt and causes the data processing device 302 to operate.
An external interrupt occurs.

In order to check the setting error of the port number register 140, in the case of the message format of FIG. 4, the data processing device 302 sets the PE routing counter 731 to 1 and the comparison data register 733 to its own PE.
Just set the number. Such a setting error in the configuration control information may be detected only once after the parallel processors are powered on.

Furthermore, the message comparison circuit 701 can be effectively used for debugging the data transfer processing between PEs of a program. This is possible by allowing the PE routing counter 731 and the comparison data register 733 to be arbitrarily set by the program executed by the data processing device 302. For example, in the message format of FIG. 4, when it is checked that data is transferred from a specific transmission PE, 3 is set in the PE routing counter 731 and the transmission PE number is set in the comparison data register 733. Also, when checking that the area that receives certain transfer data has been written,
4 may be set in the PE routing counter 731, and the transfer data storage address may be set in the comparison data register 733.

[0039]

According to the present invention, in detecting a parity error during message transfer in a network, a parity check is performed only on information necessary for determining a message route in the network, and when a parity error occurs, it is frozen. Since it can be performed, network freeze due to a parity error during message transfer can be minimized, and a plurality of jobs in parallel processors can be efficiently operated.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a network used for a parallel processor according to the present invention.

FIG. 2 is a diagram showing an example of a parity check set condition circuit used in the network of FIG.

FIG. 3 is a block diagram showing an example of a PE used with the network of FIG.

FIG. 4 is a diagram showing information on transfer between PEs according to this embodiment.

5 is a diagram showing a partial message string used in the network of FIG.

FIG. 6 is a diagram showing an embodiment of a parallel processor according to the present invention.

FIG. 7 is a configuration diagram showing another embodiment of the PE used in the parallel processor according to the present invention.

FIG. 8 is a configuration diagram of a Benes network using a 2-input-2 output crossbar switch used in the parallel processor of the present invention.

[Explanation of symbols]

101 ... Network, 102 ... Processing element, 104 ... SVP, 110 ... Message reception control,
117 ... Freezing instruction latch, 119 ... Failure point latch, 1
22 ... Message start signal, 123 ... Message end signal, 124 ... Data signal, 125 ... Data error signal, 1
30 ... Message transmission control, 140 ... Port number register, 150 ... SVP adapter, 201 ... Parity check set condition circuit, 116 ... Parity check, 401
... Receiving PE number, 402 ... Transfer control, 403 ... Sending PE
Number, 404 ... Transfer data storage address, 405 ... Transfer data length, 406 ... Transfer data, 235 ... Check latch set condition signal, 202 ... Counter circuit, 222 ... Message counter, 203 ... Condition generating circuit, 231 ... Routing counter, 232 Comparator, 337 Machine check latch, 701 Message comparison circuit, 702
... PE counter circuit, 703 ... PE condition generation circuit, 72
2 ... PE message counter, 731 ... PE routing counter, 732 ... Counter comparator, 734 ... Message comparator, 735 ... External interrupt latch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Hamanaka 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shigeo Takeuchi 5-2-1, Mizumizumotocho, Kodaira-shi, Tokyo Hitate Super LSI Engineering Co., Ltd.

Claims (9)

[Claims] 1. A processor comprising a plurality of processors, a data communication path connecting the processors, determining a transfer route using a message transferred from a source processor, and transferring the message to a destination processor. In the parallel processor, a means for discriminating at least an error in transfer path determination information in the message on the data communication path, and freezing the network when the determination means detects an error in the transfer path determination information in the message. A parallel processor characterized by comprising a freezing means for freezing the network due to an error in information other than the transfer route information in the message. 2. The discriminating means is means for discriminating an error in information other than the transfer route determination information of the message, and when discriminating the error, a signal indicating that an error has occurred is sent to the destination of the message together with the message. The parallel processor according to claim 1, further comprising means for transferring to the processor. 3. A parallel processor comprising a plurality of processors and a data communication path for determining a transfer path using a message transferred from a source processor and transferring the message to a destination processor. A means for discriminating an error in the message for determining the transfer route in the data communication path; and when the discriminating means discriminates an error in the transfer route determining information in the message, the transfer of the message is stopped and the discriminating means A parallel processor characterized in that it has means for transferring to the second processor together with a message that an error has occurred when an error other than the transfer route determination information of the message is determined. 4. The parallel processor according to claim 1, further comprising means for classifying each error and notifying the service processor when an error in transfer control information or an error in other information is detected by the judging means. .. 5. The processor has error detecting means for detecting a data error in the message, and means for notifying the processor of a data error when the error detecting means detects an error in the message. The parallel processor according to claim 3. 6. A parallel processor comprising a plurality of processors and a data communication path connecting the processors to transfer messages between the processors, wherein each processor holds comparison data set by the processor. Comparison data holding means, means for comparing the message transferred from the data communication path with the comparison data, and interruption means for interrupting the processor when the comparison means detects a match A parallel processor characterized by being provided with. 7. The interrupt means counts the number of pieces of information in a message transferred from the data communication path to the processor by holding the comparison timing data set by the processor, and the comparison timing. 7. The parallel processor according to claim 6, further comprising an interrupt factor setting unit that compares the result of the comparing unit with the holding unit, and instructing to hold the result of the comparing unit in the interrupt factor holding unit. 8. The parallel processor according to claim 7, wherein the comparison data holding means and the comparison timing holding means can be designated by a program. 9. A parallel processor comprising a plurality of processors and a data communication path connecting the processors, a judgment means for judging an error in transfer path determination information in a message in the data communication path, and the judgment means. A parallel processor, characterized in that, when an error in the transfer route determination information of the message is detected by the above, a part of the route related to the passage of the message in the data communication path is selectively frozen.