JPH0581219A - Microprocessor operation control device - Google Patents

Abstract

PURPOSE:To suppress the transfer of an instruction code in the case of executing the same processing as the preceding one in order to minimize the lowering in a DSP execution speed due to the transfer of the instruction code from a host microprocessor to an internal instruction RAM in a DSP. CONSTITUTION:A CPU 30 selectively sets up each processing number corresponding to each processing contents of the DSP 40 in an internal data RAM 41 and starts the execution of the DSP 40 in each setting. When the set processing number in the RAM 41 corresponds to a, DSP program number stored in the RAM 42 in each starting, the DSP 40 executes processing contents corresponding to the DSP program number based upon DSP program stored in the RAM 42. When the DSP 40 judges no correspondence, the host microprocessor transfers and stores the DSP program with the program number corresponding to the processing number set up in the RAM 41 to/in the RAM 42.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having an instruction random access memory (hereinafter referred to as an internal instruction RAM) inside a chip and executing an operation in accordance with an instruction read from the internal instruction RAM. In particular, the present invention relates to a microprocessor operation control device suitable for controlling instruction execution of a digital signal processor (hereinafter referred to as DSP) of the microprocessor.

[0002]

2. Description of the Related Art Conventionally, in a DSP having an internal instruction RAM and functioning as a slave microprocessor, a central processor of a host microprocessor is operated before execution.
A processing unit (hereinafter referred to as CPU) normally reads an instruction code from its internal memory and transfers it to the internal instruction RAM of the DSP.

[0003]

By the way, in such a DSP, the capacity of the internal instruction RAM is usually limited to several hundred steps due to the restriction of the chip area. Therefore,
When many processing contents are performed by a single DSP, there is a problem that it is necessary to replace the instruction code contents in the internal instruction RAM. However, exchanging the instruction code contents in the internal instruction RAM every time prior to the execution of each processing content of the DSP causes a problem that the execution speed of the DSP is lowered. Also, if the DSP instruction code or program configuration is changed at the development stage, the CPU cannot transfer the instruction code unless the CPU recognizes the change.
This causes a problem that the CPU program needs to be changed in accordance with the DSP program change. In view of the above, the present invention minimizes the decrease in the execution speed of the DSP in the microprocessor operation control device due to the transfer of the instruction code from the host microprocessor to the internal instruction RAM of the DSP. Therefore, when the same processing as the previous time is performed, the instruction code is not transferred, and even if the DSP program is changed, the host microprocessor program need not be changed. is there.

[0004]

To solve the above problems, the configuration of the present invention has a role as a slave microprocessor having a host microprocessor, an internal data RAM and an internal instruction RAM, as illustrated in FIG. And a DSP that fulfills the above, and the host microprocessor stores in advance a plurality of DSP programs respectively representing a plurality of processing contents of the DSP together with their respective program numbers, and a plurality of processing contents of the DSP. It has processing number setting means 2 for selectively setting the corresponding processing numbers in the internal data RAM, and start means 3 for starting the execution of the DSP after setting by the processing number setting means 2. DS
P starts the internal data RA when the DSP starts.
The set process number in M is the DSP in the internal instruction RAM
Judgment means 4 for judging whether or not it corresponds to the program number, and execution means 5 for executing the corresponding processing contents based on the DSP program in the internal instruction RAM when the judgment means 4 judges that it corresponds. In addition, when the determination means 4 determines that they do not correspond, the host microprocessor stores, from the storage means 1, the DSP program having the program number corresponding to the processing number set in the internal data RAM. This is because it is transferred to the instruction RAM.

[0005]

When the processing number setting means 2 of the host microprocessor selectively sets each processing number corresponding to a plurality of processing contents of the DSP in the internal data RAM, the start means 3 for each of the sets. DS
Start execution of P. Then, at each start, the determination means 4 of the DSP causes the internal data RAM to
It is determined whether or not the set process number in the internal instruction RAM corresponds to the number of the DSP program in the internal instruction RAM. When the execution means 5 determines that the determination means 4 corresponds, the DSP program in the internal instruction RAM is determined. Then, the processing content corresponding to this is executed. When the determination means 4 determines that the host microprocessor does not support,
The DSP program having the program number corresponding to the processing number set in the internal data RAM is transferred from the storage means 1 to the internal instruction RAM and stored therein. Then, based on the determination by the determination unit 4 similar to that described above, the execution unit 5 transfers the DS transferred and stored in the internal instruction RAM.
The corresponding processing content is executed based on the P program.

[0006]

As described above, unless the judgment means 4 judges that it does not correspond, the execution means 5 is executed without changing the DSP program in the internal instruction RAM. DS in instruction RAM
The decrease in the execution speed of the DSP due to the replacement of the P program can be performed without increasing the capacity of the internal instruction RAM.
It can be suppressed to a minimum. Further, D in the internal instruction RAM
When the SP program is replaced, the host microprocessor only needs to transfer the DSP program from the storage means 1 to the internal instruction RAM on the basis of the judgment by the judgment means 4 that it does not correspond. Therefore, the program of the host microprocessor is changed. Is unnecessary.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an example in which the present invention is applied to a fingerprint collation system. The fingerprint collation system includes an image input device 10. The image input device 10 optically detects the fingerprint of the fingerprint collator when the finger of the fingerprint collator is pressed against the reading screen of the image sensor. The read fingerprint image is generated as a fingerprint image output signal. The interface 20 receives the fingerprint image output signal from the image input device 10 as the CP of the host microprocessor.
Output to U30. The CPU 30 uses the interface 2
0, the DSP 40, the DMA controller 60, etc., execute the main control program and the interrupt control program according to the flowcharts shown in FIGS. 3 to 6, and during this execution, the arithmetic processing required for fingerprint collation is performed. Further, the CPU 30 has a built-in memory (hereinafter referred to as CPU memory), and the memory area 3 of this CPU memory.
DSP 40 of 3 (hereinafter referred to as CPU memory area 33)
The four DSP programs 1, 2, 3 and 4 are stored in advance in the DSP instruction code holding area 33a for. The main control program and the interrupt control program described above are stored in advance in the CPU memory area 33.

The DSP 40 functions as a slave microprocessor and has a data RAM 41 having a communication area (hereinafter referred to as internal data RAM).
And the internal instruction RAM 42 are built in, and the internal instruction RA
The M42 temporarily stores the instruction content of the DSP 40 as data. Further, the DSP 40 executes the DSP control program in accordance with the flowchart shown in FIG.
When interrupting the PU 30, an interrupt signal is generated and output to the CPU 30. The DSP 40 is a DSP
Data is output to the external data RAM 45 via the address bus 43 and the DSP data bus 44 so as to be temporarily stored in the external data RAM 45. The above DSP
The control program is stored in the DSP 40 in advance.

Further, each processing number and each program number of each processing content performed by the DSP 40 correspond to each processing content of the DSP 40 as shown in Table 1 below.

[Table 1] However, as shown in Table 1, each of the process numbers 1 to 4 has a DSP 40
One-to-one correspondence to each processing content of
Regarding the correspondence relationship between each processing content of P40 and each program number, a single program number 2 corresponds to both processing content of minutiae position and direction calculation and position shift and rotation amount calculation. Each program number is DSP
No. of program in the instruction code holding area 33a
It represents whether each processing content of 40 is included.

The following Table 2 shows a program number table. In this program number table, the program numbers in Table 1 are arranged in the order of processing numbers from the upper column to the lower column of the table. However, this program number table is stored in the internal data RAM 41 of the DSP 40.

[Table 2]

The following Table 3 shows each data set in the communication area of the DSP 40, and each of these data is transferred between the DSP 40 and the CPU 30.

In the address decoder 50, the CPU 30
When it is necessary to access SP40, the same CPU30
The access command from is decoded and output to the DSP 40 as a DSP selection signal. Also, this address decoder 5
When the CPU 30 accesses the direct memory access controller 50 (hereinafter referred to as the DMA controller 60), 0 decodes the access command from the CPU 30 and outputs it to the DMA controller 60 as a DMA selection signal. The DMA controller 60 transfers necessary data from the CPU 30 through the CPU data bus 31 to the internal data RAM 41 and the internal instruction RAM 42 of the DSP 40 in response to the DMA selection signal from the address decoder 50 and the DMA signal from the CPU 30.

In the present embodiment configured as described above,
When the system of the present invention is in the operating state, the CPU 30 starts the execution of the main control program in step 100 according to the flowcharts of FIGS. At this stage, if the fingerprint image output signal is output from the image input device 10 to the interface 20, the CPU 30 causes the step 1
At 01, the fingerprint image output signal is input from the interface 20. Then, the CPU 30 executes the step 1
At 02, the value of the fingerprint image output signal is binarized to create a ridge crest image of the fingerprint, and at step 103, the ridge crest image is inverted to create a ridge valley image of the fingerprint. Step 10
In step 4, the ridge mountain image in step 102 is thinned, and in step 105, the processing number 1 corresponding to the calculation of minutiae position and direction in the processing content of the DSP 40 is communicated in the internal data RAM 41 of the DSP 40. Set in the area and advance the main control program to the next step 106.

When the main control program proceeds to step 106 in this way, the CPU 30 starts the DSP 40, at step 107, the ridge-valley image at step 103 is thinned, and at step 110, "N" is displayed.
The determination of "O" is repeated. In addition, as described above, the DSP4
When 0 is started, the DSP 40 starts executing the DSP control program in step 300 according to the flowchart of FIG. Next, in the next step 310, the DSP 40 reads the processing number 1 already set in the communication area of the internal data RAM 41, and advances the DSP control program to step 320.

The process number 1 read out in step 310 has already been transferred to the internal instruction RAM 42.
If the processing number that can be executed by the program does not match, the DSP 40 determines “NO” in step 320, refers to the program number table in the internal data RAM 41 in step 350, and reads in step 310. The program number 1 corresponding to the process number 1 is set in the communication area of the internal data RAM 41, and in step 360, the program change request flag is set in the communication area to set DS.
The P control program proceeds to step 370.

When the DSP control program proceeds to step 370 in this way, the DSP 40 interrupts the CPU 30. Then, the CPU 30 stops the execution of the main control program and starts the execution of the interrupt control program in step 200 according to the flowchart of FIG.
At step 210, it is checked whether the end flag is set. At this stage, since the end flag is not set based on the determination of “NO” in step 320 as described above, the CPU 30 determines in step 230 in step 230 based on the determination of unfinished in step 210.
Check whether the program change request flag is set. At this time, since the program change request flag is set in step 360 as described above, the CPU 3
0 determines in step 230 that there is a program change request, and in step 250, the internal data RAM 4
The program number 1 is acquired from the communication area of 1.

When the CPU 30 causes the address decoder 50 to output the DMAC selection signal to the DMA controller 60 in step 260 in order to transfer the DSP program designated by the program number 1 to the internal instruction RAM 42 of the DSP 40. This DMA controller 6
0 is the DS in the CPU memory area 33 of the CPU 30
The DSP program 1 is read from the P instruction code holding area 33a, transferred to the internal instruction RAM 42, and newly stored. Then, the CPU 30 sends the D
The SP 40 is started, and in the next step 280, the execution of the interrupt control program ends.

As described above, the DSP 4 in step 270.
When 0 is started, the DSP 40 starts executing the DSP control program in step 300 according to the flowchart of FIG.
The process number 1 in the communication area of M41 is read. At this stage, since the processing number 1 read out as described above corresponds to the DSP program already transferred to the internal instruction RAM 42 in step 260, the DSP 40 determines “YES” in step 320, and the internal instruction RAM
In step 330, based on the DSP program 1 that has been transferred to 42, a process of calculating the position and direction of the minutiae is executed based on the ridge mountain image thinning result in step 104, and in step 340, an end flag. Is set in the communication area of the internal data RAM 41, and the CPU 30 is interrupted in step 370.

Therefore, the CPU 30 starts the execution of the interrupt control program in the same manner as described above, and step 210
At step 340, it is determined that the end flag has been set and the execution of the interrupt control program is ended at step 220. After that, CP
In step 110 of the main control program, U30 determines "Y" based on the setting of the end flag in step 340.
ES ", the process number 2 for removing pseudo minutiae is set in the communication area of the internal data RAM 41 in step 111, and the next step 112
Start the DSP 40 at step 120 and
The determination of "NO" is repeated.

As described above, in step 112, the DSP 4
When 0 is started, the DSP 40 follows step 310 of the DSP control program according to the flowchart of FIG.
Then, the processing number 2 which has been set is read in the communication area of the internal data RAM 41, and the DSP control program is advanced to step 320. At the present stage, the process number 2 read in step 310 is
Since the processing number 1 that can be executed by the DSP program already transferred to the internal instruction RAM 42 does not match, the DSP 40
It is determined to be “NO” in step 320, and step 350
In reference to the program number table in the internal data RAM 41, the program number 2 corresponding to the process number 2 read in step 310 is stored in the internal data RAM 4
In step 360, the program change request flag is set in the communication area and the DSP control program proceeds to step 370 to interrupt the CPU 30.

When the CPU 30 is interrupted in this way, the CPU 30 stops the execution of the main control program and shifts to the execution of the interrupt control program according to the flowchart of FIG. Based on the determination of “NO” in 320, it is determined that the program has not ended, and in step 230, it is determined that there is a program change request based on the setting of the program change request flag in step 360 as described above. In step 250, the program number 2 is acquired from the communication area of the internal data RAM 41. Then, in order to transfer the DSP program designated by the program number 2 to the internal instruction RAM 42 of the DSP 40,
When the address decoder 50 outputs the DMAC selection signal to the DMA controller 60 in step 260, the DMA controller 60 reads the DSP program 2 from the DSP instruction code holding area 33a in the CPU memory area 33 of the CPU 30. It is transferred to the internal instruction RAM 42 and newly stored. Then, CP
The U30 starts the DSP 40 in step 270, and ends the execution of the interrupt control program in step 280.

Thus, in step 270, the DSP 40
7, the DSP 40 executes the DSP control program according to the flowchart of FIG. 7, and reads the process number 2 in the communication area of the internal data RAM 41 in step 310. At the present stage, since the processing number 2 read out as described above corresponds to the DSP program already transferred to the internal instruction RAM 42 at step 260, the DSP 40 sends “YE” at step 320.
S ”, and the DS already transferred to the internal instruction RAM 42
Based on the P program 2, in step 330, the pseudo minutiae removal process is executed based on the above calculation result of the position and direction of the minutiae, and in step 340,
The end flag is set in the communication area of the internal data RAM 41, and in step 370, the CPU
Interrupt 30. Therefore, the CPU 30 starts the execution of the interrupt control program in the same manner as described above, determines in step 210 that the end has been set in step 340 and the interrupt control is executed in step 220. Terminates program execution.

After that, the CPU 30 determines "YES" in step 120 of the main control program based on the setting of the end flag in step 340, and then executes step 1
At 21, the processing number 3 for calculating the position shift and the rotation amount
Is set in the communication area of the internal data RAM 41, the DSP 40 is started in the next step 122, and the determination of "NO" is repeated in step 130. Thus, in step 122, the DSP 40
7, the DSP 40 reads the process number 3 already set in the communication area of the internal data RAM 41 in step 310 of the DSP control program according to the flowchart of FIG. 7, and advances the DSP control program to step 320.

At the present stage, the process number 3 read out as described above corresponds to the DSP program already transferred to the internal instruction RAM 42 in step 260.
However, in step 320, it is determined to be “YES”, and based on the DSP program 2 transferred to the internal instruction RAM 42, in step 330, based on the calculation result of the position and direction of the minutia described above, the positional deviation and the rotation amount Is executed, the end flag is set in the communication area of the internal data RAM 41 in step 340, and the CPU 30 is interrupted in step 370. Therefore, the CPU 30 starts the execution of the interrupt control program in the same manner as described above, and step 210
At step 340, it is determined that the end flag has been set and the execution of the interrupt control program is ended at step 220.

After that, the CPU 30 determines "YES" based on the setting of the end flag in step 340 in step 130 of the main control program, and the step 1
At 31, the affine transformation process number 4 is set to the internal data RA.
It is set in the communication area of M41, the DSP 40 is started in the next step 132, and the determination of "NO" is repeated in step 140.
When the DSP 40 is started in step 132 in this way, the DSP 40 follows the flowchart of FIG.
In step 310 of the DSP control program, the processing number 4 which has been set in the communication area of the internal data RAM 41 is read and the DSP control program is advanced to step 320.

At the present stage, since the process number 4 read out as described above does not correspond to the DSP program transferred to the internal instruction RAM 42 at step 260, the DSP 4
0 determines “NO” in step 320, refers to the program number table in the internal data RAM 41 in step 350, and determines the program number 3 corresponding to the process number 4 already read in step 310 as internal data. R
Set it in the communication area of AM41, and
In step 360, the program change request flag is set in the communication area, the DSP control program is advanced to step 370, and the CPU 30 is interrupted.

Then, the CPU 30 stops the execution of the main control program and executes the interrupt control program in accordance with the flowchart of FIG. 6, determines in step 210 that it is not completed as described above, and in step 230, Based on the setting of the program change request flag in step 360 as described above, it is determined that there is a program change request, and in step 250, the program number 4 is acquired from the communication area of the internal data RAM 41. Then, in order to transfer the DSP program designated by the program number 4 to the internal instruction RAM 42 of the DSP 40, the CPU 30 sends the DMAC selection signal from the address decoder 50 in step 260 to the DMA controller 6 in step 260.
When it is output to 0, this DMA controller 60
The DSP program 4 is read from the DSP instruction code holding area 33a in the CPU memory area 33 of the PU 30, transferred to the internal instruction RAM 42, and newly stored. Then, the CPU 30 causes the DSP 40 to proceed in step 270.
Is started, and in the next step 280, the execution of the interrupt control program is ended.

As described above, in step 270 the DSP 4
When 0 is started, the DSP 40 executes the DSP control program according to the flowchart of FIG. 7, and reads the process number 4 in the communication area of the internal data RAM 41 in step 310. At this stage, the process number 4 read out as described above corresponds to the DSP program already transferred to the internal instruction RAM 42 at step 260, so that the DSP 40 sends “YE” at step 320.
S ”, and the DS already transferred to the internal instruction RAM 42
Based on the P program 4, in step 330, the affine transformation processing is executed based on the above-described position shift and rotation amount calculation results, and in step 340, the end flag is set in the communication area of the internal data RAM 41.
At step 370, the CPU 30 is interrupted.

Therefore, the CPU 30 starts the execution of the interrupt control program in the same manner as described above, and step 210
At step 340, it is determined that the end flag has been set and the execution of the interrupt control program is ended at step 220. After that, CP
In step 140, the U30 determines “YES” in substantially the same manner as described above, and in step 150, performs pattern matching between the registered fingerprint image of the fingerprint collator and the collated fingerprint image after the affine transformation. At 160, a match / mismatch between the registered fingerprint image and the matching fingerprint image is determined based on the pattern matching result. However, the above registered fingerprint image is stored in advance in the CPU memory area of the CPU 30.

As described above, in the fingerprint collation of the fingerprint collator, the pseudo minutiae removal process and the misregistration / rotation amount calculation process are performed in the arithmetic processing process by the cooperation of the CPU 30 and the DSP 40 as described above. Is continued as described above, the pseudo minutiae removal process and the misregistration and rotation amount calculation process in step 330 are performed through the arithmetic processes of steps 111 to 122 in the main control program and the execution of the DSP control program. , DSP program 2 in internal instruction RAM 42
Is executed without being changed, the number of times the DSP program is replaced in the internal instruction RAM 42 can be suppressed to a minimum, and as a result, the DSP 40 can be executed while minimizing the capacity of the internal instruction RAM 42. Can improve speed. In such case, internal instruction RAM
Replacing the DSP program in 42 does not require modification of the CPU 30 program. Further, after the thinning process of the ridge mountain image in step 104 of the main control program, the DSP 40 started in step 106 calculates the minutiae position and direction of the ridge mountain image in step 330, and the ridge valley image in the CPU 30. Since the thinning process is performed in parallel, the CPU 30 and the DSP
The execution processing speed by the cooperation of 40 can be improved.

In implementing the present invention, when the DMP controller 60 is not used, I / O read / write from the CPU 30 can access the DSP 40 side. Further, in carrying out the present invention,
Not limited to fingerprint matching system, DSP and host C
The present invention may be applied to and implemented in each system including a PU.

[Brief description of drawings]

FIG. 1 is a diagram corresponding to the description of the claims.

FIG. 2 is a block diagram of a fingerprint matching system to which the present invention is applied.

3 is a front part of a flowchart of a main control program to be executed by the CPU of FIG.

FIG. 4 is a middle section of a flowchart of the main control program.

FIG. 5 is a latter part of the flowchart of the main control program.

FIG. 6 is a flowchart of an interrupt control program to be executed by the CPU of FIG.

7 is a flowchart of a DSP control program to be executed by the DSP of FIG.

[Explanation of symbols]

30 ... CPU, 33 ... CPU memory area, 40 ... DS
P, 41 ... Internal data RAM, 42 ... Internal instruction RAM.

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[Procedure amendment]

[Submission date] November 22, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

The following Table 3 shows each data set in the communication area of the DSP 40, and each of these data is transferred between the DSP 40 and the CPU 30.

[Table 3]

Claims (1)

[Claims] 1. A host microprocessor, and a DSP having an internal data RAM and an internal instruction RAM and serving as a slave microprocessor, wherein the host microprocessor has a plurality of DSPs respectively representing a plurality of processing contents of the DSP. DS
Storage means for pre-storing the P program together with each program number, processing number setting means for selectively setting each processing number corresponding to a plurality of processing contents of the DSP in the internal data RAM, and this processing number setting And a start means for starting execution of the DSP after setting by the means, and the DSP has a set process number in the internal data RAM when the DSP starts and the DSP program in the internal instruction RAM. Means for judging whether or not the internal command R corresponds to the number
And a executing means for executing corresponding processing contents based on a DSP program in the AM, and when the judging means judges that the processing contents do not correspond, the host microprocessor has already set in the internal data RAM. DS of the program number corresponding to the processing number of
A microprocessor operation control device adapted to transfer a P program from the storage means to the internal instruction RAM.