JPH0575969A - Video signal recorder - Google Patents

Abstract

PURPOSE:To suppress the breaking of a picture due to burst error or the like to the degree for compression or lower at the time of non-compression in a video signal recording device which selectively performs compression recording and non-compression recording. CONSTITUTION:A memory 101 outputs an inputted video signal with one 8X8-picture element block as the unit. A compressing circuit 102 compresses picture data of block units by DCT. A data shuffling circuit 103 reconstitutes data inputted with one block as the unit and successively outputs every 8th picture element in the horizontal direction. A selector 104 selects the output of the compressing circuit 102 or the data shuffling circuit 103 and outputs it to an error correction encoder 105. A subcode generating part 107 generates a subcode including information of compression/non-compression or the like related to the signal to be recorded. A channel encoder 106 encodes picture data and the subcode and records them on a recording medium 110 through a recording head 109.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called digital video recorder for digitally processing and recording video signals.

[0002]

2. Description of the Related Art In recent years, digital processing of video signals has been widely studied as means for recording / reproducing or transmitting the video signals with higher quality. In general, since the information amount of image data is enormous, it is indispensable to compress the information amount of the image data so as to match the characteristics (bit rate) of the transmission path and the recording medium for image transmission and recording. In order to improve the efficiency of such digital transmission and recording, a high-efficiency coding technique for coding image data at a smaller bit rate is required, and various systems are being studied for standardization. For example, CCITT (Comite Consulta
fif International Telegraphique et Telephonique)
Is the proposed standardization recommendation H.261 for video conferencing / video telephony,
JPEG (Joint Photographic Expert) for color still images
s Group) system (Nikkei Electronics 19
90.10.15 (No.511) "Detailed description of unified high-efficiency image coding method". All three of these proposals are DC
It is a system based on T (discrete cosine transform).

In addition to the above-mentioned MPEG system, there is also a system that employs only intra-picture coding as a moving image coding system. Figure 8 shows "AN EXPERIMENTAL STUDY FOR A HOME
FIG. 3 is a block diagram showing a configuration of a high-efficiency encoding recording / reproducing apparatus of this type proposed in “-USE DIGITAL VTR” (IEEE vol.35, No.3, Aug.1989). In the figure, 1 is a frame memory for converting an input interlaced video signal into a frame structure, and 2 is a video signal converted into a frame structure by the frame memory 1 in horizontal and vertical 8 × 8 pixels. Bit rate reduction circuit that reduces the amount of information by DCT, and adds a parity for error correction, and a fixed-length sync block that synchronizes the variable-length data of each block with the synchronization signal. An encoder 4 for converting into an audio signal, an audio processing circuit 4 for digitally processing an audio signal, and a video signal 5 input from the encoder 3 and an audio signal input from the audio processing circuit 4 according to the characteristics of the recording medium 8. A channel encoder for recording and encoding, 6 a recording amplifier, 7 a magnetic recording head, 8 a recording medium such as a magnetic tape, 9 For example, a magnetic reproduction head, 10 is a reproduction amplifier, 11 is a detector that detects the bit clock of the reproduction signal, decodes the recorded data, and performs TBC processing to correct the time axis, and 12 is a random error and burst that occurred during recording and reproduction. A decoder that corrects errors using a correction code, 13 is a bit rate decoder that decodes the variable-length code input from the decoder 12, performs inverse quantization processing and inverse DCT processing, and restores the original information. , 14 is a bit rate decoder 1
A frame memory for converting the data decoded by 3 into an interlaced video signal, and a voice processing circuit 15 for restoring the voice signal input from the detector 11.

FIG. 9 is a block diagram showing a detailed structure of the bit rate reduction circuit 2. As shown in the figure, the bit rate reduction circuit 2 is composed of a DCT circuit 16, a buffer memory 17, an adaptive quantization circuit 18, a data amount evaluation circuit 19, and a variable length coding circuit 20. A block unit signal composed of 8 × 8 pixels input from the frame memory 1 is subjected to two-dimensional DCT by the DCT circuit 16 and converted into a frequency component. This reduces the spatial correlation component. The DCT-processed signal is input to the adaptive quantization circuit 18 via the buffer memory 17 and requantized. This reduces the redundancy of one block.
At this time, the adaptive quantization circuit 18 uses the data amount evaluation circuit 19
Quantization is performed using the coefficient based on the DCT result input from. In the variable length coding circuit 20, for example, Huffman coding is performed based on the result calculated from the statistical code amount of the quantized output. As a result, short bits are assigned to data with a high appearance probability and long bits are assigned to data with a low appearance probability, and the amount of transmission is further reduced. In this way, the bit rate reduction circuit 2 outputs the 162 Mbps video signal to 19
Compress to Mbps. That is, the data amount of the video signal is 1/8
Is compressed into.

The signal thus compressed is converted into a fixed-length sync block as shown in FIG. 10 by the encoder 3 and then sequentially recorded on the recording medium 8. At that time, in consideration of special reproduction, etc., on the recording medium 8,
As shown in FIG. 11, each sync block is arranged in a form corresponding to the screen position. Measures against tape burst errors and the like are implemented in the addition of validity calculation.

That is, when the Y signal is sampled at 13.5 MHz and the Cr and Cb signals are sampled at 6.75 MHz, the effective pixels are 720 horizontal pixels and 4 vertical pixels as shown in FIG.
It becomes 80 pixels. When this is cut out in blocks of 8 × 8 pixels, which is the processing unit of DCT, the number of blocks per frame is 5400 blocks. This is recorded on two tracks as shown in the figure.

By the way, the data amount of the video signal is compressed to 1/8 and recorded as described above. When sampling, 16 bits per pixel (Y: 8 bits / 1 sample, Cr,
Cb: 4 bits / 0.5 samples), but it is compressed to 2 bits per pixel during recording. Therefore, FIG.
The distance A on the recording medium between the pixels at the same position in the blocks adjacent to each other in the horizontal direction is 128 bits (2 bits / pixel × 64 pixels). In addition, the distance B between pixels at the same position in vertically adjacent blocks is 11520 bits (2 bits /
X 64 pixels x 90 blocks).

However, here, when the video signal is recorded without compression, if the pixels are sequentially recorded as in the case of compression, the number of bits per pixel is 16 bits, so the distance between adjacent pixels is 128 bits each (16 bits / pixel ×
8 pixels, 92160 bits (16 bits / pixel x 720 pixels x)
8 lines), which is significantly different from the case of compressed recording.

[0009]

When recording / reproducing or transmitting a video signal by digital processing, it is desired to be able to select and use either compressed recording or non-compressed recording depending on the situation. However, the conventional video signal recording device has a problem that the pixel position on the screen and the inter-pixel distance on the recording medium greatly differ between compressed and uncompressed. That is, since the distance between pixels is different between the compressed state and the non-compressed state, the burst error handling capability is different, and the influence on the image is greatly changed. That is, when a burst error occurs during compressed recording, the image breaks down into blocks, but during non-compressed recording, horizontal pull-out noise occurs.

[0010]

According to the present invention, there is provided a quantizing means for quantizing a video signal pixel by pixel, and information of the pixel is compressed by recording horizontal and vertical 8 × 8 pixels as a unit block and recorded. It comprises a compression recording means for sequentially recording on the medium, and a non-compression recording means for recording the information of the pixels on the recording medium in sequence in the horizontal direction at intervals of every 8 pixels.

[0011]

In the present invention, the uncompressed pixel data is set in the horizontal direction.
Since the data is recorded on the recording medium sequentially at intervals of 8 pixels, the distance between pixels when compressed and when not compressed becomes equal to or less than the same, and the image failure when a burst error occurs can be processed to the same degree.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a video signal recording / reproducing apparatus according to an embodiment of the present invention. The video signal recording / reproducing apparatus (digital VTR) 100 shown in the figure includes a frame memory 101, a compression circuit (bit rate reduction circuit) 1
02, data shuffling circuit 103, selector 10
4, error correction encoder 105, channel encoder 106, subcode creation unit 107, recording amplifier 10
8, recording head 109, magnetic tape 110, reproducing head 111, reproducing amplifier 112, detector 113, error correction decoder 114, selector 115, decompression circuit 11
6, data deshuffling circuit 117, selector 11
8, subcode decoder 119, frame memory 120
The main part is composed of.

The frame memory 101 converts an input interlaced video signal into a frame structure, and outputs to the compression circuit 102 each horizontal and vertical 8 × 8 pixel as a unit block. That is, the Y signal is 1
Pixel data obtained by sampling Cr and Cb signals at 6.75 MHz at 3.5 MHz is sequentially stored and read out in 8 × 8 pixel units.

The compression circuit 102 is a frame memory 101.
The amount of information of block-wise pixel data input from
Reduce by T.

The data shuffling circuit 103 reconstructs pixel data in block units input from the frame memory 101 into a frame structure, and sequentially outputs predetermined pixel data according to a transmission method. Transmission methods include frame feed transmission and partial transmission. Either method is a means for transmitting uncompressed data at the same bit rate as that at the time of compression, and the bit rate is reduced by thinning out the data instead of compressing the pixel data. That is, V
In TR, 1 frame of data is 2 when compressed and recorded.
The data is recorded on tracks, but the same recording density is achieved by recording one frame of data on 16 tracks during uncompressed recording.

The selector 104 selects the signal from the compression circuit 102 and the data shuffling circuit 1 according to the recording method.
One of the signals from 03 is selected and output to the error correction encoder 105.

The error correction encoder 105 calculates an error correction parity signal from the input signal, adds it to the signal, and converts it into a fixed-length sync block as shown in FIG.

The channel encoder 106 encodes the signal input from the error correction encoder 105 according to the characteristics of the magnetic tape 110. The encoded signal is amplified by the recording amplifier 108, and then the recording head 10
9 is sequentially recorded on the magnetic tape 110.

The sub-code creating section 107 creates a sub-code including these pieces of information according to each signal of the transmission method (frame feed or partial transmission) and the recording method (compressed recording or non-compressed recording), Add to image data.

The reproduction amplifier 112 amplifies the reproduction signal input from the reproduction head 111 and outputs it to the detector 113.

The detector 113 detects the bit clock of the reproduced signal, decodes the recorded data, and performs TBC processing for correcting the time axis.

The error correction decoder 114 corrects random errors, burst errors and the like that occur during recording and reproduction using a correction code.

The expansion circuit 116 decodes the variable length code,
Inverse quantization processing and inverse DCT processing are performed to restore the original block unit data.

The data deshuffling circuit 117 reconstructs the reproduced signal and outputs it in block units of 8 × 8 pixels.

The frame memory 120 converts pixel data in block units into interlaced video.

The subcode decoder 119 extracts information such as recording method and transmission method from the subcode included in the reproduction signal.

The selectors 115 and 118 switch the flow of signals based on the recording method information output from the subcode decoder 119.

The operation of the data shuffling circuit 103 will now be described in more detail. Data shuffling circuit 1
As described above, the signal input to 03 is a signal in which 8 × 8 pixels in the horizontal and vertical directions are used as a unit block. The input signal is once reconstructed into a frame structure as shown in FIG. 2, and then pixel data is read out according to a transmission method or a shuffling method. For example, horizontal 8
The pixels are sequentially read out. The arrangement on the magnetic tape in this case is shown in FIG. As a result, the inter-pixel distance on the magnetic tape is 128 bits / 8 pixels in the horizontal direction and 11520 bits / 8 pixels in the vertical direction, which can be less than the inter-pixel distance during compression recording.

Next, a detailed configuration of the data shuffling circuit 103 is shown in FIG. 4, and a detailed configuration of the data deshuffling circuit 117 is shown in FIG. In FIG. 4, 121 is an input buffer, 122 is a memory for storing input block-unit data and reading it in pixel units, 123 is an output buffer, and 124 is a control for writing and reading data in the memory 122. Memory to perform, control signal generation circuit 12
Reference numeral 5 denotes a shuffling ROM for converting a virtual address signal input from the memory control signal generating circuit 124 into an address of a pixel to be actually read. That is, the memory control signal creation circuit 124 creates a write control signal, a write address, a read control signal, and a read address. This can be realized by using, for example, Toshiba TC521000P. In addition, the address at the time of writing is written to an address determined in block units of 8 × 8 pixels according to the time from the reference signal. Further, at the time of reading, the memory control signal creation circuit 124 creates a virtual address calculated by simple addition by the counter and shuffles it.
The shuffling conversion table in the ROM 125 is used as the read address, which is converted into the address to be actually read, for example, every 8 pixels. Further, the shuffling ROM 125 sends address information to the subcode creating unit 107. Sub code creation unit 107
Also incorporates this address information into the subcode.

In FIG. 5, 126 is an input buffer, 127 is a memory for temporarily storing the shuffled reproduction signal, and reconstructing it into a block of 8 × 8 pixels,
128 is an output buffer, 129 is a memory control signal generation circuit that controls writing and reading of data to the memory 127, and 130 is an address of a pixel to which the virtual address signal input from the memory control signal generation circuit 129 is actually written. Deshuffling RAM to convert to. The memory control signal creation circuit 129 uses the memory control signal creation circuit 12 as a write address to the memory 127.
Similar to 4, the virtual address is output. Deshuffling
The RAM 130 converts this virtual address into a real address based on the address information input from the subcode decoder 119. The input buffers 121 and 126 and the output buffers 123 and 128 also serve as time adjustments with the compression recording / reproducing system. In this way, shuffling ROM 12
5. By using the deshuffling RAM 130, the address information for shuffling can be easily obtained by the address conversion table regardless of the transmission method. On the other hand, since writing to the memory 122 and reading from the memory 127 have a constant periodicity, they can be easily realized without using a conversion table.

In the above embodiment, the recording is performed sequentially in the vertical direction, but the recording may be performed every other line. That is, as shown in FIG. 6, first, after recording every 8 pixels for odd-numbered lines,
Record every 8 pixels for even numbered lines. Also, it may be arranged every 8 m pixels (m is an integer of 1 or more) instead of every 8 pixels in the horizontal direction. Every n lines in the vertical direction (n is
Integer greater than or equal to 1). Further, as shown in FIG. 7, it is also convenient to correct the error by shifting the pixels to be recorded for each line in the vertical direction in the horizontal direction. That is,
Pixels 1, 9, 17, ... Are recorded in the first line, and pixels 722, 730, 738, ... are recorded in the second line.

[0033]

According to the present invention, the inter-pixel distance on the recording medium during non-compressed recording is equal to or less than the inter-pixel distance during compressed recording. Therefore, it is possible to process the image failure when the burst error occurs to the same degree.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a video signal recording / reproducing apparatus of the present invention.

FIG. 2 is a diagram showing an array of pixels forming an image.

FIG. 3 is a diagram showing an array of pixels recorded on a magnetic tape.

FIG. 4 is a block diagram showing the configuration of a data shuffling circuit.

FIG. 5 is a block diagram showing a configuration of a data deshuffling circuit.

FIG. 6 is a diagram showing an array of pixels on a magnetic tape in an example of recording every other line in the vertical direction.

FIG. 7 is a diagram showing an array of pixels on a magnetic tape in an example in which one pixel in the horizontal direction is shifted and one pixel is recorded in the horizontal direction.

FIG. 8 is a block diagram showing a configuration of a conventional example.

FIG. 9 is a block diagram showing a configuration of a bit rate reduction circuit in a conventional example.

FIG. 10 is a diagram showing a configuration of a sync block.

FIG. 11 is a diagram showing an arrangement of sync blocks on a recording pie body during compressed recording.

FIG. 12 is a diagram for explaining a distance between pixels.

[Explanation of symbols]

 101 ... Memory 102 ... Compression circuit 103 ... Data shuffling circuit 104 ... Selector 105 ... Error correction encoder 107 ... Subcode creation unit 110 ... Magnetic tape

Claims (1)

[Claims] 1. A quantizing means for quantizing a video signal pixel by pixel, and 8 × 8 horizontal and vertical information of the pixel.
Compressing and recording means for compressing information by using pixels as a unit block and sequentially recording the information on a recording medium;
A video signal recording apparatus comprising: an uncompressed recording means for sequentially recording every eight pixels on the recording medium without compression.