JPH0574961A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0574961A JPH0574961A JP23798791A JP23798791A JPH0574961A JP H0574961 A JPH0574961 A JP H0574961A JP 23798791 A JP23798791 A JP 23798791A JP 23798791 A JP23798791 A JP 23798791A JP H0574961 A JPH0574961 A JP H0574961A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- tin
- semiconductor device
- annealing
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣ、ＬＳＩなどの半
導体装置の製造方法、より詳しくは、該半導体装置の配
線の形成方法に関する。近年の半導体装置の高集積化に
伴い、配線とＳｉ基板のソース、ドレインなどのＮ+ 領
域（或いはＰ+ 領域）との電気的なコンタクトの信頼
性、さらに配線自身の信頼性を維持するのが難しくな
り、信頼性を向上させる工夫が求められている。そこ
で、配線を多層化してバリアメタル層を用いることが行
われている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as an IC and an LSI, and more particularly to a method for forming a wiring of the semiconductor device. With the recent high integration of semiconductor devices, the reliability of electrical contact between the wiring and the N + region (or P + region) such as the source and drain of the Si substrate, and the reliability of the wiring itself are maintained. It is difficult to do so, and a device to improve reliability is required. Therefore, it has been practiced to form the wiring in multiple layers and use the barrier metal layer.
【０００２】[0002]
【従来の技術】バリアメタル層としＴｉ／ＴｉＮ層が提
案されている。なお、Ｔｉ層は、ＴｉＮ層よりもかなり
薄く、密着性を高めるためおよびＴｉＮとＳｉとのコン
タクト抵抗を下げるためにバリアメタルのＴｉＮ層の下
に形成してある。このＴｉ／ＴｉＮバリア層とその上の
Ａｌ合金層と多層配線においては、例えば、スパッタリ
ングでＴｉ層を形成し、続けてスパッタリングでＴｉＮ
層を形成し、窒素（Ｎ2 ）雰囲気中でアニールし（４０
０〜４５０℃にて）、スパッタエッチングで表面クリー
ニングし、そしてＡｌ合金層をスパッタリング（または
真空蒸着）で形成している。アニールはＴｉＮ層中の窒
化されていないＴｉを窒化するためである。また、スパ
ッタリングによるＴｉＮ層形成の代わりに、Ｔｉ層をＮ
2 雰囲気中でアニールしてＴｉＮ層を形成することもで
きる。2. Description of the Related Art A Ti / TiN layer has been proposed as a barrier metal layer. The Ti layer is much thinner than the TiN layer, and is formed under the barrier metal TiN layer in order to improve the adhesion and to reduce the contact resistance between TiN and Si. In the Ti / TiN barrier layer, the Al alloy layer thereon, and the multilayer wiring, for example, a Ti layer is formed by sputtering, and then TiN is formed by sputtering.
A layer is formed and annealed in a nitrogen (N 2 ) atmosphere (40
The surface is cleaned by sputter etching (at 0 to 450 ° C.), and the Al alloy layer is formed by sputtering (or vacuum evaporation). The annealing is for nitriding unnitrided Ti in the TiN layer. Also, instead of forming the TiN layer by sputtering, the Ti layer is replaced by N
The TiN layer can also be formed by annealing in a 2 atmosphere.
【０００３】[0003]
【発明が解決しようとする課題】このＴｉ／ＴｉＮバリ
ア層の採用によって、配線に起因する半導体装置の信頼
性や歩留りの低下をかなり回避することができる。しか
し、上層金属（Ａｌ、Ａｌ合金、Ｃｕ、Ａｕなど）とＴ
ｉＮとの反応を十分に防ぐことができないので、バリア
層のバリア性をより高める必要がある。By adopting this Ti / TiN barrier layer, it is possible to considerably avoid the decrease in the reliability and yield of the semiconductor device due to the wiring. However, the upper metal (Al, Al alloy, Cu, Au, etc.) and T
Since the reaction with iN cannot be sufficiently prevented, it is necessary to further enhance the barrier property of the barrier layer.
【０００４】なお、ＴｉＮのアニール処理の時に、Ｔｉ
Ｎ層表面が酸化されることがあるが、通常は上述したよ
うに表面クリーニングを施しており、この酸化量および
酸化膜質を管理することは困難であり、かつ制御する方
法がない。本発明の目的は、Ｔｉ／ＴｉＮバリア層を用
いた多層配線において、ＴｉＮ層と上層金属層との反応
（相互拡散）を抑制し、Ｓｉ基板ないしポリシリコンま
たはシリサイドの層とのコンタクト信頼性を向上させ、
かつ該多層配線自身の信頼性を向上させることであり、
そのような多層配線を有する半導体装置の製造方法をも
提供することである。During the annealing process of TiN, Ti
Although the surface of the N layer may be oxidized, the surface cleaning is usually performed as described above, and it is difficult to control the amount of oxidation and the quality of the oxide film, and there is no control method. An object of the present invention is to suppress the reaction (mutual diffusion) between the TiN layer and the upper metal layer in the multilayer wiring using the Ti / TiN barrier layer, and to improve the contact reliability with the Si substrate or the polysilicon or silicide layer. Improve,
And to improve the reliability of the multilayer wiring itself,
Another object of the present invention is to provide a method for manufacturing a semiconductor device having such multi-layer wiring.
【０００５】[0005]
【課題を解決するための手段】上述の目的が、Ｔｉ層と
ＴｉＮ層とからなるバリア層およびその上の金属層を含
んでなる多層構造配線を有する半導体装置を製造する方
法において、該金属層の形成前に、ＴｉＮ層を酸化し
て、該ＴｉＮ層および該金属層とが反応せずかつ電気的
な導通がとれる程度の薄い酸化膜を形成する工程を有す
ることを特徴とする半導体装置の製造方法によって達成
される。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device having a multi-layered wiring including a barrier layer composed of a Ti layer and a TiN layer and a metal layer on the barrier layer. Prior to the formation of the TiN layer, there is a step of oxidizing the TiN layer to form a thin oxide film that does not react with the TiN layer and the metal layer and is electrically conductive. This is achieved by the manufacturing method.
【０００６】ＴｉＮの酸化膜の反射強度を酸化前のＴｉ
Ｎの反射強度に対して0.６５〜0.９（測定入射波長：４
８０nmにて）とすることが好ましい。金属層はＡｌ、Ａ
ｌ−Ｃｕ、Ａｌ−Ｓｉ、Ａｌ−Ｓｉ−Ｃｕ、Ａｌ−Ｃｕ
−Ｔｉ、ＣｕまたはＡｕであり、かつＴｉ層はＳｉ基
板、ポリシリコン層またはシリサイド層と接触している
ことが好ましい。The reflection intensity of the oxide film of TiN is set to Ti before oxidation.
0.65-0.9 for the reflection intensity of N (measured incident wavelength: 4
(At 80 nm) is preferred. Metal layer is Al, A
l-Cu, Al-Si, Al-Si-Cu, Al-Cu
-Ti, Cu or Au, and the Ti layer is preferably in contact with the Si substrate, the polysilicon layer or the silicide layer.
【０００７】また、生じさせるＴｉＮの酸化膜の膜厚は
５nm以下であり、これよりも厚いと配線のコンタクト抵
抗が大きく増加してしまう。反射強度は、薄膜厚測定器
（例えば、キャノン製ＴＭ００５）によってＴｉＮ層の
酸化前と酸化後と測定して、測定の入射光の波長に応じ
て、「ＴｉＮ酸化膜／ＴｉＮ」の反射強度割合を下記の
表１のようにするのが望ましい。Further, the thickness of the TiN oxide film produced is 5 nm or less, and if it is thicker than this, the contact resistance of the wiring will be greatly increased. The reflection intensity is measured before and after the oxidation of the TiN layer by a thin film thickness measuring device (for example, TM005 manufactured by Canon), and the reflection intensity ratio of "TiN oxide film / TiN" is determined according to the wavelength of the incident light in the measurement. Is preferably as shown in Table 1 below.
【０００８】[0008]
【表１】 [Table 1]
【０００９】この範囲内であれば、コンタクト抵抗を大
きく増加することなく、ＴｉＮ層のバリア性を向上させ
る。Within this range, the barrier properties of the TiN layer are improved without significantly increasing the contact resistance.
【００１０】[0010]
【作用】本発明では、ＴｉＮ層とその上の金属層との間
に薄いＴｉＮの酸化膜を形成しており、これがＴｉＮと
金属層との相互拡散を抑制し、かつ上層金属のＴｉＮ粒
界拡散をも抑制する。このことによって、ＴｉＮ層を含
む多層配線と半導体（Ｓｉ）基板のＮ+ 領域（或いはＰ
+ 領域）とのコンタクト部分における接合の信頼性が向
上し、そして、該多層配線のエレクトロマイグレーショ
ンのＭＴＦ（平均寿命）が延びる。ＴｉＮの酸化膜の膜
厚が５nm以下に制御してあるので、ＴｉＮ層とＡｌ合金
層とのコンタクトに問題はない。さらに、たとえ上層金
属層がエレクトロマイグレーションあるいはストレスマ
イグレーションによる破断となっても、ＴｉＮ層が電気
抵抗の増加を軽減して、いわゆる、積層（多層）化のメ
リットを保つことができる。In the present invention, a thin TiN oxide film is formed between the TiN layer and the metal layer thereabove, which suppresses the mutual diffusion of TiN and the metal layer, and the TiN grain boundary of the upper metal. It also suppresses diffusion. As a result, the multilayer wiring including the TiN layer and the N + region (or P
The reliability of the junction at the contact portion with the + region) is improved, and the MTF (average life) of electromigration of the multilayer wiring is extended. Since the thickness of the TiN oxide film is controlled to 5 nm or less, there is no problem in contact between the TiN layer and the Al alloy layer. Further, even if the upper metal layer is broken due to electromigration or stress migration, the TiN layer can reduce the increase in electric resistance and maintain the merit of stacking (multilayer).
【００１１】[0011]
【実施例】以下、添付図面を参照して、本発明の実施例
を含む実験によって本発明を詳細に説明する。図１に示
すような、多層配線を備えた半導体装置を作製し、その
過程でのＴｉＮ層形成後のアニール処理条件を変えるこ
とで本発明の効果を調べる。The present invention will now be described in detail with reference to the accompanying drawings by experiments including examples of the present invention. The effect of the present invention is examined by producing a semiconductor device having a multilayer wiring as shown in FIG. 1 and changing the annealing condition after the TiN layer is formed in the process.
【００１２】実験１ 先ず、Ｐ- 型Ｓｉ基板（ウエハー）１を用意し、選択酸
化によってＳｉＯ2 層２を形成し、そして、イオン注入
によってＮ+ 領域３のコンタクト領域を形成する。全面
にＢＰＳＧ層（厚さ４００nm）４をＣＶＤ法によって堆
積し、ホトリソグラフィ法でＢＰＳＧ層４をエッチング
してコンタクト領域３を表出させる（コンタクト・ホー
ル径0.６μｍ）。次に、スパッタリングによってＴｉ層
（厚さ２０nm）５を全面に堆積し、その上にスパッタリ
ングによってＴｉＮ層（厚さ１００nm）６を全面に堆積
する。これを加熱炉に入れて、アニール処理（３０分）
を施し、その際のアニール温度および雰囲気を下記のよ
うに設定する。 Experiment 1 First, a P − type Si substrate (wafer) 1 is prepared, a SiO 2 layer 2 is formed by selective oxidation, and a contact region of an N + region 3 is formed by ion implantation. A BPSG layer (thickness 400 nm) 4 is deposited on the entire surface by the CVD method, and the BPSG layer 4 is etched by the photolithography method to expose the contact region 3 (contact hole diameter 0.6 μm). Next, a Ti layer (20 nm thick) 5 is deposited on the entire surface by sputtering, and a TiN layer (100 nm thick) 6 is deposited on the entire surface by sputtering. Put this in a heating furnace and anneal (30 minutes)
And the annealing temperature and atmosphere at that time are set as follows.
【００１３】（１）アニール雰囲気に酸素ガスを添加す
る。 アニール温度（℃）… 300 、350 、375 、400、425
および450 アニール雰囲気 … Ｎ2 ８０％±５％（２４リット
ル／分）およびＯ2 ２０％±５％（６リットル／分） （２）アニール雰囲気に酸素ガスを添加しない。(1) Oxygen gas is added to the annealing atmosphere. Annealing temperature (℃)… 300, 350, 375, 400, 425
And 450 annealing atmosphere ... N 2 80% ± 5% (24 l / min) and O 2 20% ± 5% (6 l / min) (2) Oxygen gas is not added to the annealing atmosphere.
【００１４】 アニール温度（℃）… 400 および450 アニール雰囲気 … Ｎ2 １００％（３０リットル／
分） アニール雰囲気が酸素ガスを含んでいるので、加熱炉内
でＴｉＮ層の表面が酸化されて、ＴｉＮの酸化膜７を形
成する。アニール雰囲気の窒素ガスと酸素ガスとの比率
を大気での比率と同じにすることにより、加熱炉への出
し入れの際のＴｉＮの酸化効果を割合を下げる。また、
アニール温度は４５０℃以下にして、ＴｉＮの酸化膜７
の厚さが５nmを越えないようにする。Annealing temperature (° C.) ... 400 and 450 Annealing atmosphere ... N 2 100% (30 liters /
Min) Since the annealing atmosphere contains oxygen gas, the surface of the TiN layer is oxidized in the heating furnace to form the TiN oxide film 7. By setting the ratio of the nitrogen gas and the oxygen gas in the annealing atmosphere to be the same as the ratio in the atmosphere, the effect of oxidizing TiN when putting in and out of the heating furnace is reduced. Also,
The annealing temperature is set to 450 ° C. or lower, and the TiN oxide film 7 is formed.
The thickness should not exceed 5 nm.
【００１５】アニール処理後に、スパッタリングによっ
てＡｌ−Ｃｕ−Ｔｉ合金を厚さ３００nm堆積して、上層
金属層８を形成し、ホトリソグラフィ法で積層した層４
〜７をエッチングして所定パターンの多層配線９とす
る。このようにして、多層配線付きの半導体装置が得ら
れる。一方、上述のアニール処理を施すことなく、この
上層金属層８を形成し、エッチングして多層配線９とし
て半導体装置を製造する。After the annealing treatment, an Al-Cu-Ti alloy is deposited to a thickness of 300 nm by sputtering to form an upper metal layer 8 and a layer 4 formed by photolithography.
7 to 7 are etched to form a multilayer wiring 9 having a predetermined pattern. In this way, a semiconductor device with multilayer wiring is obtained. On the other hand, the upper metal layer 8 is formed and etched without performing the above-mentioned annealing treatment to manufacture the semiconductor device as the multilayer wiring 9.
【００１６】反射強度について アニール処理の前および後で、キャノン製の薄膜厚測定
器（ＴＭ００５）にてＴｉＮ層とその酸化膜に所定波長
の光を当て、その反射強度を測定して、図２に示す結果
が得られた。なお、Ｓｉ基板１の反射強度も測定して示
してある。温度４００℃、酸素ガス２０％含有の雰囲気
でのアニール処理の場合には、得られた結果から計算に
よって、入射波長ごとの「ＴｉＮ酸化膜／ＴｉＮ」の反
射強度割合を求めると、表２となる。 Reflection intensity Before and after annealing, a thin film thickness measuring instrument (TM005) manufactured by Canon was used to irradiate the TiN layer and its oxide film with light of a predetermined wavelength, and the reflection intensity was measured. The results shown in are obtained. The reflection intensity of the Si substrate 1 is also measured and shown. In the case of annealing at a temperature of 400 ° C. and in an atmosphere containing 20% of oxygen gas, the reflection intensity ratio of “TiN oxide film / TiN” for each incident wavelength is calculated from the obtained results. Become.
【００１７】[0017]
【表２】 [Table 2]
【００１８】また、温度３５０℃、酸素ガス２０％含有
の雰囲気でのアニール処理の場合には、入射波長ごとの
「ＴｉＮ酸化膜／ＴｉＮ」の反射強度割合を同様に求め
ると、表３となる。Further, in the case of annealing treatment at a temperature of 350 ° C. in an atmosphere containing 20% of oxygen gas, the reflection intensity ratio of “TiN oxide film / TiN” for each incident wavelength is similarly obtained, as shown in Table 3. ..
【００１９】[0019]
【表３】 [Table 3]
【００２０】コンタクト抵抗について 所定の多層配線を形成した半導体装置におけるコンタク
ト抵抗を測定し、さらに、コンタクト抵抗のアニール温
度依存性を調べるために、該半導体装置を５００℃×
３０分または４５０℃×３０分の加熱処理を施してコ
ンタクト抵抗を測定した。得られた結果を図３に示す。 Regarding contact resistance: In order to measure the contact resistance of a semiconductor device in which a predetermined multilayer wiring is formed and to examine the annealing temperature dependence of the contact resistance, the semiconductor device is tested at 500 ° C. ×
The contact resistance was measured by performing heat treatment for 30 minutes or 450 ° C. × 30 minutes. The obtained results are shown in FIG.
【００２１】コンタクト抵抗はアニール時に酸素ガスを
添加すると、抵抗は高くなる（アニール温度４００℃で
の比較で）。さらに、アニール温度が高くなるほど、か
つ熱処理温度が高いほど、抵抗も上昇する。この点か
ら、ＴｉＮの酸化膜の厚さには制限がある。接合リーク（Junction Leak)について 所定の多層配線を形成した半導体装置における接合リー
ク不良率のアニール温度依存性を調べるために、該半導
体装置を５００℃×３０分の加熱処理を２回または３
回繰り返した。得られた結果を図４に示す。The contact resistance increases when oxygen gas is added during annealing (comparison at an annealing temperature of 400 ° C.). Furthermore, the higher the annealing temperature and the higher the heat treatment temperature, the higher the resistance. From this point, the thickness of the TiN oxide film is limited. Regarding Junction Leak In order to examine the annealing temperature dependency of the junction leak defect rate in a semiconductor device in which a predetermined multilayer wiring is formed, the semiconductor device is subjected to heat treatment at 500 ° C. for 30 minutes twice or three times.
Repeated times. The obtained results are shown in FIG.
【００２２】アニール温度が高いほど、不良率は低くな
り、バリア性が高められている。配線のシート抵抗について 形成した多層配線自身のシート抵抗のアニール温度依存
性を、４５０℃×１５０分または４５０℃×３３０
分の加熱処理を施してシート抵抗の上昇率として求め
た。得られた結果を図５に示す。The higher the annealing temperature, the lower the defect rate and the higher the barrier property. Regarding the sheet resistance of the wiring, the annealing temperature dependence of the sheet resistance of the formed multilayer wiring is 450 ° C. × 150 minutes or 450 ° C. × 330.
After heat treatment for a minute, the increase rate of the sheet resistance was obtained. The obtained results are shown in FIG.
【００２３】アニール時の酸素添加でＴｉＮの酸化膜が
あると、幾分か上昇率が抑えられ、また、アニール温度
の高いほうが上昇率が低い。実験２ Ｓｉ基板を熱酸化してＳｉＯ2 層（厚さ１００nm）を形
成し、その上に上述した実験１と同様にスパッタリング
でＴｉ層およびＴｉＮ層を連続的に積層形成する。そし
て、その後のアニール処理をアニール温度を４５０℃一
定にして次のような条件にて行う。If there is a TiN oxide film due to the addition of oxygen during annealing, the rate of increase is somewhat suppressed, and the higher the annealing temperature, the lower the rate of increase. Experiment 2 A Si substrate is thermally oxidized to form a SiO 2 layer (thickness: 100 nm), and a Ti layer and a TiN layer are successively laminated thereon by sputtering as in Experiment 1 described above. Then, the subsequent annealing process is performed under the following conditions with the annealing temperature kept constant at 450 ° C.
【００２４】（１）アニール雰囲気を窒素のみとして、
３０リットル／分のＮ2 を流し、３０分アニールを１
回あるいは３回行う。 （２）アニール雰囲気に酸素ガスを添加し、その添加量
（Ｎ2 ３０リットル／分に加える量）を0.３５リット
ル／分、1.０リットル／分および2.０リットル／分
として、アニール時間３０分とする。(1) The annealing atmosphere is nitrogen only,
Flow 30 liters / min N 2 and anneal for 30 minutes 1
Do one or three times. (2) Annealing is performed by adding oxygen gas to the annealing atmosphere and adjusting the addition amount (the amount added to 30 liters / minute of N 2 ) to 0.35 liters / minute, 1.0 liters / minute, and 2.0 liters / minute. Time is 30 minutes.
【００２５】アニール処理の前および後で、実験１と同
じにキャノン製の薄膜厚測定器（ＴＭ００５）にてＴｉ
Ｎ層とその酸化膜に所定波長の光を当て、その反射強度
を測定して、図６に示す結果が得られた。なお、Ｓｉ基
板の反射強度も測定して示してある。得られた結果から
計算によって、入射波長ごとの「ＴｉＮ酸化膜／Ｔｉ
Ｎ」の反射強度割合を求めると、表４となる。Before and after the annealing treatment, Ti was measured by a thin film thickness measuring device (TM005) manufactured by Canon as in Experiment 1.
Light of a predetermined wavelength was applied to the N layer and its oxide film, and the reflection intensity thereof was measured, and the results shown in FIG. 6 were obtained. The reflection intensity of the Si substrate is also measured and shown. By calculation from the obtained results, "TiN oxide film / Ti
Table 4 shows the reflection intensity ratio of "N".
【００２６】[0026]
【表４】 [Table 4]
【００２７】[0027]
【発明の効果】以上説明したように、本発明によれば、
Ａｌ−Ｃｕ−ＴｉのようなＳｉを含有しない金属層に対
してバリア性が向上し、Ａｌ−ＳｉのようにＳｉを含有
する金属層でもバリア性が改善できる。従来ＴｉＮバリ
ア層は２００nm程度の厚さで形成されていたが、本発明
ではその半分の１００nm程度でも同等のバリア性を有す
る。また、エレクトロマイグレーションのＭＴＦが延び
るなどで多層配線の信頼性が向上する。さらに、本発明
の方法を用いると、安定した膜厚のＴｉＮの酸化膜形成
が可能となる。As described above, according to the present invention,
The barrier property is improved for a metal layer containing no Si such as Al-Cu-Ti, and the barrier property can be improved even for a metal layer containing Si such as Al-Si. Conventionally, the TiN barrier layer has been formed to have a thickness of about 200 nm, but in the present invention, even half of that, about 100 nm, has an equivalent barrier property. Further, the reliability of the multi-layer wiring is improved because the MTF of electromigration is extended. Furthermore, by using the method of the present invention, it is possible to form a TiN oxide film having a stable film thickness.
【図１】本発明に係る方法で製作された多層配線付き半
導体装置の部分断面図である。FIG. 1 is a partial cross-sectional view of a semiconductor device with a multilayer wiring manufactured by a method according to the present invention.
【図２】ＴｉＮ層のアニール処理前後の「ＴｉＮ酸化膜
／ＴｉＮ」の反射強度割合を示すグラフである。FIG. 2 is a graph showing a reflection intensity ratio of “TiN oxide film / TiN” before and after annealing of a TiN layer.
【図３】多層配線のコンタクト抵抗とアニール条件との
関連を示すグラフである。FIG. 3 is a graph showing the relationship between contact resistance of multilayer wiring and annealing conditions.
【図４】多層配線による接合リーク不良とアニール条件
との関連を示すグラフである。FIG. 4 is a graph showing a relationship between a junction leak defect due to multilayer wiring and an annealing condition.
【図５】多層配線のシート抵抗とアニール条件との関連
を示すグラフである。FIG. 5 is a graph showing the relationship between sheet resistance of multilayer wiring and annealing conditions.
【図６】ＴｉＮ層のアニール処理前後の「ＴｉＮ酸化膜
／ＴｉＮ」の反射強度割合を示すグラフである。FIG. 6 is a graph showing a reflection intensity ratio of “TiN oxide film / TiN” before and after annealing the TiN layer.
１…半導体基板 ３…Ｎ+ （Ｐ+ ）領域 ４…ＢＰＳＧ ５…Ｔｉ層 ６…ＴｉＮ層 ７…ＴｉＮの酸化膜 ６…金属層 ９…多層配線DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 3 ... N + (P + ) area | region 4 ... BPSG 5 ... Ti layer 6 ... TiN layer 7 ... TiN oxide film 6 ... Metal layer 9 ... Multilayer wiring
Claims (4)
よびその上の金属層を含んでなる多層構造配線を有する
半導体装置を製造する方法において、前記金属層（８）
の形成前に、前記ＴｉＮ層（６）を酸化して、該ＴｉＮ
層および該金属層とが反応せずかつ電気的な導通がとれ
る程度の薄い酸化膜（７）を形成することを特徴とする
半導体装置の製造方法。1. A method for manufacturing a semiconductor device having a multi-layered wiring including a barrier layer composed of a Ti layer and a TiN layer and a metal layer thereon, wherein the metal layer (8)
The TiN layer (6) is oxidized before the formation of
A method of manufacturing a semiconductor device, characterized in that a thin oxide film (7) which does not react with the layer and the metal layer and is electrically conductive is formed.
のＴｉＮの反射強度に対して0.６５〜0.９（測定入射波
長：４８０nmにて）とすることを特徴とする請求項１記
載の製造方法。2. The reflection intensity of the TiN oxide film is set to 0.65 to 0.9 (at a measurement incident wavelength: 480 nm) with respect to the reflection intensity of TiN before oxidation. The manufacturing method described.
Ａｌ−Ｓｉ、Ａｌ−Ｓｉ−Ｃｕ、Ａｌ−Ｃｕ−Ｔｉ、Ｃ
ｕまたはＡｕであることを特徴とする請求項１記載の製
造方法。3. The metal layer (8) comprises Al, Al--Cu,
Al-Si, Al-Si-Cu, Al-Cu-Ti, C
The manufacturing method according to claim 1, wherein the manufacturing method is u or Au.
リシリコン層またはシリサイド層と接触していることを
特徴とする請求項１記載の製造方法。4. The manufacturing method according to claim 1, wherein the Ti layer (5) is in contact with the Si substrate (1), a polysilicon layer or a silicide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23798791A JPH0574961A (en) | 1991-09-18 | 1991-09-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23798791A JPH0574961A (en) | 1991-09-18 | 1991-09-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574961A true JPH0574961A (en) | 1993-03-26 |
Family
ID=17023440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23798791A Pending JPH0574961A (en) | 1991-09-18 | 1991-09-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574961A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066891A (en) * | 1994-04-28 | 2000-05-23 | Nippondenso Co., Ltd | Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same |
| KR100267104B1 (en) * | 1997-08-25 | 2000-11-01 | 윤종용 | Contact Forming Method of Semiconductor Device Using Multilayer Diffusion Film |
| US6650017B1 (en) | 1999-08-20 | 2003-11-18 | Denso Corporation | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821339A (en) * | 1981-07-29 | 1983-02-08 | Toshiba Corp | Formation of semiconductor oxide film |
| JPH02249273A (en) * | 1989-03-23 | 1990-10-05 | Seiko Epson Corp | Semiconductor device |
| JPH04196122A (en) * | 1990-11-26 | 1992-07-15 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1991
- 1991-09-18 JP JP23798791A patent/JPH0574961A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821339A (en) * | 1981-07-29 | 1983-02-08 | Toshiba Corp | Formation of semiconductor oxide film |
| JPH02249273A (en) * | 1989-03-23 | 1990-10-05 | Seiko Epson Corp | Semiconductor device |
| JPH04196122A (en) * | 1990-11-26 | 1992-07-15 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066891A (en) * | 1994-04-28 | 2000-05-23 | Nippondenso Co., Ltd | Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same |
| US6348735B1 (en) | 1994-04-28 | 2002-02-19 | Nippondenso Co., Lt. | Electrode for semiconductor device and method for manufacturing same |
| KR100267104B1 (en) * | 1997-08-25 | 2000-11-01 | 윤종용 | Contact Forming Method of Semiconductor Device Using Multilayer Diffusion Film |
| US6650017B1 (en) | 1999-08-20 | 2003-11-18 | Denso Corporation | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime |
| US6908857B2 (en) | 1999-08-20 | 2005-06-21 | Denso Corporation | Method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4555540B2 (en) | Semiconductor device | |
| JP3128811B2 (en) | Method for manufacturing semiconductor device | |
| JP2811131B2 (en) | Wiring connection structure of semiconductor device and method of manufacturing the same | |
| US4998157A (en) | Ohmic contact to silicon substrate | |
| JP4647184B2 (en) | Manufacturing method of semiconductor device | |
| US6204167B1 (en) | Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer | |
| JPH03119727A (en) | Semiconductor device and its manufacture | |
| KR100319588B1 (en) | Method for forming interconnection structure | |
| JPH04259242A (en) | Manufacture of semiconductor device | |
| US20030020165A1 (en) | Semiconductor device, and method for manufacturing the same | |
| JPH0629468A (en) | Manufacture of thin-film resistance | |
| JPH0574961A (en) | Manufacture of semiconductor device | |
| JP3158598B2 (en) | Semiconductor device and method of manufacturing the same | |
| JPH07201859A (en) | Wiring formation method and semiconductor device | |
| JPH06314690A (en) | Semiconductor device and its manufacture | |
| JP3283965B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH02260535A (en) | Manufacture of semiconductor device | |
| JPH09298238A (en) | Wiring forming method | |
| JP3045850B2 (en) | Manufacturing method of Al-Si based alloy wiring | |
| JPH02186634A (en) | Manufacture of integrated circuit device | |
| JP3510943B2 (en) | Method for manufacturing semiconductor device | |
| JP3896492B2 (en) | Titanium oxynitride film evaluation method and wiring formation method | |
| JPH01124238A (en) | Wiring for semiconductor integrated circuit and its formation | |
| JPH06326105A (en) | Laminated interconnection structure of semiconductor device | |
| JPH05226479A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980120 |