JPH0574960A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0574960A JPH0574960A JP2800092A JP2800092A JPH0574960A JP H0574960 A JPH0574960 A JP H0574960A JP 2800092 A JP2800092 A JP 2800092A JP 2800092 A JP2800092 A JP 2800092A JP H0574960 A JPH0574960 A JP H0574960A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- wiring
- integer
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、更に詳しくは改良された層間絶縁膜の製造方法
に関する。この本発明でいう半導体装置とは、多層配線
構造を有するＩＣチップのみならず、このようなＩＣチ
ップを多数基板上に組込んだ構造の装置、例えばマルチ
チップモジュールをも言うものとする。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an improved interlayer insulating film. The semiconductor device in the present invention means not only an IC chip having a multilayer wiring structure but also a device having a structure in which a large number of such IC chips are incorporated on a substrate, for example, a multi-chip module.
【０００２】半導体装置は、近年その小型化・高速化に
伴い集積度の向上が非常に重要となってきている。この
ために、多層配線が必要である。多層配線をなすために
は層間絶縁膜が必要である。ところで、多層配線の間に
は層間絶縁膜を介した配線容量が避け難く、この配線容
量が大きいと信号伝播速度がそれだけ遅くなる。これ
は、マルチチップモジュールについても同様である。す
なわち、マルチチップモジュールの実装密度を上げよう
とした場合、チップ間の配線は下層の基板内において多
層配線となり、また配線間隔もせばまってきてしまう。
そうすると、配線間の容量による、信号伝送の遅延が問
題となってくる。従来の絶縁層の材料ではいずれも誘電
率が３以上と大きく、高速ＩＣのマルチチップモジュー
ルでは、この配線容量による遅延が深刻な問題となって
いる。2. Description of the Related Art In recent years, it has become very important to improve the degree of integration of semiconductor devices as they become smaller and faster. For this reason, multilayer wiring is necessary. An interlayer insulating film is required to form a multilayer wiring. By the way, it is difficult to avoid wiring capacitance between the multi-layered wiring via the interlayer insulating film, and if the wiring capacitance is large, the signal propagation speed becomes slower. The same applies to the multichip module. That is, when trying to increase the packaging density of the multi-chip module, the wiring between the chips becomes a multilayer wiring in the lower layer substrate, and the wiring interval becomes narrow.
Then, the delay of signal transmission due to the capacitance between wirings becomes a problem. All of the conventional insulating layer materials have a large dielectric constant of 3 or more, and the delay due to the wiring capacitance has become a serious problem in multichip modules of high-speed ICs.
【０００３】[0003]
【発明が解決しようとする課題】従来、半導体装置にお
ける層間絶縁膜として、ＳｉＯ2 膜、ＰＳＧ膜又はポリ
イミド膜等を使用していた。しかるに、従来技術に係る
前記の層間絶縁膜は、いずれも比誘電率が大きいもので
あった。ちなみに、ＳｉＯ2 の比誘電率は４．０、ＰＳ
Ｇの比誘電率も４．０であり、またポリイミドの比誘電
率は３．２である。Conventionally, a SiO 2 film, a PSG film, a polyimide film or the like has been used as an interlayer insulating film in a semiconductor device. However, each of the above-mentioned interlayer insulating films according to the prior art has a large relative dielectric constant. By the way, the relative permittivity of SiO 2 is 4.0, PS
The relative permittivity of G is 4.0, and the relative permittivity of polyimide is 3.2.
【０００４】従って、従来の製造方法による場合層間絶
縁膜の配線容量が大きくなるという欠点があった。この
ように配線容量が大きくなると前記のように半導体装置
の動作スピードが遅くなる。このような問題を解決する
手段として、フッ素樹脂膜を層間絶縁膜の一部に用いる
方法が公知となっている（特開平３−３４５５８）。す
なわち、この方法は比誘電率が小さい材料、すなわちフ
ッ素樹脂を用い、この樹脂の溶液をスピンコート法等に
より塗布・熱処理して層間絶縁膜を形成せんとするもの
である。Therefore, the conventional manufacturing method has a drawback that the wiring capacitance of the interlayer insulating film becomes large. When the wiring capacitance increases in this way, the operation speed of the semiconductor device slows down as described above. As a means for solving such a problem, a method of using a fluororesin film as a part of the interlayer insulating film has been known (Japanese Patent Laid-Open No. 34558/1993). That is, in this method, a material having a small relative dielectric constant, that is, a fluororesin is used, and a solution of this resin is applied and heat-treated by a spin coating method or the like to form an interlayer insulating film.
【０００５】しかし、この方法による場合次の２つの問
題点がある。密着性の問題と熱フローの問題である。す
なわち、第１の密着性に関しては、スピンコート法等で
塗布・熱処理して得られたフッ素樹脂膜とその下層との
密着性が良くないと言う点である。このような密着性不
良のため、次の加熱工程で形成されたフッ素樹脂膜が剥
離してしまうという事態が生じる。第２の熱フローの問
題とは、フッ素樹脂のガラス転移温度（Ｔｇ）は１００
℃前後であり、この１００℃を越えて熱処理（例えば２
００℃以上、例えば、素子ダメージを除くためのアニー
ル工程、又はアッセンブリー工程においてチップをパッ
ケージに組込む工程）すると樹脂が軟化し、流動性を持
つに至るということである。このように樹脂が流動して
しまうと、形成されたフッ素樹脂のパターン（例えばス
ルーホール等）の形状がくずれてしまう等という問題を
生じる。However, this method has the following two problems. There are problems of adhesion and heat flow. That is, regarding the first adhesiveness, the adhesiveness between the fluororesin film obtained by coating and heat treatment by the spin coating method or the like and the underlying layer is not good. Due to such poor adhesion, the fluororesin film formed in the next heating step may peel off. The second problem of heat flow is that the glass transition temperature (Tg) of the fluororesin is 100.
The temperature is around ℃, and heat treatment (eg 2
When the temperature is higher than or equal to 00 ° C., for example, an annealing process for removing element damage or a process of incorporating a chip into a package in an assembly process), the resin softens and becomes fluid. If the resin flows in this way, there arises a problem that the shape of the formed fluororesin pattern (for example, a through hole) is broken.
【０００６】本発明は、前記問題点を解決するためにな
されたものであり、絶縁膜の比誘電率を小さく保持しつ
ゝ密着性に秀れかつ熱フローの問題が生じない層間絶縁
膜を得ることを目的とする。The present invention has been made in order to solve the above-mentioned problems, and provides an interlayer insulating film which keeps the relative permittivity of the insulating film small and has excellent adhesion and no heat flow problem. The purpose is to get.
【０００７】[0007]
【課題を解決するための手段】本発明はかかる目的を達
成するためになされたものであり、本発明の半導体装置
の製造方法は基板上に第一の配線を形成し、次いで一般
式１： ＣX ＦY ＨZ （１） （式中、Ｘは１〜５の整数であり、Ｙは１〜１０の整数
であり、更にＺは０〜５の整数である）で表わされる化
合物ガス又は該化合物ガスおよび水素を反応ガスとして
用いてプラズマ重合法により該第一の配線上を含む基板
上に層間絶縁膜を形成し、次いで該層間絶縁膜上に第二
の配線を形成することを含んでなる。The present invention has been made to achieve the above object, and a method of manufacturing a semiconductor device according to the present invention comprises forming a first wiring on a substrate, and then forming the general formula 1: C X F Y H Z (1) (wherein, X is an integer of 1 to 5, Y is an integer of 1 to 10, and Z is an integer of 0 to 5) or Forming an interlayer insulating film on a substrate including the first wiring by a plasma polymerization method using the compound gas and hydrogen as a reaction gas, and then forming a second wiring on the interlayer insulating film. It consists of
【０００８】本発明は、更に前記の工程に加え、絶縁膜
を形成し、該絶縁膜を介して複数のチップを搭載し次い
で該チップを前記第一又は第二の配線と選択的に接続す
ることを特徴とする。この後者の発明は、マルチチップ
モジュールの多層配線部分の絶縁膜の形成に適用される
ものである。なお、前記絶縁膜の形成は前記式１で表わ
される化合物又は該化合物および水素を用いてプラズマ
重合法により好ましく行うことができる。In addition to the above steps, the present invention further comprises forming an insulating film, mounting a plurality of chips through the insulating film, and then selectively connecting the chips to the first or second wiring. It is characterized by The latter invention is applied to the formation of the insulating film in the multi-layer wiring portion of the multichip module. The insulating film can be preferably formed by a plasma polymerization method using the compound represented by the formula 1 or the compound and hydrogen.
【０００９】本発明方法においてプラズマ重合は、プラ
ズマ発生機構を有する反応容器（プラズマ重合装置）内
で、通常のプラズマＣＶＤ法を用いて好ましく行うこと
ができる。本発明方法で用いられる好ましい反応ガス
は、式１の化合物中、Ｘ，ＹおよびＺが小さい整数の化
合物であり、例えばＣＨＦ3 ，ＣＨ2 Ｆ2 ，Ｃ2 Ｆ4 ，
Ｃ2 Ｆ6 ，Ｃ3 Ｆ8 、又はＣ4 Ｆ8 である。In the method of the present invention, the plasma polymerization can be preferably carried out in a reaction vessel (plasma polymerization apparatus) having a plasma generating mechanism by using a usual plasma CVD method. A preferred reaction gas used in the method of the present invention is a compound of formula 1 in which X, Y and Z are small integers, such as CHF 3 , CH 2 F 2 , C 2 F 4 ,
C 2 F 6, C 3 F 8, or C 4 F 8.
【００１０】また、これらのガスとＨ2 との混合ガスも
好ましくは用いられ、例えばＣＦ4 およびＨ2 との混合
ガスも好ましく用いられる。A mixed gas of these gases and H 2 is also preferably used, for example, a mixed gas of CF 4 and H 2 is also preferably used.
【００１１】[0011]
【作用】上記本発明方法によって得られる重合膜は、炭
素とフッ素と（またはこれに少量の水素と）からなるポ
リマーからなり、比誘電率は２．０〜２．５と低比誘電
率である。また、この方法では、基板表面はプラズマの
荷電粒子の衝撃を受けるので、表面にダングリングボン
ドが生じる。このため、通常、この種のポリマーで問題
となる、密着性も充分良好なものが得られる。The polymer film obtained by the method of the present invention comprises a polymer composed of carbon, fluorine and (or a small amount of hydrogen) and has a relative dielectric constant of 2.0 to 2.5 and a low relative dielectric constant. is there. Further, in this method, the surface of the substrate is bombarded with charged particles of plasma, so that dangling bonds are generated on the surface. Therefore, it is possible to obtain a polymer having sufficiently good adhesion, which is usually a problem with this type of polymer.
【００１２】さらに、本発明方法で得られるポリマーは
高い架橋密度を持つ。このため従来例のフッ素樹脂にお
いてみられるような熱フローが起きない。また、絶縁耐
圧、耐熱性、耐薬品性の点でも充分半導体装置の製造工
程に耐えるものを得ることができる。以下、図面を参照
しつつ本発明を実施例により更に説明するが、本発明が
これらの実施例に限定されないことはもとよりである。Furthermore, the polymers obtained by the process according to the invention have a high crosslink density. For this reason, the heat flow as seen in the conventional fluororesin does not occur. In addition, it is possible to obtain a product that can sufficiently withstand the manufacturing process of a semiconductor device in terms of withstand voltage, heat resistance, and chemical resistance. Hereinafter, the present invention will be further described by way of examples with reference to the drawings, but it goes without saying that the present invention is not limited to these examples.
【００１３】[0013]
【実施例】例１ 図１は本発明の一実施例に係る半導体装置の製造方法の
説明図である。図１において、１は０．５Torrに減圧さ
れた反応容器Ｐである。この反応容器１内には平行平板
電極２が設けられている。この平行平板電極２の一方に
基板３を載置し、反応容器１内に反応ガス、例えばＣＨ
Ｆ3 を流入する。上記の平行平板電極２に高周波（Ｒ
Ｆ）電源４をもって高周波電圧を印加すると、電極間に
おいて放電が発生し、ＣＨＦ3 が電離されてプラズマが
発生し、反応ガス分子が活性状態に励起されて基板３上
に堆積し薄膜を形成する。EXAMPLE 1 FIG. 1 is an explanatory view of a method for manufacturing a semiconductor device according to an example of the present invention. In FIG. 1, 1 is a reaction vessel P whose pressure is reduced to 0.5 Torr. A parallel plate electrode 2 is provided in the reaction container 1. A substrate 3 is placed on one of the parallel plate electrodes 2 and a reaction gas such as CH 2 is placed in the reaction vessel 1.
Inflow F 3 . A high frequency (R
F) When a high frequency voltage is applied by the power source 4, a discharge is generated between the electrodes, CHF 3 is ionized and plasma is generated, and reactive gas molecules are excited to an active state and deposited on the substrate 3 to form a thin film. ..
【００１４】以下、更に図２に基づき説明する。シリコ
ン基板１１上にホトリソグラフィー技術を用い、材質と
してアルミニウムを用い第一の配線層１２（厚み；１μ
ｍ）をパターン形成する（図２（Ａ））。次いで図１で
示した反応容器１内に基板１１を載置し下記の条件でプ
ラズマ重合を行った： 使用反応ガス；Ｃ2 Ｆ4 流量；２５０SCCM 圧力；０．１torr 電力；３００Ｗ 以上の条件のもとでプラズマ重合を１０分間行い、約１
μｍの絶縁膜１３を堆積した（図２（Ｂ））。Further description will be given below with reference to FIG. A first wiring layer 12 (thickness: 1 μm is formed on the silicon substrate 11 by using a photolithography technique and aluminum as a material.
m) is patterned (FIG. 2A). Then, the substrate 11 was placed in the reaction vessel 1 shown in FIG. 1 and plasma polymerization was performed under the following conditions: Reaction gas used; C 2 F 4 flow rate; 250 SCCM pressure; 0.1 torr power; Plasma polymerization is carried out for 10 minutes under the condition of about 1
A μm insulating film 13 was deposited (FIG. 2B).
【００１５】次いで、公知のホトリソグラフィー法によ
り前記絶縁膜１３にスルーホール１４を形成する（図２
（Ｃ））。次いでアルミニウムを用い第二の配線層１５
（厚み；約１μｍ）を形成し（図２（Ｄ））、最後に第
二の配線層をパターニングした（図２（Ｅ））。上記の
プロセスで得られた絶縁膜をＸＰＳ（Ｘｒａｙ Ｐｈｏ
ｔｏｅｌｅｃｔｒｏｎ Ｓｐｅｃｔｒｏｓｃｏｐｙ）法
を用いて次の絶縁膜の組成構造を得た： Ｃ−Ｃ 構造；５％ Ｃ−ＣＦX 〃 ；２５％ ＣＦ 〃 ；３７％ ＣＦ2 〃 ；２１％ ＣＦ3 〃 ；１２％ この分析結果から得られた絶縁膜は高度に架橋した構造
を採っていることが判明する。Then, a through hole 14 is formed in the insulating film 13 by a known photolithography method (FIG. 2).
(C)). Then, using aluminum, the second wiring layer 15
(Thickness: about 1 μm) was formed (FIG. 2D), and finally the second wiring layer was patterned (FIG. 2E). The insulating film obtained by the above process is applied to XPS (Xray Pho
The following compositional structure of the insulating film was obtained by using a toelectron spectroscopy method: C—C structure; 5% C—CF X 〃; 25% CF 〃; 37% CF 2 〃; 21% CF 3 〃; 12% From this analysis result, it is found that the insulating film has a highly crosslinked structure.
【００１６】次に得られた絶縁膜の耐熱性をＴＧ−ＤＴ
Ａ（Ｔｈｅｒｍｏｇｒａｖｉｍｅｔｒｙ−Ｄｉｆｆｅｒ
ｅｎｔｉａｌ Ｔｈｅｒｍｏｌ Ａｎａｌｙｓｉｓ）法
を用いて測定した。この結果、膜の耐熱性は、空気中で
３７０℃であった。また、絶縁膜の誘電率（εr ）は
２．４であった。 例２ 例１と同様の手順をくり返した。但し、プラズマ重合の
条件は次の如くであった。Next, the heat resistance of the obtained insulating film was measured by TG-DT.
A (Thermogrammetry-Differ
The measurement was carried out by the method of "Thermal Thermol Analysis". As a result, the heat resistance of the film was 370 ° C. in air. The dielectric constant (ε r ) of the insulating film was 2.4. Example 2 The same procedure as in Example 1 was repeated. However, the conditions for plasma polymerization were as follows.
【００１７】 使用反応ガス；Ｃ4 Ｆ8 ガス流量；２５０SCCM 圧力；０．５torr 電力；３００Ｗ 以上の条件のもとで得られた絶縁膜について例１と同様
に耐熱性を測定した。その結果、空気中で３５０℃であ
った。また、比誘電率（εr ）は２．４であった。 例３ 例１と同様の手順をくり返した。但し、プラズマ重合の
条件は次の如くであった。Heat resistance was measured in the same manner as in Example 1 for the insulating film obtained under the conditions of the reaction gas used, C 4 F 8 gas flow rate, 250 SCCM pressure, 0.5 torr power, and 300 W or more. As a result, it was 350 ° C. in air. The relative dielectric constant (ε r ) was 2.4. Example 3 The same procedure as in Example 1 was repeated. However, the conditions for plasma polymerization were as follows.
【００１８】 使用反応ガス；ＣＨＦ3 ガス流量；２５０SCCM 圧力；０．５torr 電力；３００Ｗ ３分間で１μｍ薄膜を堆積した。A reaction gas used: CHF 3 gas flow rate; 250 SCCM pressure; 0.5 torr electric power; 300 W, a 1 μm thin film was deposited for 3 minutes.
【００１９】得られた絶縁膜の耐熱性は３５０℃であ
り、比誘電率は２．５であった。 例４ 例１と同様の手順をくり返した。但し、プラズマ重合条
件は次の如くであった。 使用反応ガス；ＣＦ4 とＨ2 の混合ガス（２対１の割
合） ガス流量；３００SCCM 圧力；０．１torr 電力；３００Ｗ 得られた絶縁膜の耐熱性は（３５０℃）、比誘電率は
（２．５）であった。 例５ この例はプラズマ重合を用いて層間絶縁膜を形成するマ
ルチチップモジュールの製造方法の一実施例である。The heat resistance of the obtained insulating film was 350 ° C. and the relative dielectric constant was 2.5. Example 4 The same procedure as in Example 1 was repeated. However, the plasma polymerization conditions were as follows. Reaction gas used; mixed gas of CF 4 and H 2 (ratio of 2 to 1) Gas flow rate; 300 SCCM pressure; 0.1 torr power; 300 W Heat resistance of the obtained insulating film (350 ° C.), relative permittivity ( 2.5). Example 5 This example is an example of a method for manufacturing a multichip module in which an interlayer insulating film is formed by using plasma polymerization.
【００２０】アルミナ基板２１上にスクリーン印刷を用
い、材質としてタングステンを用い第一の配線層２２
（厚み；１０μｍ）をパターン形成する（図３
（Ａ））。次いで図１で示した反応容器（カソードカッ
プルのプラズマチャンバー）１内に基板１１を載置し下
記の条件でプラズマ重合を行った： 使用反応ガス；Ｃ2 Ｆ4 流量；３００SCCM 圧力；０．１torr 電力；３００Ｗ 以上の条件のもとでプラズマ重合を２分間行い、約１０
μｍの第一の絶縁膜２３を堆積した（図３（Ｂ））。The first wiring layer 22 is formed by using screen printing on the alumina substrate 21 and using tungsten as a material.
(Thickness: 10 μm) is patterned (FIG. 3
(A)). Next, the substrate 11 was placed in the reaction vessel (cathode-coupled plasma chamber) 1 shown in FIG. 1 and plasma polymerization was carried out under the following conditions: Reaction gas used; C 2 F 4 flow rate; 300 SCCM pressure; 0.1 torr Electric power: Plasma polymerization is performed for 2 minutes under the condition of 300 W or more, and about 10
A first insulating film 23 having a thickness of μm was deposited (FIG. 3 (B)).
【００２１】次いで、公知のホトリソグラフィー法によ
り前記絶縁膜２３にスルホール２４を形成する（図３
（Ｃ））。次いでアルミニウムを用い前記と同じ条件で
第二の配線層２５（厚み；約３μｍ）を形成し（図３
（Ｄ））、最後に第二の配線層をパターニングした（図
３（Ｅ））。Next, through holes 24 are formed in the insulating film 23 by a known photolithography method (FIG. 3).
(C)). Then, using aluminum, the second wiring layer 25 (thickness: about 3 μm) is formed under the same conditions as described above (see FIG. 3).
(D)), and finally the second wiring layer was patterned (FIG. 3 (E)).
【００２２】次いで第一の絶縁膜形成と同一の条件下で
プラズマ重合を行い第二の絶縁膜１６（厚さ；約２μ
ｍ）を堆積した（図４（Ｆ））。上記のプロセスで得ら
れた絶縁膜の比誘電率を測定したところ、ε＝２．４で
あった。次いで、公知のホトリソグラフィー法により前
記第二の絶縁膜１６にスルホール２７を形成した（図４
（Ｇ））。Next, plasma polymerization is performed under the same conditions as the formation of the first insulating film, and the second insulating film 16 (thickness: about 2 μm) is formed.
m) was deposited (FIG. 4 (F)). When the relative dielectric constant of the insulating film obtained by the above process was measured, it was ε = 2.4. Then, a through hole 27 is formed in the second insulating film 16 by a known photolithography method (FIG. 4).
(G)).
【００２３】最後にこのようにして作成したプリント基
板に、通常のポンディング法を用い半導体チップＡを組
込み半導体装置を完成した（図４（Ｈ））。 例６ Ｃ4 Ｆ8 の反応ガスを用い例５と同様の条件下で手順を
くりかえし、それぞれ約２．０μｍの絶縁膜２３，２６
を得た。絶縁膜の誘電率はεr ＝２．４であった。 例７ ＣＨＦ3 の反応ガスを用い、例５と同様の条件下で手順
をくりかえし、それぞれ約０．８μｍの絶縁膜１３，１
６を得た。絶縁膜の誘電率はεr＝２．５であった。 例８ ＣＦ4 とＨ2 の混合ガスを用い、次のプラズマ重合条件
下で例５と同様のプロセスを行った。Finally, a semiconductor device was completed by incorporating the semiconductor chip A into the printed circuit board produced in this way by using a normal bonding method (FIG. 4 (H)). Example 6 The procedure was repeated using the reaction gas of C 4 F 8 under the same conditions as in Example 5, and the insulating films 23 and 26 each having a thickness of about 2.0 μm were formed.
Got The dielectric constant of the insulating film was ε r = 2.4. Example 7 The reaction gas of CHF 3 was used and the procedure was repeated under the same conditions as in Example 5 to obtain insulating films 13 and 1 each having a thickness of about 0.8 μm.
Got 6. The dielectric constant of the insulating film was ε r = 2.5. Example 8 The same process as in Example 5 was performed under the following plasma polymerization conditions using a mixed gas of CF 4 and H 2 .
【００２４】 ＣＦ4 ：３００SCCM Ｈ2 ：２００SCCM 圧力：０．４torr r.f.パワー：３００Ｗ ２分間の処理で、それぞれ約１．８μｍの絶縁膜２３，
２６を得た。絶縁膜の誘電率は、εr ＝２．５であっ
た。例５〜８はカソードカップルの例であるが、アノー
ドカップルあるいは誘導結合のプラズマ装置でも同様の
成膜を行うことができる。CF 4 : 300SCCM H 2 : 200SCCM Pressure: 0.4 torr rf Power: 300 W 2 minutes of processing, the insulating film 23 of about 1.8 μm,
26 was obtained. The dielectric constant of the insulating film was ε r = 2.5. Although Examples 5 to 8 are examples of the cathode couple, similar film formation can be performed with an anode couple or an inductively coupled plasma device.
【００２５】以上説明したように本発明は構成されるも
のであるから、得られる層間絶縁膜の比誘電率が低く、
かつち密な薄膜を得る効果を奏する。従って、配線遅延
を大幅に改善することが可能となる。また公知の方法の
如くフッ素樹脂をスピンコートして得られた膜のよう
に、熱フロー、密着性の問題がない。Since the present invention is configured as described above, the relative dielectric constant of the obtained interlayer insulating film is low,
The effect of obtaining a dense and thin film is obtained. Therefore, it is possible to significantly reduce the wiring delay. Further, unlike a film obtained by spin coating a fluororesin as in a known method, there is no problem of heat flow and adhesion.
【図１】本発明の一実施例に係る半導体装置の製造方法
の主要工程の説明図である。FIG. 1 is an explanatory diagram of main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例の工程図である。FIG. 2 is a process drawing of an example of the present invention.
【図３】本発明の他の実施例の工程図（一部）である。FIG. 3 is a process diagram (partial view) of another embodiment of the present invention.
【図４】本発明の他の実施例の残りの工程図である。FIG. 4 is a remaining process diagram of another embodiment of the present invention.
１１，２１…基板 １２，２２…第一の配線層 １３，２３…絶縁膜 １５，２５…第二の配線層 11, 21 ... Substrate 12, 22 ... First wiring layer 13, 23 ... Insulating film 15, 25 ... Second wiring layer
Claims (5)
般式１： ＣX ＦY ＨZ （１） （式中、Ｘは１〜５の整数であり、Ｙは１〜１０の整数
であり、更にＺは０〜５の整数である）で表わされる化
合物ガス又は該化合物ガスおよび水素を反応ガスとして
用いてプラズマ重合法により該第一の配線上を含む基板
上に層間絶縁膜を形成し、次いで該層間絶縁膜上に第二
の配線を形成することを含んでなる、半導体装置の製造
方法。1. A first wiring is formed on a substrate, and then a general formula 1: C X F Y H Z (1) (wherein, X is an integer of 1 to 5 and Y is 1 to 10). An integer, and Z is an integer of 0 to 5) or an interlayer insulating film on the substrate including on the first wiring by plasma polymerization using a compound gas or the compound gas and hydrogen as a reaction gas. And then forming a second wiring on the interlayer insulating film.
を形成し、該絶縁膜上に複数のチップを搭載し次いで該
チップを前記第一又は第二の配線と選択的に接続するこ
とを特徴とする請求項１の半導体装置の製造方法。2. An insulating film is formed on a substrate including on the second wiring, a plurality of chips are mounted on the insulating film, and then the chips are selectively connected to the first or second wiring. The method for manufacturing a semiconductor device according to claim 1, wherein
3 ，ＣＨ2 Ｆ2 ，Ｃ 2 Ｆ4 ，Ｃ2 Ｆ6 ，Ｃ3 Ｆ8 、又は
Ｃ4 Ｆ8 の一種である請求項１の半導体装置の製造方
法。3. A compound represented by the general formula 1 is CHF
3, CH2F2, C 2FFour, C2F6, C3F8, Or
CFourF8A method of manufacturing a semiconductor device according to claim 1, which is a kind of
Law.
ラズマ重合を行う請求項１の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein plasma polymerization is performed using a mixed gas of CF 4 and H 2 .
であり、更にＺは０〜５の整数である）で表わされる化
合物ガス又は該化合物ガスおよび水素を反応ガスとして
用いてプラズマ重合法により前記絶縁膜を形成する、請
求項２の半導体装置の製造方法。5. General formula 1: C X F Y H Z (1) (wherein, X is an integer of 1-5, Y is an integer of 1-10, and Z is an integer of 0-5. The method for manufacturing a semiconductor device according to claim 2, wherein the insulating film is formed by a plasma polymerization method using a compound gas represented by the formula (3) or the compound gas and hydrogen as a reaction gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2800092A JPH0574960A (en) | 1991-03-25 | 1992-02-14 | Manufacture of semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3-60068 | 1991-03-25 | ||
| JP6006891 | 1991-03-25 | ||
| JP2800092A JPH0574960A (en) | 1991-03-25 | 1992-02-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574960A true JPH0574960A (en) | 1993-03-26 |
Family
ID=26366014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2800092A Pending JPH0574960A (en) | 1991-03-25 | 1992-02-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574960A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0701283A2 (en) * | 1994-09-12 | 1996-03-13 | Nec Corporation | Semiconductor device with amorphous carbon layer and method of fabricating the same |
| JPH0883842A (en) * | 1994-09-12 | 1996-03-26 | Nec Corp | Semiconductor device |
| JPH08222557A (en) * | 1995-02-09 | 1996-08-30 | Nec Corp | Manufacture of fluorinated amorphous carbon film |
| JPH08264648A (en) * | 1995-03-23 | 1996-10-11 | Nec Corp | Semiconductor device |
| WO1997042356A1 (en) * | 1996-05-06 | 1997-11-13 | Massachusetts Institute Of Technology | Chemical vapor deposition of fluorocarbon polymer thin films |
| WO1999057760A1 (en) * | 1998-05-07 | 1999-11-11 | Tokyo Electron Limited | Semiconductor device |
| US5985750A (en) * | 1997-05-23 | 1999-11-16 | Nec Corporation | Manufacturing method of semiconductor device |
| DE102015017359B3 (en) | 2015-07-20 | 2023-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | WAFER LEVEL PACKAGE (WLP) AND PROCEDURE FOR FORMING ITS |
-
1992
- 1992-02-14 JP JP2800092A patent/JPH0574960A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0701283A2 (en) * | 1994-09-12 | 1996-03-13 | Nec Corporation | Semiconductor device with amorphous carbon layer and method of fabricating the same |
| JPH0883842A (en) * | 1994-09-12 | 1996-03-26 | Nec Corp | Semiconductor device |
| EP0701283A3 (en) * | 1994-09-12 | 1996-11-13 | Nec Corp | Semiconductor device with amorphous carbon layer and method of fabricating the same |
| US6033979A (en) * | 1994-09-12 | 2000-03-07 | Nec Corporation | Method of fabricating a semiconductor device with amorphous carbon layer |
| JPH08222557A (en) * | 1995-02-09 | 1996-08-30 | Nec Corp | Manufacture of fluorinated amorphous carbon film |
| JPH08264648A (en) * | 1995-03-23 | 1996-10-11 | Nec Corp | Semiconductor device |
| WO1997042356A1 (en) * | 1996-05-06 | 1997-11-13 | Massachusetts Institute Of Technology | Chemical vapor deposition of fluorocarbon polymer thin films |
| EP1795626A1 (en) * | 1996-05-06 | 2007-06-13 | Massachusetts Institute Of Technology | Chemical vapor deposition of fluorocarbon polymer thin films |
| US5985750A (en) * | 1997-05-23 | 1999-11-16 | Nec Corporation | Manufacturing method of semiconductor device |
| WO1999057760A1 (en) * | 1998-05-07 | 1999-11-11 | Tokyo Electron Limited | Semiconductor device |
| US6720659B1 (en) | 1998-05-07 | 2004-04-13 | Tokyo Electron Limited | Semiconductor device having an adhesion layer |
| DE102015017359B3 (en) | 2015-07-20 | 2023-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | WAFER LEVEL PACKAGE (WLP) AND PROCEDURE FOR FORMING ITS |
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