JPH0573420A - Computer having cache memory - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a cache memory with limited memory capacity without imposing a large burden on a hardware. CONSTITUTION:In a computer having a cache memory, at the time of development of a program, the program is recorded in a secondary storage device 7 by giving priority of a cache object. In an operation system, a table for registering and managing a program store state of a cache memory 6 is provided. At the time of executing a task, the program is read out of the secondary storage device 7, the read-out program module is stored by distributing the programs in the cache memory 6 or a main storage device 5 in accordance with the priority, based on information of the management table of the operation system, and the management table is updated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer having a cache memory, and more particularly to a computer having improved cache memory usage efficiency.

[0002]

2. Description of the Related Art Due to recent advances in computer technology,
CPU (central processing unit: processor) performance improvement,
In particular, there is a remarkable increase in signal processing speed. A small capacity high speed buffer is used to separate such a high speed CPU from a low speed main memory. This buffer is a cache memory, and in order to correspond to the fast clock of the CPU, the instruction that the CPU wants to access most frequently and the last used data are stored in advance in the high speed memory, and these can be accessed quickly. It is a memory. This is the dynamic R used in the main memory device.
This is adopted because the AM cannot keep up with the access to the CPU with a high clock speed, and if the necessary data is in the cache memory, the time-consuming access to the main storage device is not necessary and the system performance is improved. .. Such a cache memory includes a type built in the CPU and a type in which a high speed memory is added to the outside of the CPU.

In order to use the cache memory efficiently, the ratio of "cache hits" where the information to be accessed exists in the cache memory must be high. A hit is a case where access is completed only in the cache memory and access to the main storage device is not necessary. If the information to be accessed does not exist in the cache memory, it is a "cache miss". In the case of this cache miss, the information is accessed from the main storage device, so that it cannot be accessed at high speed.

FIG. 6 shows a block diagram of a conventional computer having a cache memory. The cache memory 1 is located between the CPU 2 and the main storage device 3, and stores a part of the contents of the main storage device 3. CPU2
When there is an access request from the cache memory 1, if the data is in the cache memory 1, the corresponding data is sent from the cache memory 1 to the CPU 2 (cache hit). If there is no data in the cache memory 1, the main memory device 3 To access the data and send the data to the CPU 2 and the cache memory 1. The cache controller 4 performs these access controls.

[0005]

Generally, when the cache memory is viewed from the software side, there is no distinction between the cache memory and the main storage device, and whether the currently executed program is executed in the main storage device or executed in the cache memory. I do not know if it is done. This is because the cache memory is controlled only by hardware,
During software development, it is possible to predict where the program will be executed at high speed. Therefore, if the software controls the cache memory to some extent, the cache can improve the processing speed.

When the cache memory is controlled by hardware as in the conventional system described above, there is an advantage that there is no software load, but the hardware of the cache controller for controlling the cache memory becomes complicated, and the cache is also complicated. The ratio of cache hits decreases as the memory capacity is increased. This phenomenon becomes more remarkable as the program becomes larger. That is, since the hardware side does not know which part of the program is frequently executed, all the modules of the program are cached with a uniform weight. Therefore, even if a frequently executed module is cached in the cache memory, it rarely occurs. Since the program modules that are not executed are cached, the programs that have been executed in the cache memory and are frequently executed will be evicted from the cache memory. Therefore, there is a problem that the data in the cache memory is frequently replaced, and the processing efficiency of the CPU is not improved so much. Particularly in a small-scale computer system, even if the cache memory is installed, the capacity of the cache memory cannot be increased due to the cost, so that the problem of data replacement as described above has a great influence.

The present invention has been made in view of the above problems of the conventional cache memory system, and provides a cache memory management system for a computer which improves the processing efficiency of the cache memory.

[0008]

In order to achieve the above object, the present invention presets a program to be executed at high speed at the time of program development, records it in a secondary storage device, and stores the program from the secondary storage device in a memory. At the time of loading, the operating system allocates and transfers the program module to the main storage device or the cache memory based on the management table in which the above-mentioned information set in advance is registered, and executes the program based on this.

[0009]

The hardware does not require a complicated cache memory controller, only the high-speed memory is arranged in the memory space of the CPU in the same manner as the main storage device, and the frequently executed program resides in the cache memory. It is expected that the processing speed of the CPU will be improved.

[0010]

1 is a block diagram of a cache memory management system which employs the present invention. In FIG. 1, the main memory 5 is composed of a dynamic memory, and a normal program module is loaded therein. Since it is composed of a dynamic memory, the access speed from the CPU 2 is limited. On the other hand, the cache memory 6, which is a high-speed memory, is composed of a high-speed static memory, and a program module to be executed at high speed is loaded into the memory blocks 0 to N by the operating system. Since it is composed of a high-speed memory, the CPU 2 can access it at the maximum speed.

At the time of program development, it is known to some extent which program modules are desired to be executed at high speed. Therefore, the priority order to be cached for each program module is determined, and this is used as additional information together with the program in a hard disk or the like. It is recorded in the stored secondary storage device. FIG. 2 schematically shows a situation of a program recorded in the secondary storage device 7, in which a plurality of program modules for one task are loaded in the main memory device 5 and a program module group 8 loaded in the cache memory 6. The program module group 9 is recorded separately.

The operating system contains a cache memory management tape 10 as shown in FIG. The management table 10 is set with an area for registering at least the information of the task number, the priority, and the block module number, and manages each block of the cache memory corresponding to blocks 0 to N of the cache memory 6, respectively. .. The task number is a number assigned to each task when a plurality of tasks are activated, the priority is information for determining the order to be loaded into the cache memory 6, and the module number is each information in one program. It is the number given to the module.

With respect to the program modules to be cached, which are recorded in the secondary storage device 7 together with the normal program modules in order of priority, when the operating system loads the programs from the secondary storage device into the memory and executes them, The program module is arranged in the main storage device 5 or the cache memory 6 based on the above-mentioned priority information stored in the secondary storage device 7. The processing flow of the operating system is shown in FIG.

The operating system judges whether or not the program module read from the secondary storage device 7 should be loaded into the cache memory, and if it is a cache target module, it is registered in the internal cache memory management table 10. Based on the information obtained, which area of the cache memory 6 is empty is searched for and the program module is loaded into the empty area. When there is no free area in the management table, the program module with the lower priority is expelled from the cache memory and a new program module is loaded. The information newly loaded in the cache memory is recorded in the management table 10.

If one task is read from the secondary storage device 7 and loaded into the memories 5 and 6 according to the instruction given to the program module, the CPU executes the program. When the execution of the program is completed, the operating system removes the unnecessary program module from the cache memory and updates the management table. FIG. 5 shows a conventional system (a) and the above embodiment (b).
In the figure comparing the relationship of the program execution time in, the execution time is 1 ms when one program module is executed in the cache, and the normal execution time is 3 m when the main storage device is used.
If s is required, a cache miss occurs as in the conventional system (a program module shown by hatching in both directions in the figure) requires 15 ms for program execution, but in this embodiment, a cache miss hardly occurs. It takes 8 ms.

[0016]

As described above, according to the present invention, it is possible to improve the use efficiency of the cache memory with a simple hardware configuration and a limited memory capacity, and to improve the processing speed of the CPU. Especially for small computers, the performance can be improved economically.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a model diagram showing a program storage state of a secondary storage device for explaining the embodiment.

FIG. 3 is a model diagram of a cache memory management table of an operating system for explaining the above embodiment.

FIG. 4 is a flowchart of an operating system for explaining the above embodiment.

FIG. 5 is a diagram comparing caches of the present embodiment and a conventional system.

FIG. 6 is a block diagram illustrating a conventional cache system.

[Explanation of symbols]

 2 CPU 5 main memory device 6 cache memory 7 secondary memory device 10 cache memory management table

Claims (1)

[Claims] 1. In a computer having a cache memory, a secondary storage device for recording a program with priorities to be cached, and a program being read from the secondary storage device at the time of executing a task, according to the recorded priority order. A cache comprising an operation system for distributing and storing a program to a cache memory or a main storage device, and a table provided in the operation system for registering the program storage status of the cache memory and managing the cache memory. A computer with memory.