JPH056951A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH056951A JPH056951A JP15706191A JP15706191A JPH056951A JP H056951 A JPH056951 A JP H056951A JP 15706191 A JP15706191 A JP 15706191A JP 15706191 A JP15706191 A JP 15706191A JP H056951 A JPH056951 A JP H056951A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead
- semiconductor device
- holding
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関し、特に、薄型パッケージ化したい場合に使
用される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and is particularly used for thin packaging.
【０００２】[0002]
【従来の技術】従来の樹脂封止薄型半導体装置の例とし
て、図５のごときフラットパッケージタイプのものを示
す。これは平面図で、図６は図５のＡ−Ａ線に沿う断面
図である。これは、Ｃｕ等からなるリードフレームから
形成されたもので、半導体チップ（半導体素子）１の載
置部２ａが、吊りピン部２ｂによりリードフレームに保
持されており、載置部２ａの周辺にリードフレームのリ
ード端子２ｃが配置されている。チップ１は接着剤（ペ
ースト）３により、載置部２ａ上に接合、固定され、ボ
ンディングワイヤ４でチップ１上のボンディングパッド
５とリード２ｃ間を配線している。樹脂（レジン）６に
より、リード２ｃの基端側（インナーリード部）とその
他の前記構成要素は、全部封止されており、外部汚染か
ら保護されている。2. Description of the Related Art As an example of a conventional resin-sealed thin semiconductor device, a flat package type device as shown in FIG. 5 is shown. This is a plan view and FIG. 6 is a sectional view taken along the line AA of FIG. This is formed from a lead frame made of Cu or the like, and the mounting portion 2a of the semiconductor chip (semiconductor element) 1 is held on the lead frame by the hanging pin portion 2b, and is placed around the mounting portion 2a. The lead terminal 2c of the lead frame is arranged. The chip 1 is bonded and fixed on the mounting portion 2a with an adhesive (paste) 3, and a bonding wire 4 connects between the bonding pad 5 on the chip 1 and the lead 2c. The resin (resin) 6 completely seals the base end side (inner lead portion) of the lead 2c and the other components described above, and is protected from external contamination.
【０００３】近年、メモリカード等の普及に伴い、半導
体装置の小型化、薄型化の要求が強く、パッケージング
技術による対応が必要となってきているなかにあって、
従来技術においては下記のような問題が生じている。す
なわち図６のごとく、載置部２ａ上にチップ１をペース
ト３にて接着、固定することにより、樹脂６で封止する
までチップ１を機械的に安定させる。この構造では、載
置部２ａとペースト３は絶対必要であり、薄型パッケー
ジ化において、これらの厚さが悪影響を及ぼしている。
また、薄型パッケージ化するために、樹脂６の厚さをで
きるだけ薄くするため、チップ１の上に存在する樹脂６
の厚さａと載置部２ａの下方に存在する樹脂６の厚さｂ
とは、互いに異なった寸法をとり、そのため例えば、加
熱試験のときなどに、樹脂６の膨脹度合が上方と下方で
互いに異なる。したがって応力のかかりかたが、樹脂６
の上面と下面で互いに異なることになり、樹脂６やチッ
プ１が割れる現象が生じ、信頼性上、極めて重要な問題
となっている。これは、従来の薄型半導体装置には、樹
脂６の表面とワイヤ４との距離ｃに決まりがあって、こ
のｃがある程度以上必要であるという条件があるため、
距離ａのほうがｂより大としなければ、上記条件を満た
せなくなってしまうためである。In recent years, along with the widespread use of memory cards and the like, there is a strong demand for miniaturization and thinning of semiconductor devices, and in response to the need for packaging technology,
The following problems have arisen in the prior art. That is, as shown in FIG. 6, by bonding and fixing the chip 1 on the mounting portion 2a with the paste 3, the chip 1 is mechanically stabilized until it is sealed with the resin 6. In this structure, the mounting portion 2a and the paste 3 are absolutely necessary, and their thickness has a bad influence in thin packaging.
Further, in order to make the resin 6 as thin as possible, in order to make the thickness of the resin 6 as thin as possible, the resin 6 existing on the chip 1 is
A and the thickness b of the resin 6 existing below the mounting portion 2a
Have different dimensions from each other, and therefore, the expansion degree of the resin 6 is different between the upper side and the lower side, for example, in a heating test. Therefore, the resin 6
Since the upper surface and the lower surface are different from each other, the phenomenon that the resin 6 and the chip 1 are cracked occurs, which is an extremely important problem in terms of reliability. This is because the conventional thin semiconductor device has a condition that the distance c between the surface of the resin 6 and the wire 4 is determined, and this c is required to be above a certain level.
This is because the above condition cannot be satisfied unless the distance a is larger than b.
【０００４】[0004]
【発明が解決しようとする課題】そこで本発明の目的
は、形状が極めて薄型で、しかも樹脂やチップに割れが
生じるなどの問題のない半導体装置およびその製造方法
を提供するものである。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device which is extremely thin in shape and has no problem that a resin or a chip is cracked and a manufacturing method thereof.
【０００５】[0005]
【課題を解決するための手段と作用】本発明は、半導体
チップと、このチップの近傍に配置されたリード端子
と、前記チップを挟んで保持するためのチップ保持体と
を具備したことを特徴とする半導体装置である。The present invention comprises a semiconductor chip, lead terminals arranged in the vicinity of the chip, and a chip holder for holding the chip. And a semiconductor device.
【０００６】すなわち本発明は、チップ保持体に、チッ
プの位置決めの役目、またワイヤボンディング時の支え
の役目、また樹脂モールド時の支えの役目などができる
ようにさせる。この様にすれば、チップ下のチップ載置
部２ａ、ペースト３を省略でき、したがって上記目的を
達成できる。That is, according to the present invention, the chip holder is made to have a function of positioning the chip, a function of supporting at the time of wire bonding, a function of supporting at the time of resin molding, and the like. By doing so, the chip mounting portion 2a and the paste 3 under the chip can be omitted, and thus the above object can be achieved.
【０００７】[0007]
【実施例】図１は本発明の一実施例を説明するための平
面図、図２は図１のＡ−Ａ線に沿う断面図、図３は図１
のＢ−Ｂ線に沿う断面図である。これら図において１１
は内部にＩＣを構成している半導体チップ、１２はチッ
プ周辺に配置されたリード端子、１３はチップ１１のボ
ンディングパッド１４とリード１３をつなぐボンディン
グワイヤ、１５はチップ１１を保持するためのチップ保
持リードである。この保持リード１５はチップ１１の位
置決めの役目、ワイヤ１３のボンディング時の支えの役
目、樹脂１６のモールド時の支えの役目をしている。保
持リード１１は、リード１２のリードフレームと一体物
であってもよいし、樹脂などの別体物であってもよく、
ただ樹脂１６との接着性が良くて、異物を侵入させない
ものがよい。樹脂１６は、チップ１１およびその周辺を
封止する。1 is a plan view for explaining one embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG. 1, and FIG. 3 is FIG.
It is sectional drawing which follows the BB line of FIG. 11 in these figures
Is a semiconductor chip that forms an IC inside, 12 is a lead terminal arranged around the chip, 13 is a bonding wire that connects the bonding pad 14 of the chip 11 and the lead 13, and 15 is a chip holding device for holding the chip 11. Be the lead. The holding leads 15 have a role of positioning the chip 11, a role of supporting the wire 13 during bonding, and a role of supporting the resin 16 during molding. The holding lead 11 may be integral with the lead frame of the lead 12, or may be a separate entity such as resin,
However, it is preferable that the adhesiveness with the resin 16 is good and foreign matter does not enter. The resin 16 seals the chip 11 and its periphery.
【０００８】上記構成を得るには、例えば図４のごとく
すればよい。まず、図４（ａ）のごとく、リードフレー
ムの各リード１２の先端側の中央位置付近にチップ１１
を置く。この時、チップ１１とリードフレームを含むリ
ード１２とは載置台などの上におくようにすると良い。
その後、四方からピン１７のようなもので、保持リード
１５を図示矢印方向にそれぞれ回動させ、図４（ｂ）の
ように四方からチップ１１を挟むようにして保持する。
チップ１１と保持リードの間には接着テープなどを挟ん
で両者を固着するようにすると良い。このようにしてチ
ップ１１を諸定位置に固定し、リード１２とチップ１１
のパッド間をボンディングワイヤにて所定配線する。そ
の後、ピン１７を除去してから、チップ１１、ボンディ
ングワイヤ１３、リード１２のインナーリード部などを
樹脂１６で封止し、外部に露出しているリード１２のア
ウターリード部などを機械的に加工し、所望の形状を得
る。このとき保持リード１５の外部露出部も同様に除去
し、樹脂内の保持リード１５は樹脂１６に埋め込んだま
まにしてよい。In order to obtain the above structure, for example, as shown in FIG. First, as shown in FIG. 4A, the chip 11 is placed near the center position on the tip side of each lead 12 of the lead frame.
Put. At this time, the chip 11 and the leads 12 including the lead frame are preferably placed on a mounting table or the like.
After that, the holding leads 15 are respectively rotated in the directions of the arrows in the figure by means of pins 17 from the four sides, and the chips 11 are held by sandwiching the chips 11 from the four sides as shown in FIG. 4B.
An adhesive tape or the like may be sandwiched between the chip 11 and the holding lead so as to fix the two. In this way, the chip 11 is fixed at various positions, and the lead 12 and the chip 11 are fixed.
The pads are connected to each other with a bonding wire. Then, after removing the pin 17, the chip 11, the bonding wire 13, the inner lead portion of the lead 12 and the like are sealed with a resin 16, and the outer lead portion of the lead 12 exposed to the outside is mechanically processed. And obtain the desired shape. At this time, the externally exposed portion of the holding lead 15 may be similarly removed, and the holding lead 15 in the resin may be left embedded in the resin 16.
【０００９】上記のようにすれば、図６の載置部２ａ、
ペースト３が除去できるため、非常に薄型の樹脂封止型
半導体装置が得られる。また、図６の載置部２ａ、ペー
スト３が不要となったため、図２、図３のごとくチップ
１１の上下の樹脂１６の厚みを同一にでき、樹脂１６、
チップ１１の割れなどを防止できる。With the above arrangement, the mounting portion 2a shown in FIG.
Since the paste 3 can be removed, a very thin resin-sealed semiconductor device can be obtained. Further, since the mounting portion 2a and the paste 3 in FIG. 6 are unnecessary, the thickness of the resin 16 above and below the chip 11 can be made the same as in FIGS.
It is possible to prevent cracking of the chip 11.
【００１０】なお、本発明は上記実施例などに限られる
ことなく、種々の応用が可能である。例えば、保持リー
ド１５は、４個で四方から保持したが、個数はこれのみ
に限られることはない。また、保持リードはリードフレ
ームと一体のリード端子または別体のリード端子を使用
したが、チップ１１の保持体はこれのみに限られない。The present invention is not limited to the above-mentioned embodiments and the like, and various applications are possible. For example, four holding leads 15 are held from all sides, but the number is not limited to this. Further, the holding lead uses a lead terminal integrated with the lead frame or a separate lead terminal, but the holding body of the chip 11 is not limited to this.
【００１１】[0011]
【発明の効果】以上説明したごとく本発明によれば、形
状が極めて薄型で、しかも樹脂やチップに割れが生じる
などの問題のない半導体装置およびその製造方法を提供
することができる。As described above, according to the present invention, it is possible to provide a semiconductor device having an extremely thin shape and free from problems such as cracks in resin or chips, and a method for manufacturing the same.
【図１】本発明の一実施例の平面図。FIG. 1 is a plan view of an embodiment of the present invention.
【図２】図１のＡ−Ａ線に沿う断面図。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】図１のＢ−Ｂ線に沿う断面図。3 is a sectional view taken along the line BB of FIG.
【図４】本発明の実施例の工程説明図。FIG. 4 is a process explanatory diagram of an example of the present invention.
【図５】従来装置の平面図。FIG. 5 is a plan view of a conventional device.
【図６】図５のＡ−Ａ線に沿う断面図。6 is a sectional view taken along the line AA of FIG.
１１…半導体チップ、１２…リード端子、１３…ボンデ
ィングワイヤ、１４…ボンディングパッド、１５…保持
リード（チップ保持体）、１６…樹脂、１７…ピン。11 ... Semiconductor chip, 12 ... Lead terminal, 13 ... Bonding wire, 14 ... Bonding pad, 15 ... Holding lead (chip holder), 16 ... Resin, 17 ... Pin.
Claims (11)
置されたリード端子と、前記チップを挟んで保持するた
めのチップ保持体とを具備したことを特徴とする半導体
装置。1. A semiconductor device comprising a semiconductor chip, lead terminals arranged in the vicinity of the chip, and a chip holder for sandwiching and holding the chip.
である請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the chip holder is a chip holding lead.
側面から挟んで保持するものである請求項１に記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the chip holder holds the chip by sandwiching it from a side surface thereof.
成されるリードフレームと一体物で構成される請求項２
に記載の半導体装置。4. The holding lead is integrally formed with a lead frame in which the lead terminal is formed.
The semiconductor device according to.
成されるリードフレームとは別体物で構成される請求項
２に記載の半導体装置。5. The semiconductor device according to claim 2, wherein the holding lead is formed separately from a lead frame in which the lead terminal is formed.
体チップを挟んで保持する工程と、前記チップとその近
傍のリード端子間のワイヤボンディングを行う工程と、
この工程後に前記チップ及びその近傍を樹脂封止する工
程とを具備したことを特徴とする半導体装置の製造方
法。6. A step of sandwiching and holding a semiconductor chip by a chip holder near a lead terminal, and a step of wire-bonding between the chip and a lead terminal in the vicinity thereof.
After this step, a step of sealing the chip and its vicinity with a resin is provided, and a method of manufacturing a semiconductor device.
である請求項６に記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the chip holding body is a chip holding lead.
ら挟んで保持するものである請求項６に記載の半導体装
置の製造方法。8. The method of manufacturing a semiconductor device according to claim 6, wherein the holding body holds the chip by sandwiching it from a side surface thereof.
成されるリードフレームと一体物で構成される請求項７
に記載の半導体装置の製造方法。9. The holding lead is integrally formed with a lead frame in which the lead terminal is formed.
A method of manufacturing a semiconductor device according to item 1.
構成されるリードフレームとは別体物で構成される請求
項７に記載の半導体装置の製造方法。10. The method of manufacturing a semiconductor device according to claim 7, wherein the holding lead is formed separately from a lead frame in which the lead terminal is formed.
着剤が介在される請求項７に記載の半導体装置の製造方
法。11. The method of manufacturing a semiconductor device according to claim 7, wherein an adhesive is interposed between the holding lead and the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15706191A JPH056951A (en) | 1991-06-27 | 1991-06-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15706191A JPH056951A (en) | 1991-06-27 | 1991-06-27 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH056951A true JPH056951A (en) | 1993-01-14 |
Family
ID=15641358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15706191A Pending JPH056951A (en) | 1991-06-27 | 1991-06-27 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056951A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09181225A (en) * | 1995-12-14 | 1997-07-11 | Samsung Electron Co Ltd | Semiconductor chip package and manufacture thereof |
-
1991
- 1991-06-27 JP JP15706191A patent/JPH056951A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09181225A (en) * | 1995-12-14 | 1997-07-11 | Samsung Electron Co Ltd | Semiconductor chip package and manufacture thereof |
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