JPH0567013A - Dma serial receiving operation end system - Google Patents
Dma serial receiving operation end systemInfo
- Publication number
- JPH0567013A JPH0567013A JP3254362A JP25436291A JPH0567013A JP H0567013 A JPH0567013 A JP H0567013A JP 3254362 A JP3254362 A JP 3254362A JP 25436291 A JP25436291 A JP 25436291A JP H0567013 A JPH0567013 A JP H0567013A
- Authority
- JP
- Japan
- Prior art keywords
- reception
- dma
- end code
- serial data
- lower controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
- Computer And Data Communications (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、調歩同期シリアルデー
タ通信機能を有する制御装置、例えばNC制御装置が上
位計算機間からDMA動作により調歩同期シリアルデー
タを受信する場合の終了方式に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a termination method in the case where a control device having an asynchronous synchronous serial data communication function, for example, an NC control device receives asynchronous synchronous serial data from a host computer by a DMA operation.
【0002】[0002]
【従来の技術】DMA動作により調歩同期シリアルデー
タを受信するとき、相手機器による受信データ量があら
かじめわかっていない場合は、何らかの手段で受信終了
を検出する必要がある。従来はタイマ割り込みによる定
期チェックにより、DMA受信カウンタの変化を調べ、
ある期間内に変化がなければ受信終了とみなす方式をと
っていた。2. Description of the Related Art When receiving asynchronous serial data by a DMA operation, if the amount of data received by a partner device is not known in advance, it is necessary to detect the end of reception by some means. Conventionally, the change of the DMA reception counter is checked by the periodic check by the timer interruption,
If there is no change within a certain period, it is considered that the reception has ended.
【0003】[0003]
【発明が解決しようとする課題】しかし前記従来例で
は、受信終了と検出されるまで必ず一定以上の判定時間
を要し、また相手機器の都合による一時転送中断も受信
終了と判断してしまうという問題があった。一方、特開
昭61−241858には終了を示す信号をデータ信号
線とは異なる信号線で送るものもあるが、信号線の増加
をまねくという欠点がある。そこで、本発明は受信デー
タそのものにより受信終了を検出し、DMA動作を直ち
に終了させることのできる方式を提供することを目的と
する。However, in the above-mentioned conventional example, it takes a certain amount of time for determination until the end of reception is detected, and the interruption of the temporary transfer due to the convenience of the partner device is also judged as the end of reception. There was a problem. On the other hand, in Japanese Patent Application Laid-Open No. 61-241858, there is also one that sends a signal indicating the end by a signal line different from the data signal line, but there is a drawback in that the number of signal lines increases. Therefore, an object of the present invention is to provide a method capable of detecting the end of reception by the received data itself and immediately ending the DMA operation.
【0004】[0004]
【課題を解決するための手段】以上の目的を達成するた
めに、本発明は次のような構成としている。すなわち、
任意の受信終了コード設定レジスタと、受信データレジ
スタとの比較回路で構成される受信終了コード検出器を
設け、データ一致により割り込み信号をNC制御装置に
出力し、DMA受信動作を強制停止させものである。In order to achieve the above object, the present invention has the following constitution. That is,
A reception end code detector composed of a comparison circuit of an arbitrary reception end code setting register and a reception data register is provided, and an interrupt signal is output to the NC control device when data matches, thereby forcibly stopping the DMA reception operation. is there.
【0005】[0005]
【作用】したがって、あらかじめ設定された受信終了コ
ードを検出することにより、直ちにDMA受信動作を終
了させることができるため、受信に対する高速応答が可
能になる。また、任意のコードを受信終了コードとして
設定できるため、例えば受信終了コードを8ビット(1
バイト)データとすれば、転送データの種類に対する制
限を1バイトのみに押さえることができる。Therefore, by detecting the preset reception end code, the DMA reception operation can be immediately terminated, so that a high-speed response to reception can be realized. Further, since an arbitrary code can be set as the reception end code, for example, the reception end code is 8 bits (1
With (byte) data, it is possible to limit the type of transfer data to only 1 byte.
【0006】[0006]
【実施例】図1は本発明の実施例を示すブロック図であ
る。図中の受信終了コード設定レジスタ1に設定された
任意の終了コードとシリアル受信器2に受信されたデー
タが比較器3にて比較され、両者が一致した場合にDM
A受信終了割り込み信号7がCPU4に出力される。C
PU4は直ちに割り込み処理を開始し、DMAコントロ
ーラ5の受信動作を終了させ、RAM6に書き込まれた
受信データの処理を行う。1 is a block diagram showing an embodiment of the present invention. The arbitrary end code set in the reception end code setting register 1 in the figure and the data received by the serial receiver 2 are compared by the comparator 3, and when both are matched, DM
The A reception end interrupt signal 7 is output to the CPU 4. C
The PU 4 immediately starts the interrupt process, ends the reception operation of the DMA controller 5, and processes the reception data written in the RAM 6.
【0007】[0007]
【発明の効果】以上述べたように、本発明によれば、終
了コード受信により直ちに受信データ処理を開始するこ
とができるため、従来行っていた受信終了判定のための
無駄時間を省けるため処理速度を向上させることができ
る。また、あらかじめ設定されている受信終了コードに
よる終了判定のため、その判定の確実さを再確認する必
要がなくなる。As described above, according to the present invention, the reception data processing can be started immediately by the reception of the end code, so that the dead time for the reception end judgment which has been conventionally performed can be saved and the processing speed can be reduced. Can be improved. Further, since the termination judgment is made by the preset reception termination code, it is not necessary to reconfirm the certainty of the judgment.
【図1】 本構成の実施例を示す図FIG. 1 is a diagram showing an example of this configuration.
1 受信終了コード設定レジスタ 2 シリアル受信器 3 比較器 4 CPU 5 DMAコントローラ 6 RMA 7 DMA受信終了割り込み信号 1 reception end code setting register 2 serial receiver 3 comparator 4 CPU 5 DMA controller 6 RMA 7 DMA reception end interrupt signal
Claims (1)
期シリアルデータ通信をDMA動作により行う場合にお
いて、下位制御装置側に予め設定した転送終了コードを
検出する検出器を設け、この検出器がシリアルデータ中
に前記転送終了コードを検出すると、下位制御装置に割
り込み動作を発生させDMA動作を強制終了させること
を特徴とするDMAシリアル受信動作終了方式。1. When a start-stop synchronous serial data communication is performed by a DMA operation between a high-order computer and a low-order control device, a detector for detecting a preset transfer end code is provided on the low-order control device side, and this detector is provided. A DMA serial reception operation ending method characterized in that, when the transfer end code is detected in serial data, an interrupt operation is generated in the lower controller to forcibly end the DMA operation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3254362A JPH0567013A (en) | 1991-09-05 | 1991-09-05 | Dma serial receiving operation end system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3254362A JPH0567013A (en) | 1991-09-05 | 1991-09-05 | Dma serial receiving operation end system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0567013A true JPH0567013A (en) | 1993-03-19 |
Family
ID=17263938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3254362A Pending JPH0567013A (en) | 1991-09-05 | 1991-09-05 | Dma serial receiving operation end system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0567013A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7069350B2 (en) | 2002-08-05 | 2006-06-27 | Seiko Epson Corporation | Data transfer control system, electronic instrument, and data transfer control method |
-
1991
- 1991-09-05 JP JP3254362A patent/JPH0567013A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7069350B2 (en) | 2002-08-05 | 2006-06-27 | Seiko Epson Corporation | Data transfer control system, electronic instrument, and data transfer control method |
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