JPH0564111A - Signal processing circuit for projection type video display device - Google Patents

Abstract

PURPOSE:To reduce the scale of an information storage circuit in the signal processing circuit by using the information storage circuit in common for a multi-layer expansion processing section and a sequential scanning conversion section. CONSTITUTION:A digital video signal subjected to synchronizing signal processing by a synchronizing signal processing section 4 is divided into two, the one is not subjected to arithmetic operation processing but subjected only to delay operation. The other is subjected to interpolation processing with respect to neighboring scanning lines at an interpolation processing section 6, resulting in forming a scanning line of sequential scanning interpolated from a scanning line of interlace-scanning. Then the two systems of the video signals are written in memories 8A-8E and 10A-10E, in which multi-layer expansion is implemented. Then double speed conversion is applied to the video signal whose frequency is decreased by the multi-layer expansion at double speed conversion sections 12A-12E. The scale of the information storage circuit in the signal processing circuit is reduced by using the information storage circuit in common for a multi-layer expansion processing section and a sequential scanning conversion section in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for driving a liquid crystal panel included in a liquid crystal projection type image display device.

[0002]

2. Description of the Related Art A signal processing circuit of a liquid crystal projection type image display device is required to operate at high speed because the frequency band of an image signal is wide. However, since the operating speed of the liquid crystal panel driving integrated circuit is slow, it is necessary to perform a multi-layer expansion process on the video signal to lower the frequency per layer.

In a CRT, an interlaced scanning display is performed except in a special case. In a display device using a liquid crystal, if the interlaced scanning is performed, every other scanning line becomes black or white, and the brightness is halved. The screen becomes white.
Therefore, a display device using liquid crystal often performs progressive scanning display.

[0004]

However, in the conventional liquid crystal projection type image display device, as shown in FIG. 4 or 5, the information holding circuit (that is, the memories 41, 42 or 52, 53) of the progressive scan conversion unit is used. , The information holding circuit of the multi-layer expansion processing unit (ie, the number of memories 44 equal to the number of layers).
˜48 or FIFO memory) are provided separately.

Further, in the progressive scan conversion unit, the scanning lines are stored in the information holding device, interpolation processing is performed, and then double speed conversion is performed. Therefore, for example, when considering high-definition, the operating frequency of the video signal is 74.25 MHz, which is doubled to 148.5 MHz after the progressive scan conversion, which causes a drawback that the circuit scale of the information holding device becomes large due to the limitation of the operating speed of the memory. ..

Therefore, in view of the above points, an object of the present invention is to reduce the scale of the information holding circuit in the signal processing circuit of the liquid crystal projection type image display device.

[0007]

In order to achieve the above object, the present invention is configured so that the multi-layer expansion processing section and the information holding circuit of the progressive scan conversion section are used in common.

[0008]

According to the present invention, the information holding circuit of the multi-layer expansion processing unit and the progressive scan conversion unit are also used, so that the scale of the information holding circuit in the signal processing circuit of the liquid crystal projection image display apparatus can be reduced.

[0009]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 2 is an A / D converter for inputting an analog video signal, 4 is a sync signal processing unit for applying a sync signal processing to an A / D converted output and outputting a digital video signal,
Reference numeral 6 is an interpolation processing unit for inputting an interlaced scanning signal (interlaced signal) to interpolate an interlaced portion, 8A to 8E and 10A to 10E are memories for interpolation processing and multilayer expansion, and 1
Reference numerals 2A to 12E are double speed conversion units for doubling the operating frequency (readout frequency) and outputting the image data.

In FIG. 1, the digital video signal is divided into two systems. That is, one does not perform arithmetic processing and only performs a delay operation. On the other hand, the interpolating unit 6 interpolates scanning lines in the vicinity to form sequential scanning lines interpolated from interlaced scanning lines. Thereafter, the video signals of the two systems are not converted to the double speed, and the memories 8A to 8E and 10A to
Write to 10E and perform multi-layer development.

Next, the video signal whose frequency has been lowered by the multi-layer expansion is subjected to double speed conversion, converted into an analog signal by the DA converter, and then output to a liquid crystal drive circuit (not shown).

FIG. 2 is a block diagram showing another embodiment of the present invention. In the figure, 21 is a line memory for inputting a digital video signal, 22 is an adder for line interpolation, 23 to 26 are D-type flip-flops (FF), A0
To F0, A1 to F1, A00 to F00, A11 to F11
(A to F indicate layers, 0:00 indicates read in the first half of 1H, and 1,11 indicates read in the second half of 1H) are FIFO (first-in / first-out) memories, 27 to 38, respectively. Is a D-type flip-flop (FF). The outputs of the D-type FFs 27 to 38 are input to the independent gamma correction units.

Next, the operation of FIG. 2 will be described with reference to the timing chart shown in FIG. 3 (A to F and 0 in FIG. 3,
1 corresponds to A to F and 0 (00) and 1 (11) in FIG. 2, and the frequency of the write clock is 1/2 of the frequency f of the operation clock of the line memory 21).

(1) Each FIFO memory resets the write address pointer to 0 at the rising edge of the write clock when the write reset pulse is "L".

(2) When each write enable of A to F, which is sequentially shifted for every H / 6, is "L", the corresponding FIFO memory (A0 to F0, A1 to F1) is set to the FIFO memory (at the rising edge of the write clock). A00-F00, A11-F1
1) is the fall of the write clock and each of the D-type FFs 23 to 26
The data on the input side of the line memory 21 and the output side of the adder 22 are written as 0 (1) or 00 (11 ) Attached F
Divided into IFO memory). At this time, the value of the write address pointer is incremented by 1.

(3) When the read reset pulse is "L", all the FIFO memories reset the read address pointer to 0 at the rising edge of the read clock.

(4) When the read enable indicated by 0 or 1 is "L", the value of the read address pointer of the corresponding FIFO memory at the rise of the read clock (the frequency of the read clock is 1/6 of the frequency of the write clock). The data is read from each address via the D-type FFs 27 to 38. At this time, the value of the read address pointer is incremented by 1. Here, the output of the corresponding FIFO memory when the read enable is "H" becomes high impedance,
It is separated from the data bus.

In this way, the data is written in each FIFO memory for the H / 6 period, and the FIFO corresponding to the next 1H period is written.
By simultaneously reading data from the memory for each H / 2 period, it is possible to perform 6-time time extension and non-interlace conversion at the same time.

Further, unlike the conventional example shown in FIG. 5, it is not necessary to raise the operating frequency to 2F, and the circuit complexity can be avoided.

[0021]

As described above, according to the present invention, the size of the information holding circuit in the signal processing circuit of the liquid crystal projection type image display device is increased by using the information holding circuit of the multi-layer expansion processing section and the progressive scan conversion section as well. Can be made smaller.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a timing diagram showing the operation of FIG.

FIG. 4 is an explanatory diagram of a conventional technique.

FIG. 5 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

2 A / D converter 4 Sync signal processor 6 Interpolator 8A-8E, 10A-10E Memory 12A-12E Double speed converter 21 Line memory 22 Adder 23-26, 27-28 D-type flip-flop A0-F0, A00-F00, A1-F1, A11-F
11 FIFO memory

Claims (2)

[Claims] 1. A signal processing circuit for driving a liquid crystal panel included in a liquid crystal projection image display device, comprising: a multi-layer expansion for multi-expanding a video signal in order to reduce an operating frequency of a drive circuit for driving the liquid crystal panel. A processing unit,
It is characterized in that it has a progressive scanning conversion unit for converting the interlaced scanning video signal into progressive scanning, and serves as both the information holding circuit in the multilayer expansion processing unit and the information holding circuit in the progressive scanning conversion unit. A signal processing circuit for a liquid crystal projection image display device. 2. The signal processing circuit of a liquid crystal projection type image display device according to claim 1, wherein the progressive scan conversion unit supplies data to the information holding circuit without performing double speed conversion.