JPH0564033A - Synchronization separating circuit - Google Patents

Abstract

PURPOSE:To execute correct synchronization separation irrespective of a noise by clamping a composite video signal at prescribed voltage, and cutting off the upper side part of this signal. CONSTITUTION:A component over an average level not relevant to the synchronizing separation in the composite video signal is cut off by a limiter 5, and the composite video signal is inputted to an operational amplifier 10. The operational amplifier 10 and resistors R1 to R3 constitute an inverting amplifier, and the composite video signal whose phase is inverted on the basis of the voltage inputted to a non-inverted input terminal is outputted from the output terminal of the operational amplifier 10. This composite video signal is inputted to the inverted input terminal of a comparator 12 and the inverted input terminal of the operational amplifier 11. The operational amplifier 11, diodes D2, D3 and the resistor R7 constitute a half-wave rectifier, and its output is inputted to the no-inverted input terminal of the operational amplifier 10. Then, the comparator 12 outputs LOW when the voltage of the inputted signal is higher than reference voltage, and outputs HIGH when it is lower, and thus, a synchronizing signal is separated.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit for separating a horizontal / vertical sync signal from a composite video signal in a television receiver or the like, and more particularly to a sync separation circuit suitable for integration.

[0003]

2. Description of the Related Art A conventional sync separation circuit in a television receiver or the like separates a horizontal / vertical sync signal from a composite video signal by using a power supply voltage of ± 12V. However, in order to integrate this synchronization separation circuit, it is necessary to set the power supply voltage to +5 V and the reference potential point. The configuration of this integrated sync separation circuit is shown in FIG.

In FIG. 5, the composite video signal is input terminal 1,
It is input to the inverting input terminal of the operational amplifier 10 via the capacitor C2 and the resistors R1 and R2. Here, the resistors R1 and R
A series circuit of a coil L and a capacitor C3 is connected between the connection point 2 and the reference potential point. The inverting input terminal of the operational amplifier 10 is also connected to the resistor R3. The other end of the resistor R3 is connected to the output terminal of the operational amplifier 10, the inverting input terminal of the comparator 12, and the resistor R4.

The other end of the resistor R4 is connected to the inverting input terminal of the operational amplifier 11, the cathode of the diode D2, one end of the capacitor C4 and one end of the resistor R7. The non-inverting input terminal of the operational amplifier 11 is connected to the connection point of the resistors R5 and R6. The resistors R5 and R6 are series circuits connected between +5 V of the power supply voltage and the reference potential point. On the other hand, the output terminal of the operational amplifier 11 is connected to the anode of the diode D2 and the cathode of the diode D3.
The anode of the diode D3 is connected to the other end of the capacitor C4, the other end of the resistor R7 and one end of the resistor R8. The other end of the resistor R8 is connected to the positive terminal of the capacitor C5 and the operational amplifier 1
0 non-inverting input terminal. The negative terminal of the capacitor C5 is connected to the reference potential point.

The non-inverting input terminal of the comparator 12 is connected to the connection point of the resistors R9 and R10. This resistor R9,
R10 is a series circuit connected between +5 V of the power supply voltage and the reference potential point. Then, the synchronization signal is output from the output terminal of the comparator 12 via the output terminal 2.

Next, the operation of the sync separation circuit shown in FIG. 5 will be described. The DC component of the composite synchronizing signal inputted from the input terminal 1 is removed by passing through the capacitor C2. Then, it is input to the operational amplifier 10 through a low pass filter (hereinafter referred to as LPF) composed of a coil L and a capacitor C3. Here, the operational amplifier 10 and the resistors R1, R2, R
3 constitutes an inverting amplifier. As a result, the output terminal of the operational amplifier 10 outputs a composite video signal whose phase is inverted with reference to the voltage input to the non-inverting input terminal of the operational amplifier 10. The gain of this inverting amplifier is 0 dB.

The composite video signal of which the phase is inverted is passed through the inverting input terminal of the comparator 12 and the resistor R4 to the operational amplifier 1
1 and the inverting input terminal of 1. Here operational amplifier 1
1 and the diodes D2 and D3 and the resistor R7 constitute a half-wave rectifier. Since the resistors R5 and R6 have the same resistance value, a voltage of 2.5 V is input to the non-inverting input terminal of the operational amplifier 11. The 2.5V is a clamp value of the sync head level.

By the way, the output voltage range of the operational amplifiers 10 and 11 and the comparator 12 is 1.5V to 3.5V. Due to these factors and the influence of the diodes D2, D3 and the resistor R7, the output voltage of the operational amplifier 11 is in the range of 2-3V. Here, the forward voltage of D2 and D3 of the diode is about 0.5V. Therefore, the voltage at the anode of the diode D3 is in the range of 2 to 2.5V. This voltage is input to the non-inverting input terminal of the operational amplifier 10 via the integrating circuit composed of the resistor R8 and the capacitor C5.

As described above, the output signal of the operational amplifier 10 is also input to the inverting input terminal of the comparator 12. In this signal, the leading level of the synchronizing signal is clamped to 2.5V. A voltage obtained by dividing 5V by resistors R9 and R10 is input to the non-inverting input terminal of the comparator 12. The comparator 12 outputs "LOW" when the voltage of the input signal is higher than the voltage of the non-inverting input terminal,
If the voltage of the input signal is lower than the voltage of the non-inverting input terminal, "HIGH" is output. This separates the sync signal.

Next, the relationship between the composite video signal input from the input terminal 1 and the separated sync signal will be described with reference to FIGS. 6 to 8. In FIG. 6, (A) shows a composite video signal per horizontal period when the amplitude is 1V, and (B) shows the separated sync signal at that time. As shown in (A), when the amplitude of the composite video signal is 1V, the amplitude of the sync signal component is about 0.3V. Therefore, the sync signal is detected by slicing with the value of Vt from the sync head level.

However, as shown in FIG. 7 (A), if the composite video signal has noise and the noise level is higher than Vt, accurate synchronization separation cannot be performed as shown in FIG. 7 (B). .. Therefore, as shown in FIG. 8, the amplitude of the composite video signal is set to 2V. However, in this case, the sync separation may not be performed correctly due to the characteristics of the sync separation circuit shown in FIG. The operation when a composite synchronizing signal having an amplitude of 2V is input will be described below.

As shown in FIG. 8, the elapsed time of the synchronizing signal in the composite video signal per horizontal period is 4.7 μsec, and the elapsed time of one horizontal scanning period is 63.5 μsec. The average level of the all-white level composite video signal is at 1.67V from the sync head level. This composite video signal is input from the input terminal 1 and the DC component is removed by the capacitor C2. The average level of the composite video signal is equal to the voltage value input to the non-inverting input terminal of the operational amplifier 10. Since this signal is inverted by the inverting amplifier including the operational amplifier 10 and the sync head level is clamped at 2.5 V, the voltage value input to the non-inverting input terminal of the operational amplifier 10 is expressed by the equation (1). It becomes the indicated voltage. 2.5− (1.67 ÷ 2) = 2.5−0.835 = 1.665 [V] (1) However, the gain of the inverting amplifier is 0 dB.

However, as described above, the range of the voltage input to the non-inverting input terminal of the operational amplifier 10 is 2 to 2.5V. Therefore, the sync head level of the composite video signal output from the operational amplifier 10 is a value different from 2.5V. Therefore, it is not possible to perform accurate synchronization separation in the comparator 12.

[0015]

In the sync separation circuit integrated as described above, the power supply voltage is +5 V and the reference potential point. When the amplitude of the composite video signal input to the sync separation circuit is set to 1 V, an accurate sync signal cannot be extracted due to the influence of noise. On the other hand, the amplitude of the composite video signal is set to 2
When V is set, the influence of noise can be eliminated, but the sync head level of the composite video signal cannot be clamped to a constant value, so that accurate sync separation cannot be performed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a sync separation circuit capable of performing accurate sync separation regardless of noise.

[Constitution of Invention]

[0018]

A first means according to the present invention is to input a composite video signal to limit means for cutting a component above the average level of the composite video signal and an output signal of the limit means. Clamping means for inputting and clamping the input signal to the first reference potential, and an input signal for the output signal of this clamping means and the second signal
By providing a comparison means for comparing with the reference potential of, accurate synchronization separation is performed regardless of noise.

A second means according to the present invention is a first clamping means which receives a composite video signal as an input and clamps a sync head level of the composite video signal to a first reference potential.
Of the output signal of the first clamp means, a limit means for cutting a component equal to or higher than the second reference potential, and an output signal of the limit means are used as inputs, and the input signal is used as a third signal.
The second clamp means for clamping the second reference means and the comparison means for receiving the output signal of the second clamp means and comparing the input signal with the fourth reference potential reduce noise. Accurate sync separation is achieved regardless.

[0020]

The first means cuts the component of the composite video signal having the average level or higher which is not related to the sync separation by the limiting means. The second means clamps the decoded video signal to the first reference potential, and cuts the component above the second reference potential. As a result, the amplitude of the sync signal component does not change, and the amplitude of the composite video signal is reduced. After the reduced composite video signal is clamped, a sync signal component is taken out to perform sync separation that is not affected by noise.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention.

In FIG. 1, the composite video signal is input to the limiter 5 via the input terminal 1. The structure of the limiter 5 will be described. First, the decoded video signal input to the limiter 5 is input to the positive terminal of the operational amplifier 3 via the capacitor C1. This positive terminal is connected to the connection point of resistors R11 and R12 connected in series between the power supply voltage 5V and the reference potential point. A resistor R1 is provided at the negative terminal of the operational amplifier 3.
3, R14 are connected. The other end of the resistor R13 is connected to the output terminal of the operational amplifier 3, the anode of the diode D1 and the capacitor C2. The other end of the resistor R14 is connected to the reference potential point via the resistors R15 and R16 connected in series, and is also connected to the negative terminal and the output terminal of the operational amplifier 4. The positive terminal of this operational amplifier 4 is
It is connected to the connection point of resistors R17 and R18 which are connected in series between the power supply voltage 5V and the reference potential point. The cathode of the diode D1 is connected to the connection point of the resistors R15 and R16.

The output signal of the limiter 5 is the capacitor C2.
And the resistors R1 and R2 to input to the inverting input terminal of the operational amplifier 10. A series circuit of a coil L and a capacitor C3 is connected between the connection point of the resistors R1 and R2 and the reference potential point. The inverting input terminal of the operational amplifier 10 is also connected to the resistor R3. The other end of the resistor R3 is connected to the output terminal of the operational amplifier 10, the inverting input terminal of the comparator 12, and the resistor R4.

The other end of the resistor R4 is connected to the inverting input terminal of the operational amplifier 11, the cathode of the diode D2, one end of the capacitor C4 and one end of the resistor R7. The non-inverting input terminal of the operational amplifier 11 is connected to the connection point of the resistors R5 and R6. The resistors R5 and R6 are series circuits connected between +5 V of the power supply voltage and the reference potential point. On the other hand, the output terminal of the operational amplifier 11 is connected to the anode of the diode D2 and the cathode of the diode D3.
The anode of the diode D3 is connected to the other end of the capacitor C4, the other end of the resistor R7 and one end of the resistor R8. The other end of the resistor R8 is connected to the positive terminal of the capacitor C5 and the operational amplifier 1
0 non-inverting input terminal. The negative terminal of the capacitor C5 is connected to the reference potential point.

The non-inverting input terminal of the comparator 12 is connected to the connection point of the resistors R9 and R10. This resistor R9,
R10 is a series circuit connected between +5 V of the power supply voltage and the reference potential point. Then, a synchronization signal is output from the output terminal of the operational amplifier 11 via the output terminal 2.

Next, the state of the composite video signal cut by the limiter 5 will be described with reference to FIG. A composite video signal as shown in FIG. 2 is input to the limiter 5. Here, the broken line indicates the average level of the composite video signal. The amplitude of the input composite video signal is 2V.

By the way, resistors R11 and R12 and resistors R17 and R18
The voltage at the connection point with and is 3.17V. This 3.17V is an addition of these two because the average level of the all-white level composite video signal is 1.67V from the sync head level and the operation lower limit voltage of the operational amplifiers 3 and 4 is 1.5V. It is the voltage. And the resistor R13 is the resistor R
Since the value is much smaller than that of 14, the gain of the signal in the operational amplifier 3 is almost 0 dB. Here, one end of the resistor R14 is connected to the output terminal of the operational amplifier 4. Since this operational amplifier 4 is a buffer, the limiter 5
The average level of the composite video signal input to is cranked to 3.17V.

On the other hand, the potential at the connection point of the resistors R15 and R16 is 3.17V rather than the forward voltage Vf (.apprxeq.
It is set lower by 0.5 V). Therefore 3.17V
The signal components of the above voltages, that is, the components above the average level of the composite video signal (hatched portion in the figure) are cut. As a result, the limiter 5 outputs a signal in which only the sync signal component is always normal.

Next, the operation of the sync separation circuit will be described. The signal output from the limiter 5 passes through the capacitor C2 to remove the DC component. And a low pass filter (hereinafter LPF) composed of coil L and capacitor C3.
Is described) and is input to the operational amplifier 10. Here, the operational amplifier 10 and the resistors R1, R2 and R3 form an inverting amplifier. As a result, the output terminal of the operational amplifier 10 outputs a composite video signal whose phase is inverted with reference to the voltage input to the non-inverting input terminal of the operational amplifier 10. The gain of this inverting amplifier is 0 dB.

The composite video signal whose phase is inverted is supplied to the operational amplifier 1 via the inverting input terminal of the comparator 12 and the resistor R4.
1 and the inverting input terminal of 1. Here operational amplifier 1
1 and the diodes D2 and D3 and the resistor R7 constitute a half-wave rectifier. Since the resistors R5 and R6 have the same resistance value, a voltage of 2.5 V is input to the non-inverting input terminal of the operational amplifier 11. The 2.5V is a clamp value of the sync head level.

Here, the output voltage range of the operational amplifiers 10 and 11 and the comparator 12 is 1.5V to 3.5V. Due to these factors and the influence of the diodes D2, D3 and the resistor R7, the output voltage of the operational amplifier 11 is in the range of 2 to 3V. Here, the forward voltage of D2 and D3 of the diode is about 0.5V. Therefore, the voltage at the anode of the diode D3 is in the range of 2 to 2.5V. This voltage is input to the non-inverting input terminal of the operational amplifier 10 via the integrating circuit composed of the resistor R8 and the capacitor C5.

As described above, the output signal of the operational amplifier 10 is also input to the inverting input terminal of the comparator 12. In this signal, the leading level of the synchronizing signal is clamped to 2.5V. Here, a voltage obtained by dividing 5V by resistors R9 and R10 is input to the non-inverting input terminal of the comparator 12. The comparator 12 outputs "LOW" when the voltage of the input signal is higher than the voltage of the non-inverting input terminal, and outputs "HIGH" when the voltage of the input signal is lower than the voltage of the non-inverting input terminal. .. This separates the sync signal.

Next, a second embodiment according to the present invention will be described with reference to FIGS. 3 and 4. In this embodiment, the limiter 5 of the first embodiment is a circuit in which the clamp circuit 6 and the limiter 7 are changed, and other configurations are the same as those of the first embodiment.

The composite video signal input from the input terminal 1 is supplied to the clamp circuit 6. The clamp circuit 6 is composed of a capacitor C1, a diode D0 and a voltage source 13. The supplied signal has its direct current component cut by passing through the capacitor C1 and is a voltage V1 which is the voltage V1 of the voltage source 13 minus the reverse voltage Vf of the diode D0.
It is clamped to 1-Vf and output.

The signal output from the clamp circuit 6 is supplied to the limiter 7. This limiter 7 is a diode D1
Of the supplied signal, the signal component higher than the voltage (V2 + Vf) obtained by adding the forward voltage of the diode D1 and the voltage V2 of the voltage source 14 is cut and output. .. The other structure is the same as that of the first embodiment.

As described above, the input composite video signal is clamped at a certain voltage and the upper portion of the clamped signal is cut. As a result, even if the amplitude of the input composite video signal is large, the sync signal portion is not damaged, so that accurate sync separation can be performed.

[0037]

As described above, the input composite video signal is clamped at a certain voltage and the upper portion of the clamped signal is cut. As a result, even if the amplitude of the input composite video signal is large, accurate sync separation can be performed without damaging the sync signal portion.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the first embodiment.

FIG. 3 is a configuration diagram showing a configuration of a second embodiment according to the present invention.

FIG. 4 is an explanatory diagram for explaining the operation of the second embodiment.

FIG. 5 is a configuration diagram showing a conventional configuration.

FIG. 6 is a first explanatory diagram illustrating a conventional operation.

FIG. 7 is a second explanatory diagram illustrating a conventional operation.

FIG. 8 is a third explanatory diagram illustrating a conventional operation.

[Explanation of symbols]

 3, 4, 10, 11 ... Operational amplifier 5, 7 ... Limiter 6 ... Clamp circuit 12 ... Comparator 13, 14 ... Voltage source

Claims (2)

[Claims] 1. A composite video signal as an input, limit means for cutting a component above the average level of the composite video signal, and an output signal of this limit means as an input, and the input signal as a first reference potential. A sync separation circuit comprising: clamp means for clamping; and comparator means for receiving an output signal of the clamp means and comparing the input signal with a second reference potential. 2. A first clamp means for receiving a composite video signal as an input and clamping a sync head level of the composite video signal to a first reference potential, and a second clamp output signal of the first clamp means. Of the second clamp means, a limit means for cutting a component above the reference potential of, a second clamp means for receiving the output signal of the limit means and clamping the input signal to the third reference potential, and A synchronization separation circuit comprising an output signal as an input and a comparison means for comparing the input signal with a fourth reference potential.