JPH0562867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital video processor device, and more particularly to a multi-move image effect device that creates a large number of reduced moving image divided images on one screen.

[Conventional technology]

Conventionally, this kind of multi-move image effect device is
Only one video reduced divided image of a preset specific size, for example 4, 9, or 16, is created.

[Problem that the invention seeks to solve]

In the case of the above-mentioned conventional multi-move image effect device, data is written in a preset size in a preset position in one frame memory. Therefore, there is a drawback that a moving picture reduced divided image can only be realized with one of the specific number of divisions, 4, 9, and 16.

[Means for solving problems]

The present invention includes a write address control circuit for writing image data obtained by digitally processing a television video signal into a preset position of one frame memory according to a specified reduction ratio; A television digital video processor device comprising a read address control circuit for reading image data, which receives address data from the write address control circuit and adjusts the read address based on a reduction ratio specified by the write address control circuit. The multi-boom control circuit includes a multi-boom control circuit that continuously issues read commands to the control circuit, and in response to the read command, the read address control circuit reads out the image data written in the one frame memory. It is a move image effect device.

〔Example〕

Next, the present invention will be explained with reference to examples.

Referring to Figure 1, television digital video processor equipment (hereinafter referred to as DVP)
is used to reduce a television video signal to a predetermined size using memory. D.V.P.
The television video signal input from the signal terminal 1 of the is equalized by the A/D converter circuit 2, and
The C separation circuit 3 separates the signal into a luminance signal and a carrier color signal. This encoded image data is subjected to filter processing in a filter circuit 4, and vertical interpolation processing is performed in a vertical interpolation circuit (V interpolation circuit) 5 according to a command from the write address circuit 13, and reduction is performed on the encoded image data. Digital processing is performed for this purpose. The color signal is further separated into an I signal and a Q signal by the decoder circuit 6, and this image data is transferred to a horizontal interpolation circuit (H interpolation circuit) by a command from the write address control circuit 13.
7, horizontal interpolation processing is performed.

As shown in FIG. 2, based on the size data and position data given from the external controller 16, the image data from the H interpolation circuit 7 is sent for one frame via the buffer memory 8 with the synchronization signal of the video signal as a reference. Preset location in memory 9
Written to P ₁ . On the other hand, a multi-move control circuit 14 (described later) receives data (address data, that is, horizontal data and vertical data) from the write address control circuit 13, and sends the data to the read address control circuit 15 based on size data given from the external controller 16. Issue read commands continuously. In response to this read command, the read address control circuit 15 issues a command, and the image data written in the one frame memory 9 is read out. The IQ filter circuit 10 corrects the I signal and Q signal of this image data to standard values. This corrected signal is combined with an IQ signal and a color signal by an encoder circuit 11, and is input to a D/A converter circuit 12, and an output terminal 17 outputs a video signal converted to an analog signal. The DVP is equipped with a lead clock regulator (RCK) 18, into which the vertical and horizontal synchronizing signals and subcarriers of the television video signal are input, and the clock signal, horizontal synchronizing signal, and vertical A synchronization signal is output. This clock signal and horizontal and vertical synchronization signals are supplied to the above-mentioned A/D converter circuit 2, Y/C separation circuit 3, filter circuit 4, V interpolation circuit 5, decoder circuit 6, H interpolation circuit 7, buffer memories 8 and 1. It is sent as a timing signal to the frame memory 9, IQ filter circuit 10, encoder circuit 11, D/A converter circuit 12, write address circuit 13, multi-move control circuit 14, and read address control circuit 15.

When obtaining a full-size image in DVP,
As shown in FIG. 6a, both write and read addresses are operated equally. For example, when reducing the size to 1/2, the advance of the write address is set to 1/2 of the read address, as shown in FIG. 6b. On the other hand, in the case of multi-move images, for example, to obtain an image divided into 16 parts on one screen,
As shown in FIG. 6c, the advance of the write address is set to 1/4, and the advance of the read address is set to 4 times. That is, the read address is repeated four times.

To control the read address, a read address counter (not shown) is cleared at a predetermined time to make the address counter zero. after that,
The address counter starts counting again.
Clearing the above read address counter
The pulses are provided by the multi-move control circuit described above.

Here, the multi-move control circuit will be explained in detail with reference also to FIG.

The multi-move control circuit 14 includes a tri-state buffer 30 to which horizontal data from the write address control circuit 13 is input, a tri-state buffer 31 to which vertical data is input, and a tri-state buffer 31 to which horizontal size data from the external controller 16 is input. A tri-state buffer 33 to which the state buffer 32 and vertical size data are input, a multiplier 29 to which the data of these tri-state buffers 30, 31, 32, and 33 are input, and a multiplier 2.
9, registers 27 and 28 connected to register 27, register 23 connected to register 27 through adder 25, register 24 connected to register 28 through adder 26, the value of horizontal counter 19 and the value of register 23. and a comparator 22 that compares the value of the vertical counter 20 and the value of the register 24.

As mentioned above, the size data given to the write address control circuit 13 (horizontal size data is Xn,
The vertical size data (Yn) is sent from the external controller 16 to the tri-state buffers 32 and 33 of the multi-move control circuit 14 for each field of the television video signal. On the other hand, horizontal data (for example, 768 pieces) and vertical data (for example, 242 pieces) are sent from the write address control circuit 13 to tristate buffers 30 and 31, respectively, as shown in FIG. The OE1 pulse generated from the synchronization signal from the RCK 18 is sent to the tri-state buffers 30 and 32 during vertical blanking, and the OE2 pulse is similarly sent to the tri-state buffers 31 and 33 (OE1 and OE2
The pulses are shown in Figure 4). Then, each data of the tristate buffers 30, 31, 32, and 33 is sent to the multiplier 29 within vertical blanking (V blanking) by the OE1 and OE2 pulses, respectively, as shown in FIG. , the horizontal data and the horizontal size data, and the vertical data and the vertical size data are multiplied, respectively, and as shown in FIG.
The horizontal multiplication result (horizontal multiplication data) is input to the register 27 by the clock from RCK18 (CKI clock), and the vertical multiplication result (vertical multiplication data) is input to the register 28 by the CK2 clock (CK1 and CK2 clock). (shown in Figure 4).
The data in registers 27 and 28 are input to adders 25 and 26, respectively, and are first added with zero.

Referring also to FIG. 5, which shows the case of reducing the image to 1/4, the LD1 pulse generated by the synchronization signal from the RCK 18 is sent to the register 23 within the horizontal blank (H blank) via the OR gate 23a. The output of the adder 25 is inputted to the register 23 by the LD1 pulse and outputted at the same time. On the other hand, the horizontal counter (H counter) 19 becomes zero with the H clear pulse generated from the horizontal synchronizing signal, and starts counting with the H start pulse. The output of the register 23 is input to the comparator 21, and when the count value of the H counter 19 matches the output of the register 23, the comparator 21 sends out an H multi-clear pulse, and this H multi-clear pulse triggers the OR gate 23a. and the output of the adder 25 is loaded into the register 23. Similarly, the comparator 21 compares the output of the register 23 with the count value of the H counter 19 and sends out an H multi-clear pulse. As described above, when the H clear pulse is input to the H counter 19, the horizontal counter 19 becomes zero. Thereafter, the output of the adder 25 is inputted to the comparator 21 via the register 23 by the LD1 pulse again, and the H counter 19 is inputted by the H start pulse.
starts counting and sends out the H multi-clear pulse as described above.

Similarly, the output of the adder 25 is the OR gate 24a
It is simultaneously input to the register 24 and output by the LD2 pulse input to the register 24 via the LD2 pulse. When the count value of the vertical counter (V counter) 20 and the output of the register 24 match, a V multi-clear pulse is sent to the comparator 22.

These H multi-clear pulses and V multi-clear pulses are sent to the read address control circuit 15 shown in FIG.
controls the 1-frame memory to read the contents of the 1-frame memory upon receiving the H multi-clear pulse and the V multi-clear pulse.

In this way, the multi-move control circuit 14 receives the size data given to the write address control circuit 13 for each field of the television video signal, and as described above, when the horizontal size data is reduced by 1/4, that is, 0.25, , since the horizontal data is 768, the multiplier 29 performs an operation of 768×0.25, and the horizontal multiplication data becomes 192. This horizontal multiplication data 192 is multiplied by an integer to 384, 576, 768 by an adder, and the comparator 21
More H multi-clear pulses are generated. This pulse is input to the read address control circuit 15. Therefore, the read address is repeated four times as shown in Figure 6c, and a reduced moving image that is divided into 16 parts per screen and reduced to 1/4 is obtained (vertical data is also processed in the same way). . Note that, as shown in FIG. 7, it is also possible to obtain a reduced moving image that is divided into 36 parts on one screen and reduced to 1/6.

〔Effect of the invention〕

As explained above, in the present invention, upon receiving address data from the write address control circuit, a clear pulse (read command) is continuously generated to the read address control circuit based on the reduction ratio specified by the write address control circuit. Since the read address control circuit receives this clear pulse and reads out the image stored in the memory, a multi-move image of any size can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a digital video processor device according to the present invention, FIG. 2 is a diagram showing an image written at a preset position in one frame memory at a specified reduction ratio, and FIG. Fig. 3 is a block diagram showing an embodiment of the multi-move control circuit used in the present invention, Fig. 4 is a timing diagram for explaining multiplication of horizontal and vertical data in one field, and Fig. 5 is an H multi-move clear pulse. 6A to 6C are diagrams showing changes in write addresses and read addresses, and FIG. 7 is a diagram showing a multi-move image divided into 36. 1...Input terminal, 2...A/D converter, 3...
Y/C separation circuit, 4...Filter circuit, 5...Vertical interpolation circuit, 6...Decoder circuit, 7...Horizontal interpolation circuit, 8...Buffer memory, 9...1 frame memory, 10...IQ filter circuit, 11...Encoder circuit , 12...D/A converter, 13...Write address control circuit, 14...Multi-move control circuit,
15... Read address control circuit, 16... External controller, 17... Output terminal, 18... Read clock regulator, 19... Horizontal counter (H counter), 20... Vertical counter (V counter), 21, 22... Comparator ,23,24,27,
28... Register, 25, 26... Adder, 29... Multiplier, 30, 31, 32, 33... Tri-state buffer.

Claims (1)

[Claims] 1. A write address control circuit that writes image data obtained by digitally processing a television video signal to a preset position in a 1-frame memory according to a specified reduction ratio, and image data written in the 1-frame memory. A television digital video processor device comprising: a read address control circuit for reading out a read address control circuit; The multi-move image is characterized by comprising a multi-move control circuit that continuously issues read commands, and in response to the read command, the read address control circuit reads out the image data written in the one-frame memory. effect device.