JPH0554002A - Inter-cpu interruption controller - Google Patents

Abstract

PURPOSE:To provide an inter-CPU interruption controller which shortens the processing time of inter-CPU interruption and simplifies the interruption handling and is capable of interruption in plural levels among plural CPUs. CONSTITUTION:The same number of interruption registers 33, which have interruption storage parts 35 having interruption flags of CPUs for the same interruption levels of interruption destination CPUs and interruption storage information generating parts 34 generating storage information based on information in interruption storage parts 35 and write information, as interruption levels are provided correspondingly to individual interruption levels. An interruption request part 36 is provided which requests interruption to CPUs by levels based on information in interruption storage parts 35 of interruption registers 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a numerical control device for a laser beam machine, etc., and uses a plurality of CPUs in the equipment, and uses an interrupt to execute information exchange between the CPUs. And an interrupt control device between a plurality of CPUs.

[0002]

2. Description of the Related Art In recent years, in devices using microcomputers, an increase in the amount of information in the devices and a high processing speed are demanded, and a plurality of CPUs are used to control each CP.
There is an increasing number of distributed systems in which the U is individually assigned a function having a characteristic and information is exchanged between the CPUs to configure the entire system.

In a device using such a distributed system microcomputer, a system shown in FIG. 1 is known as a system for exchanging information between CPUs in a large amount at high speed.

In the conventional example shown in FIG. 1, an interrupt control device provided for each CPU 5 receives an interrupt generation unit 9 for generating an interrupt and an interrupt reception for receiving an interrupt generated by another CPU 5. And a section 10. As shown in FIG. 2, the interrupt receiving unit 10 includes an interrupt receiving register 15 including a large number of interrupt flags 16 so as to be able to respond to the interrupt generation of all the CPUs 5 of the other party.
And an interrupt request unit 17 which issues an interrupt request to its own CPU 5. Also, the interrupt generation unit 9
Has a large number of interrupt generation units for each CPU so as to be able to handle the interrupt reception of all the CPUs 5 of the other party. As shown in FIG. 2, the interrupt generation units for each CPU and the interrupt flags 16 corresponding thereto are provided. And are in a one-to-one correspondence, and are connected by the interrupt request line 13.

However, according to this conventional example, when the number of CPUs 5 for performing interrupt communication between the CPUs 5 increases, the number of interrupt request lines 13 increases geometrically.

That is, assuming that the number of CPUs 5 is M, the number W of interrupt request lines 13 is represented by the equation (1).

W = M × (M 1) (1) FIG. 3A shows the case where the number of CPUs 5 is four. In this case, the interrupt request line 13 Will be 12. Further, FIG. 3B shows a case where the number of CPUs 5 is 5, but in this case, the number of interrupt request lines 13 is 20.
It will be a book.

In the above case, the interrupt level was not taken into consideration, but in many cases the interrupt level must actually be taken into consideration. If there are N levels of interrupt levels, the interrupt request line The number W of 13 is expressed as in equation (2).

W = N × M × (M 1) (2) Therefore, for example, the number of CPUs 5 is 4 and the interrupt level is 7
In the stage, the number of interrupt request lines 13 becomes 84. As described above, in the conventional example described above, the CPU 5
The number of interrupt request lines 13 increases extremely as the number of interrupts increases, and in particular, when the number of interrupt levels increases in addition to the increase in the CPU 5, there is a problem that it is practically impossible to deal with this. There is.

As a conventional example that solves such a problem, there are conventional examples shown in FIGS.

In this conventional example, the interrupting CPU obtains the exclusive right of the local bus of the interrupt destination CPU and stores the interrupt information to perform the interrupt between the CPUs.

As shown in FIG. 4, corresponding to each CPU 21, a bus control unit 18, a buffer 19, a memory 22, an interrupt control unit 23, an I / O 24, and an inter-CPU interrupt control device 2 are provided.
5 are provided. Inter-CPU interrupt controller 25
Is an interrupt register 2 having an interrupt storage unit 30 having an individual interrupt flag configuration for each CPU, as shown in FIG.
9 and an interrupt request unit 31. The internal structure of the interrupt register 29 is shown in Table 1. Table 2 is a state transition table of the interrupt flag in the interrupt register 29. FIG. 6 shows the interrupt register 29 and the interrupt request unit 3.
1 shows an example of a circuit configuration of 1.

[0013]

[Table 1]

[0014]

[Table 2]

As shown in FIGS. 4 and 5, each CPU 21
There is provided a common memory 20 for storing management information for managing the individual access to the interrupt register 29 which is locally present. The common memory 20 has an interrupt register access control storage unit 32. The access control storage unit 32, as shown in Table 3, has a semaphore flag corresponding to each interrupt register 29.

[0016]

[Table 3]

Next, the interrupt operation between the CPUs of the above conventional example will be described. Since the interrupt register 29 of the inter-CPU interrupt control device 25 attached to each CPU 21 has an interrupt flag corresponding to all the other CPUs 21, each C
Access from the PU 21 may be mixed. For this reason, the interrupt generation processing by the other CPU 21 and its own C
It is necessary to guarantee a series of read and write access to the interrupt register 29 in the interrupt reception processing by the PU 21, and for this guarantee, the access control storage unit 32 on the common memory 20 stores the interrupt register 29 of each CPU 21. In order to individually manage the access right, it is configured to have semaphore flags for the number of interrupt registers 29,
This controls the access right.

FIG. 7 is a flowchart showing the control of the access right. The CPU requesting the interrupt accesses the interrupt register access control storage unit 32 on the common memory 20, determines whether the semaphore flag corresponding to the interrupt register 29 of the other CPU is “0”,
When this is "1", the other CPU has acquired the access right, and therefore waits for the release of the access right of the other CPU (step # 1). When it is "0", "1" is written in the corresponding semaphore flag to acquire the access right, and this is notified to the other CPU (step # 2). Then, a series of processing to the corresponding interrupt register 29 is performed (step # 3), and immediately thereafter, the semaphore flag is set to "0".
To release the access right (step # 4).

FIG. 8 shows a flow chart when the interrupt from the i-th CPU (CPU-i) to the j-th CPU (CPU-j) is performed. CP requesting an interrupt
U-i is the interrupt register 2 of the CPU-j on the other side.
The access right is acquired for the semaphore flag corresponding to 9 according to the access right control flow (step # 1).
1, # 12). Next, the CPU-i accesses the interrupt register 29 in the local area of the CPU-j, reads the contents, and then changes only its own interrupt flag for the CPU-i to "1" (steps # 13, # 1).
4). Based on this information, the interrupt request unit 31 determines that the CPU-j
An interrupt request is issued via the interrupt controller 23 (see FIG. 5, step # 16). At the same time, the CPU-i sets the semaphore flag to "0", and the interrupt register 2
The access right to 9 is released (step # 15).

The CPU-j on the side requested to interrupt recognizes the interrupt request, interrupts the current process (steps # 17, # 18), and then C in the common memory 20.
The access right is acquired in accordance with the access right control flow (see FIG. 7) for the semaphore flag for the interrupt register of PU-j (steps # 19, # 20). Then, by reading the interrupt register 29, the CPU-i requesting the interrupt is recognized (steps # 21 and # 2).
2). Further, only the interrupt flag corresponding to the CPU-i which has requested the interrupt is changed to "0" to initialize the interrupt factor (steps # 23, # 24). Finally CPU-
Set the interrupt register semaphore flag of j to "0",
The access right of the interrupt register is released, the process corresponding to the interrupt is executed, and then the process of returning from the interrupt process is executed (steps # 25, # 26, # 27).

In FIG. 7 and FIG. 8, the processing indicated by a is access that prohibits division, and it is necessary to guarantee this in terms of hardware. As one method for this, T
There is a method of guaranteeing division prohibition by having an AS (test and set) instruction.

The process indicated by b shows the access right control flow of FIG.

[0023]

The conventional example shown in FIG.
As described above, in order to guarantee a series of accesses relating to interrupt generation processing by another CPU and interrupt reception processing by its own CPU, an access control storage unit is provided on the common memory, and this access control storage unit is local to each CPU. It was necessary to configure the interrupt register of semaphore flag individually and perform the access right control flow.
The access right control flow is complicated and the processing time is long.

If the number of CPUs is M and the interrupt level is N stages, the number of semaphore flags is (M × N).
There is also a problem that the number of individuals becomes extremely large, and the management of access rights becomes complicated.

If the interrupt register access control storage unit 32 shown in FIG. 5 is omitted and the access right control flow shown in FIG. 8B is omitted, the following inconvenience occurs.

FIG. 9 shows the CPU-
2 shows the transition of the interrupt flag in the interrupt register in the inter-CPU interrupt control device attached to the receiving CPU when the interrupt request is generated. In the case shown in FIG. 9, since the prohibition of access by the other CPUs is guaranteed and the interrupt request of only the CPU-2 occurs during the period shown by P and Q, normal processing is performed. However, it is difficult to guarantee P and Q by hardware, and if this is not guaranteed, interrupt requests from a plurality of CPUs are mixed and normal processing is not performed as shown in FIGS. 10 and 11. Cause a situation.

FIG. 10 shows a case where the CPU-2 and the CPU-M request an interrupt to the same interrupt register. In this case, the prohibited period of P shown in FIG.
The PU-2 and, subsequently, the CPU-M read the interrupt register, and then write to the CPU-2 to
-2 flag becomes "1", then CPU-M write causes the CPU-2 flag to become "0",
The M flag becomes "1" (see Table 2), and C
The inconvenience that the interrupt request of PU-2 disappears occurs.

FIG. 11 shows a case where an interrupt request is issued from CPU-M while the receiving CPU recognizes the interrupt from CPU-2. In this case, the prohibited period of Q shown in FIG. 9 is not guaranteed, and the receiving CPU and the CPU subsequent to this are not guaranteed.
-M reads the interrupt register and then writes the receiving CPU to change the CPU-2 flag to "0" to initialize the interrupt factor. Then, write CPU-M to the CPU-2 flag and CPU. As a result of the -M flag being set to "1" (see Table 2), the CPU-2 flag is returned to "1", resulting in a double interrupt.

The present invention solves the above-mentioned problems of the conventional example and enables a CPU up to a plurality of interrupt levels.
An object is to provide an inter-interruption control device.

[0030]

In order to achieve the above object, the present invention has a plurality of CPUs in a device, and the interrupting CPU acquires the bus exclusive right of the local bus of the CPU that receives the interrupt and interrupts. CP in the system
In the inter-CPU interrupt control device attached to U, each interrupt level on the side of the CPU receiving the interrupt is the same
An interrupt register composed of an interrupt storage unit having an interrupt flag from, and an interrupt storage information creation unit that creates storage information based on the information in the interrupt storage unit and write information corresponds to each interrupt level. As many as the corresponding number, and an interrupt request unit for requesting an interrupt request to the CPU for each level based on the information in the interrupt storage unit of the interrupt register. Is configured to access the interrupt register for each interrupt level and manage the write operation to the interrupt storage unit according to the information of the interrupt storage unit. Characterize.

[0031]

According to the present invention, since the interrupt register for each interrupt level has the interrupt storing section and the interrupt storing information creating section, the access right to the interrupt register can be obtained by utilizing the characteristics of the interrupt storing information creating section. Control becomes unnecessary, and it becomes unnecessary to dispose the access control storage unit on the common memory as in the conventional example shown in FIG.

[0032]

EXAMPLE An example of the present invention will be described with reference to FIGS. 4 and 12 to 17.

In this embodiment as well, similar to the above-mentioned conventional example, the CPU (transmission CPU) that issues an interrupt is the CPU (reception C) that is the interruption destination.
It is configured to perform an interrupt between CPUs by acquiring the bus occupation right of the local bus (PU) and storing the interrupt information. The basic system is shown in FIG. 4, but in the above-mentioned conventional example, an access control storage unit constituted by a semaphore flag is provided on the common memory 20, and the access right control flow shown in FIG. 8 is provided. On the other hand, in the present embodiment, the CPs provided in each local area without providing them
The U-interrupt controller 25 is characterized in that it has an access right control function.

The basic configuration of the system shown in FIG. 4 is the same as that explained in the above-mentioned conventional example, and therefore its explanation is omitted.

As shown in FIG. 12, the inter-CPU interrupt controller 25 comprises a plurality of interrupt registers 33, an interrupt request unit 36 and an address decoder 37.

The interrupt register 33 creates stored information based on the information in the interrupt storage unit 35 and the interrupt storage unit 35 having the same interrupt level on the receiving CPU side and the flag from each transmitting CPU. And the interrupt storage information creation unit 34. Then, the inter-CPU interrupt controller 25, as shown in FIG. 12 and Table 4, is an interrupt register including an interrupt register for interrupt level 1, an interrupt register for interrupt level 2, ..., An interrupt register for interrupt level N. A group, that is, an interrupt register group provided so as to correspond to each interrupt level.

[0037]

[Table 4]

The interrupt request unit 36 is the interrupt storage unit 3
It has a function of requesting an interrupt request to the CPU 21 for each level based on the information of 5.

The address decoder 38 has a function of selecting one of the plurality of interrupt registers 33 to make it accessible.

Table 5 shows the state transition of the interrupt flag in the interrupt storage unit 35. As shown in this table, the flag information after access is the exclusive OR of the pre-access flag information and the write flag information.

[0041]

[Table 5]

That is, writing "0" to the interrupt flag does not change the internal information, and writing "1" inverts the internal information. Then, write "1" only to a flag that generates an interrupt or a flag that initializes, and write "0" to other flags to retain the internal information. You can

Since the transmitting CPU 21 knows the flag for generating an interrupt in advance, by setting only that flag to "1" and writing it in the interrupt register 33,
Information on other flags can be held. Also received CP
U21 is the interrupt register 3 of the interrupt level interrupted
By reading out 3, the sending CPU 21 determines which CPU 2
It is possible to recognize whether it is 1, and to the interrupt register 33,
By writing only the flags that require initialization to "1" and writing, the information of other CPU flags can be held.

FIG. 13 shows a flowchart for accessing the interrupt register 33 from the transmission CPU 21. FIG. 14 shows a flowchart for the receiving CPU to access the interrupt register 33. These explanations will be given later in FIG.
Concretely based on 7.

FIG. 15 and FIG. 16 more specifically show the configuration of this embodiment. Each interrupt register 33 divided according to the corresponding interrupt level has a total of M bits for the CPU-1 flag to the CPU-M flag and is connected to the data bus. The interrupt storage information unit 34 has a data bus as an input and an output of the interrupt storage unit 35, is configured by exclusive OR, and is connected to the interrupt storage unit 35. The interrupt storage unit 35 is connected to the data bus via the buffer and can be read.

The interrupt request unit 36 has a configuration in which the output of the interrupt storage unit 35 is logically ORed for each interrupt level.
An interrupt request is issued to the PU 21 for each interrupt request level. That is, the interrupt request unit 37 transmits one of the interrupt request signal level 1, the interrupt request signal level 2, ..., And the interrupt request signal level N to the interrupt control unit 23 (FIG. 4). The address decoder 37 selects one of the interrupt registers 33 based on the address signal from the connected address bus.

Next, based on FIG. 17, CPU-i to CPU
The interrupt operation of interrupt level k to -j will be described.

First, the CPU-i is a CP which is a receiving CPU.
The bus control right of the U-j local bus is given to the bus control unit 18
(Via Figure 4). Then CPU-i is CPU
It is determined whether the CPU-i flag of the interrupt register 33 for the interrupt level k of the inter-CPU interrupt controller 25 attached to -j is "1" or "0", and if it is "1", the process waits (step). # 31). If it is "0", only the bit corresponding to the flag is set to "1" and written in the interrupt register 33. Based on this, the interrupt storage information creation unit 34 sets only the CPU-i flag to "1". It is inverted and stored in the interrupt storage unit 35 (step # 32). The interrupt storing unit 35 transmits the CPU-i interrupt information to the interrupt requesting unit 36, and the interrupt requesting unit 36 requests the CPU-j to perform interrupt processing at the interrupt level k (step # 33).
The CPU-j recognizes the interrupt request of the interrupt level k (step # 34) and interrupts the current process (step # 34).
35).

Next, the CPU-j reads the interrupt register 33 of the interrupt level k (step # 36), and the CPU
Recognizing that the flag for -i is "1", CPU-i
It is recognized as an interrupt from (step # 37). Then, only the bit corresponding to the CPU-i flag is set to "1" and written in the interrupt register 33 (step # 38).
The interrupt storage information creation unit 34 inverts only the CPU-i flag to "0" and stores it in the interrupt storage unit 35.
As a result, the CPU-i flag is initialized (step # 39). After that, the CPU-j executes the interrupt processing of the interrupt level k from the CPU-i, and then executes the return processing from the interrupt processing (steps # 40, # 4).
1). Inter-CPU interrupt control device 25 described above
Has an interrupt storage information creation unit 34 in the interrupt register 33 for each interrupt level, and it is necessary to arrange the access control storage unit on the common memory as in the conventional example shown in FIG. Disappears.

The basic structure and operation of the inter-CPU interrupt control device of this embodiment have been described above.
By executing the process flow indicated by I and II, it is possible to smoothly perform the process of delivering a large amount of information associated with the interrupt. That is, an information storage unit is provided for each interrupt CPU on the common memory 20 (FIG. 4), and each interrupt register 3
Information can be stored and information can be read out by using the interrupt flag in 3. The process flow indicated by I in FIG. 17 shows a process (step # 51) of storing information at the time of CPU-i and level k in the common memory 20,
The process flow indicated by II in FIG. 17 is a process of reading the information written in the process indicated by I from the common memory 20 (step #
52), the access right to the information storage section on the common memory 20 in these is the interrupt register 3
Guaranteed by the interrupt flag in 3. As described above, the inter-CPU interrupt control device is highly expandable in the transfer of information between CPUs by an interrupt.

[0051]

According to the present invention, the access control storage unit on the common memory and the access right control flow using this access control storage unit, which were required in the conventional example, are not required, so that an interrupt between CPUs is not required. Although the processing time can be shortened and the structure can be simplified, multiple CPUs can be used.
C capable of enabling interrupts at multiple levels between
An inter-PU interrupt controller can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first conventional example.

FIG. 2 is a configuration diagram showing a first conventional CPU interrupt control device.

FIG. 3 is an explanatory diagram showing a problem of the first conventional example.

FIG. 4 is a configuration diagram showing a system used in the present invention and a second conventional example.

FIG. 5 is a configuration diagram showing an inter-CPU interrupt control device and an access control storage unit in a second conventional example.

FIG. 6 is a circuit configuration diagram showing an interrupt register and an interrupt request unit in a second conventional example.

FIG. 7 is a flowchart showing an operation of access right control in the second conventional example.

FIG. 8 is a flowchart showing the operation of the inter-CPU interrupt control device in the second conventional example.

FIG. 9 is an explanatory diagram showing flag transitions in the interrupt storage unit in the interrupt register in the second conventional example.

FIG. 10 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 11 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 12 is an internal configuration diagram of an inter-CPU interrupt control device according to an embodiment of the present invention.

FIG. 13 is a flowchart illustrating an operation when accessing the interrupt register from the transmission CPU according to the embodiment of the present invention.

FIG. 14 is a flowchart illustrating an operation when accessing the interrupt register from the receiving CPU according to the embodiment of the present invention.

FIG. 15 is a configuration diagram showing an inter-CPU interrupt control device in an embodiment of the present invention.

FIG. 16 is a circuit configuration diagram showing an interrupt register and an interrupt request unit in the embodiment of the present invention.

FIG. 17 is a flowchart illustrating the operation of the inter-CPU interrupt control device according to the embodiment of the present invention.

[Explanation of symbols]

 21 CPU 33 Interrupt Register 34 Interrupt Storage Information Creation Unit 35 Interrupt Storage Unit 36 Interrupt Request Unit 37 Address Decoder

Claims (1)

[Claims] 1. An inter-CPU interrupt control attached to each CPU in a system having a plurality of CPUs in a device, and a CPU issuing an interrupt acquires a bus occupation right of a local bus of the CPU receiving the interrupt and makes an interrupt. In the device, each interrupt level on the CPU side that receives an interrupt is the same, and each C
An interrupt register composed of an interrupt storage unit having an interrupt flag from the PU and an interrupt storage information creation unit that creates storage information based on the information in the interrupt storage unit and write information is provided for each interrupt level. The corresponding number is provided so as to correspond to the CP, based on the information in the interrupt storage section of the interrupt register.
An interrupt request unit for requesting an interrupt to U by level is provided, and an address decoder for selecting one of the plurality of interrupt registers to make it accessible is provided. Access each time,
CPU configured to manage write operation to the interrupt storage unit based on information in the interrupt storage unit
Interrupt control device.