JPH05506338A - frequency synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Name of invention Frequency synthesizer Technical field This invention relates to frequency synthesis. In particular, for example, cellular radio systems It is applied to frequency synthesizers used in wireless systems such as .

technology n weight Generally, a frequency synthesizer uses a reference signal as a source and uses the reference frequency to a multiple (for indirect synthesizers) or a quotient (for direct synthesizers) of the reference signal. A predetermined output frequency is synthesized as Appropriate ratio of output frequency and reference frequency control signals from analog or digital means.

In a typical direct frequency synthesizer, the input reference frequency is the frequency being synthesized. is directly divided to provide an output signal of the required frequency, much higher than the number . A low pass filter reduces quantization noise in this output signal. direct frequency One drawback of synthesizers is that the reference signal must be at a higher frequency than the output signal. This is important. For this reason, cellular radios whose output frequency is close to the limits of manufacturing technology It is unsuitable for such applications. Another drawback is high resolution digital/analog conversion If a frequency synthesizer is manufactured using an integrated circuit, If built, substantial technical problems arise.

In a typical indirect frequency synthesizer, the division is done in the feedback path. It will be done. The frequency of the input reference signal is approximately equal to the divided frequency. actually divided The signal that is generated is the desired output signal, which is the highest signal that should be generated in the circuit. This is the number. Therefore, indirect frequency synthesizers are suitable for cellular radio applications. .

In both direct and indirect frequency synthesizers, quantization eliminates spurious The problem is that the arise. Analog/digital synthesizers that use sine lookup tables Accurate matching between the digital value and the time delay at the output of the voltage controlled pulse delay Phase accumulator, periodic wave function conversion data in the form of read-only memory (RAM) By applying it to a digital-to-analog converter, the entire frequency spectrum can be This is because they still exist in the vicinity of the wave number. This is due to the disadvantages and securities of this technology as mentioned above. As the number of users of the Lula wireless system increases, communication channels within the allocated band The number of channels increases. This results in a more accurate reference or mixing frequency for each channel. finer-grained signals to accurately divide the frequency and minimize spurious and/or phase noise. Frequency resolution is required.

detecting means, e.g. changing in response to a phase difference between the reference signal and the phase control signal (f4); a detection means (110) that generates a control signal to It consists of a connection block and a low synthesizer that filters the control signal.

Figure 5 is a block diagram applicable to both indirect and direct synthesizers. It is.

The signal changes the time interval discretely rather than continuously. In fact, sigma-delta modulation The filter 102 operates as an all-band pass filter for a substantially constant control signal δφ. , it operates as a bypass filter for quantization noise. This noise is It is unique within the ma/delta modulator 102. Analog sigma delta modulation Where the circuit 102 is used, the noise is generated near the phase control signal f4 and its multiples. In other words, the power spectral density is reduced. Digital sigma-delta modulator Where used, reduced spurious frequency components near frequency f0 and its multiples is the zero position of the bypass filter function in DC, the phase control signal f, and its multiples. Occurs in frequency.

FIG. 2 includes a variable coefficient divider 106 and a second order sigma-delta modulator 102. .

N divider 100 is shown with second order sigma-delta modulator 102 shown in more detail. It will be done. In embodiments of the invention, variable coefficient divider 106 includes two coefficient programmers. Bull Divider (Component Manufactured by Bulleacy Semiconductor Limited) 5P8716). Two coefficient programmable divider 1 06 is the control signal 1 or The frequency f. is divided alternately by 40" and "41" depending on the state of 0. Ru.

The phase control signal f, which is the output of the two coefficient programmable frequency divider 106, is on line 10. 8 to a phase detector 110 (FIG. 1).

In the sigma-delta modulator 102, two complementary control signals δφ are sent to the adder 20. 2. A positive reference signal (+REF) or a negative reference signal (-REF) is selected. is applied to the second input of adder 202 via line 204 from director 206 .

Selector 206 selects the output of sigma-delta modulator 102 [104 from selector 2 Depending on the state of the ratio control signal b(t) applied to 06, the positive reference signal (+REF) or a negative reference signal (-REF) from the power supplies 208 and 210, respectively.

The adder 202 receives a positive reference signal (+REF) or a negative reference signal (-REF) and a control signal. δφ and the sum is printed on accumulator 214 via line 212. added.

In normal operation, the control signal δφ is greater than (-REF/2) and (+RE F/2). In a 16-bit configuration, REF is, for example, 8192 It may be the number of The frequency control signal δφ has a constant or slowly changing level. and therefore the reference signal applied to adder 202 is constant or slowly varying. The levels can be switched alternately. The input of accumulator 214 is 2 with sign The output is an unsigned binary number that can be raised or lowered. . In the second accumulator 216, an unsigned binary number is stored previously. is added to the value stored in accumulator 216, increasing the value stored in accumulator 216.

The overflowed 1-bit output of accumulator 216 is is stored by the delay means or latch 218 until the cycle (signal ta). the It is then provided as the output of the sigma-delta modulator 102 via line 104. ( Latches 218 and accumulators 214, 216 are all driven by signal f. clocked. ) Quantization noise occurs when the output of the sigma-delta modulator 102 is, for example, 1 bit. Since the input is a high resolution signal such as the signal δφ, the quantization noise is low. The sigma-delta modulator 102 is unique within the sigma-delta modulator 102. However, as mentioned above , the noise is shifted from DC, and the frequency of the phase control signal f4 and its multiples is shifted from DC. The problem of real frequency and/or phase noise is improved. sigma delta modulator By increasing the number of bits in the signal or by connecting sigma-delta modulators in series, one bit can be Arbitrarily fine resolution is possible even if the output itself constitutes a coarse resolution.

The basic phase-locked loop without a sigma-delta modulator has two frequencies, f , Xn or f, X (n+1) can be synthesized. sigma delta If the sigma-delta modulator 102 has enough bits, Which period between f, X (n+0.25) and f lx (n + 0.75) It can also be synthesized using wave numbers.

As the number of bits increases, the resolution of frequencies that can be synthesized increases.

In Figure 3, the same as that shown in Figure 1, but with a two-stage variable coefficient frequency divider. Another N divider is shown having a sigma-delta modulator 102 including a sigma-delta modulator 102. sigma de The router modulator 102 is controlled by a frequency control signal δφ. Signal bit sea The second control signal (4) containing the signal is applied to the 3-1 multiplexer 302. that At the same time, the output of the sigma-delta modulator 102 is sent to the 3-1 multiplexer 302. 304.308 to the previous clock frequency of the sigma-delta modulator 102. The first output is applied via a one bit delay device 306.

[The output of 3-1 multiplexer 302 on 310 is divided into 3 or 4 by frequency divider 312. It will be surrounded. This frequency divider 312 outputs a signal f. and the resulting fe, is applied to a divide-by-16 frequency divider 316 via line 314. 16 frequency divider 316 is phase controlled Outputs signal f4. The 16 frequency divider 316 is composed of 16 stages, and is typically divided into 16 stages. Displayed in 4 bits or 8 bits depending on the counter execution.

The instantaneous state of the 16 frequency divider 316 is applied to the control logic circuit 318 and the multiplexer 3o. Control 2. The control logic circuit 318 and the 3-1 multiplexer 302 are connected to the frequency divider 312. It is clocked by output f1. In the actual example, the control signal ■4 is It includes 14 "1's" or "0" and two "O"s indicating the integer part of the circumferential ratio.

The control logic circuit 318 is configured so that the multiplexer 302 receives (i) the second control signal 6, (ii) the direct output of the sigma-delta modulator 102; (iii) the sigma-delta modulator 10; control to select one of the two delayed outputs. For the first 14 cycles, Control signal I controls a 3 or 4 frequency divider 312. In the 15th cycle, 3 prongs The divide-by-4 frequency divider 312 is controlled by the direct output of the sigma-delta modulator 102. Ru. The 16th cycle is controlled by the output of 1-bit delay device 306. . As a result, the coefficient-programmable frequency divider 106 provides an integer portion of the division ratio and Using Id representing δφ that represents the fractional part of the division ratio, any arbitrary value between 49 and 63 divided by a number. The phase control signal f6, which is the output of the 16 frequency division counter 316, is 1 bit. is used as a clock for delay unit 306. In the above, indirect frequency synchronization Although a synthesizer has been described, the present invention can also be applied directly to a synthesizer. .

Figure 4 shows such a direct synthesizer. FIG. 4 shows the sigma-delta modulator 102 and a coefficient programmable frequency divider 106, and has a configuration similar to that of FIGS. 1, 2, and 3. It is. The reference frequency f1 is applied to the coefficient programmable frequency divider 106, and its output The forces are output signals f, d of the desired frequency. The frequency of the reference signal f1 is the output signal f . , which is a much higher frequency than . This frequency division ratio is determined by the sigma-delta modulator 102. is controlled by a control signal δφ applied to.

This frequency division ratio is determined by the positive reference signal (+REF) and negative reference signal in sigma-delta modulator 102. It is controlled by changing the value of the quasi signal (-REF). The division ratio is δφ /REF, so the frequency of the output signal fad changes linearly with REF. do. As a result, by fixedly increasing the reference voltage, the output frequency f, , 4 can be increased linearly.

In short, the direct frequency synthesizer includes a phase detector 110, a low-pass filter 1 14 and voltage controlled oscillator 118 removed fractional-N frequency divider 100 example For example, it corresponds to the frequency synthesizer of FIG.

The fractional-N frequency divider 100 in FIG. 3 can be used for both direct and indirect synthesizers. It can also be used for

In order to work as a good pseudorandom number generator (PN), all digital The magma-delta modulator must be able to generate long pit sequences. No. Sequence length is one of several figures of merit for a PN generator. Therefore, all PN generators have a finite sequence length. however , under certain conditions, all second-order digital sigma-delta modulators are suitable for practical use. It is not possible to generate a sequence length that is sufficiently satisfactory. This condition applies to Sigma Del At the input to the data modulator, a static signal with many zeros in the least significant bit of the binary It is generated by the appearance of the target signal δφ. For example, sigma-delta modulator 10 2, if the control signal δφ is 20 in binary representation 0001000000000 If it is a "rounded" binary number like 48, it will depend on the initial state of accumulator 214. Therefore, the sequence length can be shortened to 4. The initial state of the accumulator 214 is If it is a “rounded” binary number (+REF), the initial conditions and frequency control signal δφ are all The input of the second accumulator 216 is also "rounded", No accumulator rotates through many states.

A simple solution applies to sigma-delta modulator 102, accumulator 214 is The accumulator 214 is multiplied by an odd binary number or the accumulator 214 is multiplied by a value of 0. Enter an odd number on the dose line 122 one cycle after . The predetermined control signal δφ is then The inputs are as described above for normal operation during the cycle. Applicability for this odd number The correct value would be 17.

Next, the short sequence problem can be solved by modifying the sigma-delta modulator 102. i.e. 3 or more with 2 or 3 feedback buses. This can be solved by providing an integrator. One of the feedback paths is While "rounding" remains in the force criterion, use a criterion that is not "rounding."

Figure 5 shows both the indirect frequency synthesizer of Figure 1 and the direct frequency synthesizer of Figure 4. Indicates the transformation applied to . two sigma-delta modulators 102 and 10 respectively 2' are connected in series via an adder 502. of the sigma-delta modulator 102 The output is applied to the output of adder 502, and the output of adder 502 is applied to the sigma delta transformer. applied to the input of regulator 102'. Multi-bit (16-bit) second frequency system Control signal δφ. is applied to the input of sigma-delta modulator 102. sigma del The output of the data modulator 102 is 1 bit, which is added to the third frequency control by the adder 502. It is added to the second least significant bit of the control signal δφ. The second frequency control signal δφ0 is This is an offset to the third frequency control signal δφ. Third frequency control signal δφ indicates a coarse adjustment in the fractional part of the quotient of the total frequency division, and the second frequency control signal δφ.

indicates fine adjustment of the division quotient. In other words, the control signal δφ1 and the control signal δφ0 are combined. The combined signal has higher resolution compared to the frequency control signal δφ of FIG.

Since the human input signal of sigma-delta modulator 102' is now active, the short sequence There is no problem with the distance length.

Many modifications and substitutions will occur to those skilled in the art. For example, as mentioned above (as disclosed by andy, analog type to sigma delta modulator) You can also use The output of delay means or latch 218 is multi-bit. Alternatively, coefficient programmable frequency divider 106 may be a multi-bit multi-fractional frequency divider. Good too.

Other variations include adder 202 and accumulators 214 and 216, respectively. It concerns many addition methods that may be performed. As mentioned above, these are the same For example, instead of being executed at the intermediate clock f or the input in the embodiment of FIG. signal f. It can be executed serially using

A sigma-delta modulator is used to generate a multiple-bit output; Appropriate modulation of the programmable frequency divider responsive to the signal can be used.

industrial stress Embodiments of the frequency synthesizer of the present invention are particularly adapted to cellular radio systems. However, its application is not limited to cellular radio systems.

Its applications are synthetic frequency modulation and mixed analog and digital sigma-delta modulation. It also includes a linear frequency stable on-chip voltage controlled oscillator.

For example, the embodiment shown in FIG. If used for channel selection, it can be used for synthetic frequency modulation. In that case, the second Frequency control signal δφ. modulates the instantaneous output frequency f0 with respect to the channel frequency will be used for. In addition, the fifth embodiment is an analog sigma delta By using the modulator 102 and the digital sigma-delta modulator 102', can be modified for use as a voltage controlled oscillator. Third frequency control signal δφ , can be fixed digital signals used for channel selection. second Frequency control signal δφ. can be an analog variable voltage to control the output frequency Wear.

In the embodiment of FIG. 1, the variable output frequency is f. It can be done. In the fourth embodiment , the variable output frequency can be fod. In both cases, the output frequency is Its stability is improved by the fact that it is associated with quasi-signals.

Copy and translation of written amendment) Submission form (Article 184-7, Paragraph 1 of the Patent Act) May 20, 1992

Claims (1)

[Claims] 1. A control signal that changes in response to the phase difference between the reference signal and the phase control signal (fd). detection means (110) for generating and an output whose frequency changes in response to said control signal; means (118) for generating a signal (fo); The output signal (fo) is controlled according to the division ratio control signal b(t) applied to the control input. means (106) for dividing the frequency and supplying the phase control signal (fd); (δφ) and the frequency division ratio control signal b(t) according to the phase control signal (fd). and extracts quantization noise from the phase control signal (fd) and its multiple frequency. a second or higher order signal to be removed to generate the frequency division ratio control signal b(t); A frequency synthesizer characterized by comprising a ma-delta modulation means (102). . 2. In claim 1, The sigma-delta modulation means (102) include means (208) for providing a reference signal REF. , 210), addition means (210) for adding the control signal δφ and the reference signal REF. 02), and frequency division control according to the added value of the control signal δφ and the reference signal REF. accumulator means (214, 216) for supplying control signals. Frequency synthesizer with characteristics. 3. In claim 2, The reference signal supply means selectively supplies a positive reference signal (+REF) and a negative reference signal (-REF). F), The sigma-delta modulation means (102) further operates according to the frequency division ratio control signal. A positive reference signal (+REF) and a negative reference signal (-REF) are input to the adding means (202). A frequency synchronizer characterized in that it comprises a selection means (206) for supplying one of the following. Sessaisa. 4. In claim 2, The accumulator means comprises a plurality of cascaded accumulators (214, 216). 5. In claim 3, The accumulator means comprises a plurality of cascaded accumulators (214, 216). 6. In claim 1, The second or higher order sigma-delta modulation means receives a third frequency control signal. A plurality of secondary or consists of a higher-order sigma-delta modulator, and a second frequency control signal a sigma signal controlled by δφo and whose output is connected to one of the inputs of the addition means. a delta modulator (102); The output of the adding means (502) is controlled by the output of the frequency divider (106). ), a sigma-delta modulation means (102') connected to the frequency synthesizer. 7. In claim 1, The frequency dividing means divides the output signal by one of two frequency division ratios and generates an intermediate signal fm. a first frequency divider (312) that supplies the intermediate signal fm by a third frequency division ratio; a second frequency dividing means (316) which divides the frequency of the signal and supplies the phase control signal fd; intermediate signal fm, second frequency according to the instantaneous state of the second frequency dividing means (316); The clock is clocked by the control signal Id and the output from the sigma-delta modulation means (102). and the first frequency divider (312) has either a first frequency division ratio or a second frequency division ratio. control means (302, 318) for controlling the selection of the Frequency synthesizer with characteristics. 8. In claim 7, Furthermore, a second delay means delays the output of the sigma-delta modulation means (102). (306), The control means modulates the sigma-delta modulation means by a second frequency control signal fd. (102) or the output of the second delay means (306). The selection means (302) controls the voltage applied to the frequency divider (312) of 1. A frequency synthesizer featuring: 9. In claim 1, A frequency synthesizer, wherein the detection means includes a phase detector. 10. In claim 1, A frequency synthesizer characterized in that said means for generating an output signal includes an oscillator. The. 11. The reference signal fr of a predetermined frequency is divided, and the division ratio is determined by the division ratio control signal b ( t) to provide an output signal fod of the desired frequency; Step (106) and The frequency division ratio is determined in response to the control signal δφ and the output signal fod from the frequency dividing means (106). sigma-delta modulation means (102) for supplying a control signal b(t); The frequency division is performed by removing quantization noise from the output signal (FOD) and its multiple frequency. A frequency synthesizer characterized in that it generates a ratio control signal b(t). 12. In claim 11, The second or higher order sigma-delta modulation means (102) is a reference signal. means for supplying REF, an adder for adding the control signal δφ and the reference signal REF; according to the calculating means (202) and the added value of the control signal δφ and the reference signal REF. accumulator means (214, 216) for supplying said frequency division ratio control signal; A frequency synthesizer comprising: 13. In claim 12, The reference signal supply means supplies a positive reference signal (+REF) and a negative reference signal (-REF). and the modulating means (102) further modulates the adding means according to the frequency division ratio control signal. (202) is either the positive reference signal (+REF) or the negative reference signal (-REF). A frequency synthesizer characterized by comprising a selection means (206) for applying a . 14. In claim 12, The accumulator means comprises a plurality of cascaded accumulators (214, 216). 15. In claim 13, The accumulator means comprises a plurality of cascaded accumulators (214, 216). 16. In claim 11, The sigma-delta modulation means is a summing means controlled by a third frequency control signal δφi. comprising a plurality of sigma-delta modulators cascaded by means (502); is controlled by the second frequency control signal δφo, and its output is the input of the adding means. a sigma-delta modulator (102) connected together and said summing means (502); and whose output is connected to the frequency divider (106). A frequency synthesizer comprising: delta modulation means (102') . 17. In claim 11, The frequency dividing means divides the output signal by one of two frequency division ratios and generates an intermediate signal fm. a first frequency divider (312) that supplies the intermediate signal fm by a third frequency division ratio; a second frequency dividing means (316) which divides the frequency of the signal and supplies the phase control signal fd; intermediate signal fm, second frequency according to the instantaneous state of the second frequency dividing means (316); The clock is clocked by the control signal Id and the output from the sigma-delta modulation means (102). and the first frequency divider (312) has either a first frequency division ratio or a second frequency division ratio. control means (302, 318) for controlling the selection of the Frequency synthesizer with characteristics. 18. In claim 17, Furthermore, a second delay means delays the output of the sigma-delta modulation means (102). (306), The control means modulates the sigma-delta modulation means by a second frequency control signal fd. (102) or the output of the second delay means (306). The selection means (302) controls the voltage applied to the frequency divider (312) of 1. A frequency synthesizer featuring: 19. In claim 11, A frequency synthesizer, wherein the detection means includes a phase detector. 20. In claim 11, A frequency synthesizer characterized in that said means for generating an output signal includes an oscillator. The. 21. In claim 12, The present invention further includes means for changing the amplitude of the reference signal REF in accordance with the frequency division ratio control signal. A frequency synthesizer featuring: