JPH05500124A - Concurrent computation/communication mechanism in SIMD architecture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Parallel computation/communication mechanism in SIMD architecture (technical field) TECHNICAL FIELD The present invention relates to computer processor architecture, and in particular to SIMD processor architecture. The present invention relates to architectures that provide parallel computation/communication in architectures. this The architecture supports simultaneous data processing and Contains an outgoing processor node that enables communication.

(Background technology) Neural networks allow computers to closely approximate human thought processes. It is a form of architecture that enables neural network a One form of architecture is that a single command can be sent to multiple processors and therefore data Single instruction stream, multiple data streams that allow sets to be commanded simultaneously Enables stream (SIMD) operations.

using existing conventional algorithms executed by traditional conventional computers. There are some important real problems that cannot be solved. These problems are , many small constraints that are often poorly specified and require a large search space. Characterized by

Computers such as computer voice recognition, computer vision and robot control The main processing of recognition information by computers belongs to this category. Traditional calculation model If used to solve this type of problem, the I get stuck. Animals also do this using neurons that are millions of times slower than transistors. perform these tasks. Neuron can be expressed as ΣW + + 0 + Performs a weighted sum of possible inputs. Here wll is the value pulled from memory, 0. is the human power value. The SIMD multiply/accumulate function performs this operation.

Feldman's 1oo step is an argument for massively parallel operations. The rule is that a "human" cognitive process with a duration of 500 milliseconds It is stated that implementation is possible within the uron switching time. If this “Sui.

If switching time is slow, configure a high-speed system with many switches. 4, which indicates that two very different computational models are used. suggest This can also be used to build a computer that does what the nervous system does. The computer must be configured to emulate the animal's nervous system. This suggests that there is no such thing. SIMD systems are massively parallel neural networks. A computing system designed to emulate a workpiece.

Nervous system and neuro-computing computers are free from human noise and hardware Characterized by continuous, non-symbolic, massively parallel structures with fault tolerance ing. The display, or input, independently reaches the result, or conclusion, and therefore the final output, the conclusion. distributed among groups of computational elements that generalize and interpolate information to arrive at a theory.

In other words, connectionist/neural networks are Find a ``good'' solution using massively parallel operations on computational elements. This model is based on the hypothesis It is one of the relaxations to the dominant or ``most likely'' hypothesis. .

The search speed is more or less independent of the size of the search space1, and learning In contrast to the allocation of data structure, a program that incrementally changes the strength of connections (synapses) It is a process. "Programming" in such neural networks ” is an example.

Total connectivity or near total connectivity (more than 30%) of communicating nodes/units is configured. processors on both sides communicate with each other after the data set is used. A lot of time is wasted waiting for things to happen. A known processing unit handles all processes. to subsequent data sets until the server nodes send their previously used data. It does not provide a mechanism that allows operations to occur.

(Disclosure of invention) It is an object of the present invention to provide parallel computing and communication functions in a SIMD structure. Provides a usage architecture.

Another object of the invention is that a similar output processor is Providing an output processor architecture that retains processing data while sending data It is in.

Another object of the invention is to provide an intermediate processing method for the processor to operate on subsequent data sets. The purpose of the invention is to provide an output processor that stores the logical data.

A fourth object of the present invention is to arbitrate communication protocols on a communication network. 9. The concurrent use architecture of the present invention consists in providing a mechanism in the output processor of The controller is a single instruction including an input bus, a person crab unit, an operation unit and an output bus. Stream 1, used in multi-core data stream processor notebooks. Figure 1. This architecture can be used to perform various operations such as an output processor with an output rose 77 unit that receives data from the unit; include. The processor note stores and outputs data from the output Huff 7 unit. power bus to transmit at the selected time. S Commands IMD operation and executes processor node between the output processor notes and output buffer units, and associated output processor notes and output buffer units. A control unit is provided for controlling the data exchange. The output processor It has an internal controller that directs the storage and transmission of data on the device.

The foregoing and other objects and advantages of the present invention will be further explained with reference to the drawings. It will become clearer if you read it.

(Brief explanation of the drawing) FIG. 1 is a schematic diagram of an array of processor notes constructed in accordance with the present invention; FIG. , an outline of the circular communication pattern of the communication nodes included in the processor notebook in Figure 1. figure, FIG. 3 is a block diagram of a single processor node of the present invention. Regarding the drawings, first, in Figure 1, there is a single instruction stream, multiple data streams. An array of system (SIMD) processors is indicated generally at 10. The array 10 is , processor node 12.14.16.18, and as needed for a particular application. A large number of processor nodes may be included. Figure 1 is for simplicity , and to enable the description of interactions between large numbers of processor nodes. 1. Contains only 4 processor nodes. Each processor note has an input bus 20 and an output bus 22. Buses 20 and 22 are shown in FIG. Although presented as a single entity structure, in some cases human and/or The power bus may have a multiple bus structure.1゜One controller 24 is connected to the control bus 2. 6, this lotus is historically connected to each of the processor notes 1, In some cases, output bus 22 is directly connected to human-powered bus 20 by line 28, and in some cases Alternatively, the output bus 22 is connected to the input bus of another array of Blosset→No.notes. However, the output bus of another array of processor notes should be connected to input bus 20. stomach.

As shown in Figure 1, each processor note (PN) 1 pair or more, such as connecting notes (cN) indicated by 30 to 37 in nodes 12 to 28. , CN is a neural network whose state is located in PN. 1. Each PN associated with an emulated note in the may have several CNs placed. Traditional computer architecture display Therefore, processor note 12 provides state information for connected node 0 (CNO). information, and state information for connected node 4 (CN4), The port 14 provides status information for connection node 1 (CNI) and connection node 5. The processor note 16 transmits the status information for the connection notebook 2 (CN5) to the connection notebook 2 (CN5). state information for CN2) and state information for connected node 6 (CN6). , and the processor node 18 also provides state information for the connection node 3 (CN3). and state information for connection node 7 (CN7). .

Referring temporarily to Figure 2, the broadcast pattern set up between connected nodes 0 to 7 is shown. CN is configured in layer J, and CN0-CN3 are 1 CN4 to CN7 include a second layer. mentioned earlier , any one processor node or There are more than two layers of connection notes in a ray. , connected nodes broadcast It operates in what is called a hierarchy, in which each connected node 0-3 is a connected node. Broadcast to each of 4 to 7. An exemplary example for configuring such a circular hierarchy: The method is from Ha+nmer published on January 3, 1989, which is cited in the text for reference. - U.S. Patent No. 4,796,199 to Strom et al. [Neural Model Information Processing] NEURAL-MODEL INFORMA TION-HANDLING ARCH! TECTURE AND METHO 1゜ disclosed in “D’)” Conceptually, the processor nodes that can be used are The processor's In this case, one processor note broadcast its output to all other processor nodes. Output processor node structure By using the It is possible to make two connections. The known conventional SIMD structure has n clocks. 02 connections can be made in 3 layers, i.e. 50% more configuration.

The normal sequence of events in a SIMD array, shown at 10, is as follows: starts with a specific portion of data sent to the server node. The data is on the input bus 20. Operated by a single command sent. Each processor node performs any operations required by the output bus 22, and then transmits the information via the output bus Attempt to transmit. Obviously, each processor note sends to the output bus at the same time. Under normal conditions, each processor node in the array The processor notebook will run many clocks until the processor sends its information onto the output bus. i.e. it has to wait for a cycle.During this waiting time, the processor node It is necessarily idle because it cannot perform another function until it is sent out. To solve this problem, 38.40.42 and An output processor or output buffer as shown at 44 is provided at each processor node. included in the architecture of the code. , the output buffer receives information from the associated connected node. each processor node receives a transmission response on output bus 22. retain this information or data until such time as possible.

Since the data is held in the output buffer, the IJ processor note The remainder of the idle processor notes can perform other functions. .

The various processors are configured to transmit the notes to the output bus 221- at the appropriate times. To control arbitration between nodes, each processor node has a flip 70 tube 46. ．． 1. Including flip 70 tubes such as 48.50 and 52. flip 70 tube Also referred to in the text as an arbitration signal generator.

3, one processor node, such as processor node 12, The remaining components of the code are shown in further detail. , the node 12 connects the human-powered bus 20 and and an input unit 54 connected to the output bus 30. Once again, the only human-powered bus and output are shown for simplicity. large number of manpower and/or output If a bus is provided, the input crab unit 54 and other units described in the text has a connection with each output bus. The processor node controller 56 is 1 provided for establishing operational parameters for each processor node. , the addition unit 58 performs addition and inputs human power from the input unit 54 and the multiplier 60. Connected to receiving and input/output buses.

Register unit 62 includes a register array, which is configured as desired by the architecture. In the preferred embodiment, it includes 32 16-bit registers. many other configurations 1, the weighted address generation unit 64 has a standby memory Compute the next address for unit 66. In a preferred embodiment, This memory address can be accessed in two ways: (1) into a weighted address register; Write directly or (2) Add the contents of the weighted offset register to memory. set in one of the assertions of the command to be added to the current contents of the address register. This will result in a new address. Note controller 56 , addition unit 58, multiplier 60, register unit 62 and weighted address. The generation unit 64 has a 1° output including what is referred to in the text as the operating unit. Ninit 68 is used to store data before it is sent onto output bus 22. 1. The output unit 68 is provided with the remaining output unit 68 before data transmission. includes an output processor node 38 that receives data from the output processor node 38; The data is one or more connection nodes such as connection node 30 or 34 that are part of the 8L connection node. 1, output unit 68 sends the first processed data to output bus 22. includes an output buffer register that receives the output buffer register. This data is loaded into the 14g+ register. When the output buffer unit is Once in a state, the output buffer is independent of, but identical to, the rest of the processor node. Operates periodically.

Since only one PN can use the output bus at a time, no output buffer or To determine which power processor node transmits first on output bus 22, 1. An arbitration process is provided between the output buffers of different processor notes; When the processor node for Initial connection indicated by arrow 70 extending from a flip-flop such as knob 46 The device in Figure 1 signals the next processor note to send. originates from the immediately adjacent node, but this does not necessarily mean that the actual It is not intended to indicate what would occur in a server node array. Others due to mediation process A certain transmission order may be determined.

The transmitted signal is connected to other operations performed on the array by controller 24. Arbitration and transmission occur only when asserted to allow synchronization. sequential, large Several modes of arbitration/data transfer, such as area and direct, are implemented in the architecture. given. Controller 24 and flip 70 tube 46.48.5 sail 52 is the point in processor operation when the signal is sent from the output processor note. 1° sequential mode including what is referred to in the text as an arbitration means operable to determine the The control bus 26- (which means that two side control signals are connected to one processor) request to move from one processor node to the next processor node.

Entry arbitration enables Ijf transmission from all processor nodes, but Uses a signal traveling on a control bus to daisy-chain the sarnodes. , that a processor node sends through which other processor nodes pass By observing the stomach.

Direct arbitration, the data goes to the arbitration output buffer:! Immediately after F is inserted, the next transfer is 1? sa It is used in situations where it is sent to the output bus at the same time as the cycle. .

In a SIMD structure, one instruction can cause the control bus 261 to Pass through to the node. This instruction is simultaneously input on the input bus 20 It is performed on the values present in M processor notes. Each output buffer is , its own internal controllers, shown at 38a, 40a, 42a, 44a in FIG. This is how each output processor is separated from the SIMD controller 24. Described below are the coats and structures that explain how they work.

In conventional architectures, outputs are routed on output bus 22 to individual processor nodes. It is sent from the card in a predetermined transmission sequence. This is II! (A new life Instruction sets or new data can be received in the processor notebook before any other processor node in the array has finished transmitting. 1, providing an output buffer 7 for each PN requires a node to wait. Processing data is stored while the processor node waits for its turn on the output bus. provide a place to A different behavior may occur at the processor node, which is a new new data is loaded, or existing data is manipulated by a new instruction set. made.

Line 28 indicates that output data from one processor node or other processor nodes. If so, you can enable it. This enablement is similar to traditional microphones. 2, which is shown schematically in FIG. .

The actual operation of the individual processors in array 10 is explained by software personnel. a physical design of an integrated circuit provided in numbers but including an output processor node of the present invention; 1゜ The code below is written by the following instruction set that is incorporated into the neuron Code describing the actual CMO3 configuration of the PN structure in a computer chip This is a simplification of The code shown below is modified by some predefined macro. 1 in the C programming language, which is written in the C programming language. The 91 emphasis character used as the description language of the register transfer level in the configuration is Significance j, /S-toe r or 1/7-l, sea r element, or phase or or clock cycle.

The variables pht and ph2 are used to realize a dynamic MOS device. The two phases of the two non-overlapping clocks are mutually exclusive. taste, r BJ means bus (more than 1 signal line), "-1" is only available during phi. means a valid dynamic signal. 1 These can be arbitrarily combined.

. Output unit (0bUNIT) (i8 is a PNN output buffer including an output buffer. Buffer interfaces are used for output and allow output to run independently of input. 1 used during various recursive and feedback operations. ゜if　(reseL)tuuLsL=o;seqrght=0;obarmd =0: seqgo ID=0; 1 This step initializes the variables used during processing. During arbitration of the output buffer to the output bus, the output from the leftmost PN The arbitration signal is a sequential arbitration OK signal, and 1efff is the main text in PN12 on the left. The signal from flip 70 knob 46, also referred to as arbitration signal generator means, is 1°, which is transmitted by PN12 and indicates that it is now PN14's turn. When output buffer 7 is written, 0b a, rmd flip 70 knob 46 is set. be done. Ob armd indicates that the output buffer is secured and ready for transmission. vinegar.

This transmission is done independently of the rest of the calculations inside the PN, and our output buffer Forms the core of the architecture.

If the transmission is 2 bytes, the lower byte is sent first. This is a sending system. Occurs when the PN control is asserted and the PN's output buffer is protected. This is 2 bytes sent 0utst flip 70 is used to indicate the second of 1, this All the arbitration rJI specifications described above work in sequential mode 1-, where I'N A. When you complete 1, send a signal to the person on your right. , xm i, t: is (arbitration Shinkyu' If you receive a SIM card that notifies you that it will be sent to a specific PN I) It is a directive. , 5cc4c, and trb flip 70 knobs have this arbitration mode. f) utmd2 recognizes that this is a 2-byte transmission. 4゜i　f((+)hl)ANDb((+revised md)ANDb(x劃[ ))(if(scqarb)( ir (nuLSL-1) i oul, bus [32 ((+uLbur E IAND 0xFFQOL)>>8+ (ILILsL-0; (city+irmd O; scqrg skin l.

The previous sequence executes the 0utbuf state manmoon for sequential arbitration.

. seclrght els signals the next PN to transmit on the next clock e if (scqgo II)) lif (ouLmd2) 1 After all PNs have transmitted on the output bus 22, the arbitration protocol is reset and System t is interrogated to determine whether there are any more outputs to come, 1, i.e. 1r (reSet) obar+++d=0; (city ariid=1; 1 if ((ph2) ANDb (vcvul) ANDb (rgctl B 2==F RGBBIIS) ANDb(r B=F-OLITBLIF)) tnbunmd=l; 1 If the output buffer has information to be sent, Obarmd is set. 1, vCval indicates the valid output buffer control signal. , a write to register 7 0UTBUF indicates that c) sets barmd; This is the 7 array 10 architecture that turns on (enables) the PN output buffer. The operation of the camera can be summarized in the following four ways. .

That is, Clock 0 period Initially, CN01CNI, CN2 and CN3 are respectively processor nodes. It has the value stored in register 62 of 12.14.16.18. These values are is written to each output buffer in each PN on the appropriate line.

Clock 1 period: An output bus 7a 38 in the processor node 12 transfers the output of the CNO to an output bus. Send to 22. This value is set by processor node 12.14.16.18 on line 2. 8 and input bus 20. Each processor note is a weighted note The weights are extracted from the Lee unit 66 and applied to the output of the CNO, for example, W, w%, . Multiply by various weights such as w6° and W7o. Then, the output buffer 738 and and processor node 12 receive an arbitration signal on output bus 22 that it may transmit all. Flip signal 70 via tube 47 and line 70 to the next processor node. to output buffer 740 at processor node 14.

Clock 2 period: Output buffer 40 in processor node 14 connects the output of CNI to an output bus. Send to 22. This value is sent to the processor node via line 28 and human power bus 20. Read by 12.14.16.18. Each processor note is a weighted note Take out the IR signal from the Lee unit 66 and apply it to the output of CN0, for example, W4. ,W, 1, W81 and W71 are multiplied by various nails. 7 Then the output buffer 40 and processor note 14 are connected by flip 70 knob 48 and line 70. The output buffer 42 in the processor notebook 16 indicates that it is OK to send the data now. signal.

Similar operations occur during successive clock cycles until the data is processed. Ru1, Another way to examine processor node functionality is that each processor node 0, addition unit 58 and two index tables, oil bug a) response generation unit 64 and weighted memory 66. , each node requires human power 3. Receive and perform multiplication-accumulation for each clock. After the cumulative loop, each processor The node moves its output to its output buffer and waits for its return for routing.

This step can be expressed as shown below. That is, i=1 Therefore, the output 01 is the value WII drawn from the weighted memory 66 multiplied by the human power value 01. where all functions are stored in the weighted address generation unit 64. It will be done.

Having disclosed preferred embodiments of the invention, the present invention as set forth in the claims. It will be understood that changes and modifications may be made without departing from the scope.

Industrial applicability A processor configured according to the present invention analyzes various functions of the human brain and makes decisions. Neural network systems that can be used to simulate Effective in stems.

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Claims (1)

[Claims] 1. An input bus (20), an input unit (54), and an operation unit (56 to 66) ) and an output bus (22). Output processors at SIMD processor nodes (12, 14, 16, 18) In processor architecture, an output for receiving data from the input unit (54) and the operating unit (56-66); a force unit (68); located at the selection processor node (12) and selected from the output unit (68). an output buffer (38) that stores and sends data at the point in time, and a processor node. between the board (12), the output buffer (38) and the output unit (68). and a control unit (56) for controlling data exchange between the architecture. 2. At what point in the operation of the processor is a signal sent out from the output buffer (38)? 2. The apparatus according to claim 1, further comprising arbitration means (46) for determining the architecture. 3. Said arbitration means is arranged in each processor node (12) to determine the next processor. Arbitration signal generator (46) that generates control signals for the server node (14) 3. The architecture of claim 2, further comprising: 4. Each output buffer has a data storage ordering and an output bus (22). and a separate internal controller (38a) for controlling subsequent transmission. 2. The architecture of claim 1. 5. Includes multiple connection nodes (30, 34) located within each processor node. If the connection node is configured to perform n2 connections in n clocks, The architecture of claim 1, characterized in that: 6. During each clock, a selected connection node (30) All selected nodes (34, 35, 36, 37) connected via the service node The architecture according to claim 5, characterized in that broadcasting is performed for sets. 7. An input bus (20), an input unit (54), and an operation unit (58 to 66) ) and an output bus (22). Output processors at SIMD processor nodes (12, 14, 16, 18) In processor architecture, Outputs for receiving data from the input unit (54) and the operating units (58-66) a force unit (68); located at the selected processor node (12) to output the output unit at the selected time. (68), an output buffer (38) for storing and transmitting data from the processor; - Node (12) and associated output buffer (38) and output unit (68) a control unit (56) for controlling the exchange of data between each processor node; the next processor node (14). Arbitration signal generator (46) that generates a signal instructing the processor node to transmit and An architecture characterized by the provision of. 8. Each output buffer (38) provides data storage ordering and an output bus (22). a separate internal controller (38a) for controlling subsequent transmission to the 8. The architecture of claim 7, wherein the architecture comprises: 9. A plurality of connection nodes (30, 3) located within each processor node (12) 4), and the connection node is configured to perform n2 connections in n clocks. 8. The architecture of claim 7, wherein: 10. During each clock, the selected connection node (30) All selected nodes (34, 35, 36, 37) connected via the server node 10. The architecture of claim 9, wherein said architecture broadcasts to said set.