JPH0547197A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device capable of utilizing effectively a normal memory cell in a memory cell array even when a defective memory cell is present. CONSTITUTION:A defective position storing means 11 storing the positional information of the defective memory cell in the memory cell array is provided with plural first pads 11A0-11A9 and plural second pads 11A00-11A09 and the address of the defective memory cell is stored by whether spaces between the first pads and the second pads are connected with wires at every bit. In a defective position detecting means 12 inputted with the selecting signal of an H level to a select input end SEL and activated, the address inputted to first input ends A0-A9 and the positional information from the defective position storing means 11 inputted to second input ends B0-B9 are compared at every one bit, when all the bits are coincident, a coincidence signal is outputted to an output end A=B and the positional information of the defective memory cell is informed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a memory cell array having a plurality of memory cells is provided in a semiconductor chip, and more particularly to a semiconductor integrated circuit device having a defective memory cell in the memory cell array. The present invention relates to a semiconductor integrated circuit device in which the position of a defective memory cell can be seen from outside the semiconductor chip.

[0002]

2. Description of the Related Art FIG. 5 is a plan view of a 1M DRAM which is a kind of conventional semiconductor integrated circuit device.
In particular, the arrangement of terminals will be described. In FIG. 5, the first terminal is the data input terminal D, the second terminal is the write control input terminal W bar, the third terminal is the row address strobe input terminal RAS bar, and the fourth terminal. And terminal 5 is the last used terminal N
C, 9th to 12th terminals are address input terminals A _{0 to} A ₃ terminals, 13th terminal is a power supply terminal Vcc, 14th to 18th and 22nd terminals are address input terminals, and 23th terminal is an end-use terminal, The 24th terminal is the column address strobe input terminal C
AS bar, the 25th terminal is a data output terminal Q, and the 26th terminal is a ground terminal Vss.

In such a semiconductor integrated circuit device, the semiconductor chip has a structure as shown in FIG. 6, in which 1 is a semiconductor chip and 2 is a row and a column. A plurality of memory cells arranged in a matrix, word lines connected to the memory cells arranged in each row of the plurality of memory cells, and memory cells arranged in each column of the plurality of memory cells, respectively. A memory cell array 3 having connected bit lines is a sense refresh amplifier input / output control means which is connected to the bit line pair in the memory cell array and amplifies and outputs the potential difference appearing in the connected bit line pair. ..

Reference numeral 4 is the row address strobe input terminal R.
A row address strobe input pad and a column address strobe input terminal CA connected to the AS bar by a wire.
The column address strobe input pad, which is connected to the S bar by wire, is connected to the input RAS bar signal and C
Internal RAS bar signal and internal C based on AS bar signal
A clock generating means 5 for outputting an internal control signal such as an AS bar signal is a row decoder for selecting one of the word lines in the memory cell array 2, and is activated by an internal control signal from the clock generating means 4. Be converted. A column decoder 6 for selecting one of the bit line pairs in the memory cell array 2 is activated by an internal control signal from the clock generating means 4.

Reference numeral 7 denotes an address input means connected to an address input pad connected to the address input terminals A _{0 to} A ₉ by a wire. The address input means 7 is activated by an internal control signal from the clock generating means 4 and is inputted. Multiplexing means for multiplexing row and column address signals, a row address buffer for temporarily latching the row address signal and outputting the row address signal to the row decoder 5, and a row address buffer for temporarily latching the column address signal, and the column decoder. 6 has a column address buffer for outputting a column address signal. Reference numeral 8 is connected to a read / write designation input pad connected to the write control input terminal W bar by a wire to input a read / write signal, and
It is a logic means which receives the internal control signal from the clock generating means 4 and outputs a read / write control signal.

Reference numeral 9 is connected to a data input pad connected to the data input terminal D by a wire, temporarily latches the input data, and is activated by a read / write control signal from the logic means 8 ( The controlled and input data is passed through the sense refresh amplifier input / output control means 3 to the row and column decoders 5 and 6
Input means 10 for writing to the memory cells in the memory cell array 2 selected by the memory cell array 2 selected by the row and column decoders 5 and 6.
The data read from the memory cell in the memory is input through the sense refresh amplifier input / output control means 3 and the input data is temporarily latched.
The output means is activated (controlled) by a read / write control signal from the logic means 8 and outputs the input data to a data output pad connected to the data output terminal Q by a wire.

Next, the operation of the semiconductor integrated circuit device thus configured, particularly the read cycle, will be described. First, the input means 9 is deactivated by the read / write control signal from the logic means 8 which receives the read / write signal input from the write control input terminal W bar and the read / write designation input pad. Until then, the output means 10 is activated. Then, the RAS bar signal is input to the clock generating means 4 via the row address strobe input terminal RAS bar and the row address strobe input pad, and the internal RAS from the clock generating means 4 is inputted.
When the bar signal falls, the address input means 7 latches the row address signal input to the address input terminals A _{0 to} A ₉ and the address input pad, and outputs it to the row decoder 5.

The row decoder 5 selects a word line in the memory cell array 2 based on the input row address signal, and the data stored in the memory cell connected to the selected word line is read out to the bit line. , Sense-frisch amplifier is amplified by the input / output control means 3. Further, the CAS bar signal is input to the clock generating means 4 via the column address strobe input terminal CAS bar and the column address strobe input pad, and the fall of the internal CAS bar signal from the clock generating means 4 causes
The address input means 7 latches the column address signal input to the address input terminals A _{0 to} A ₉ and the address input pad and outputs it to the column decoder 6.

The column decoder 6 selects a bit line in the memory cell array 2 based on the input column address signal, the data is read out to the selected bit line, and the data amplified by the sense refresh amplifier input / output control means 3 is selected. Will be output from the output means 10, the data output pad and the data output terminal.

The semiconductor integrated circuit device having the above structure is manufactured by the manufacturing process shown in FIG. That is, as shown in step S1, first, a large number of semiconductor chips 1 shown in FIG. 6 are formed on a wafer by the wafer manufacturing process. Then, in step S2, all the memory cells in the memory cell array 2 are inspected for each semiconductor chip 1 on the wafer. If all the memory cells are normal, the process proceeds to step S3 to perform dicing, wire bonding, resin molding, etc. The assembling process is performed, and the process proceeds to step S4. The inspection is performed again in step S4, and if the inspection is acceptable, the product is shipped, and if the inspection is not accepted, the product is discarded. In the inspection in step S2, if even one memory cell in the memory cell array 2 has a defect, it is discarded as a chip.

In the semiconductor integrated circuit device configured as described above, for example, in a 1M DRAM, more than 1 million memory cells are provided, and even one of them is defective. If it exists, it is discarded and the yield is poor.
As disclosed in Japanese Patent No. 4864 or Japanese Patent Application Laid-Open No. 63-124299, one or a plurality of spare memory cell columns are formed in the semiconductor chip 1 separately from the memory cell array, and a defective memory cell array 2 It has been proposed to replace a memory cell column having a defective memory cell with a spare memory cell column to repair the defect when the memory cell exists.

However, in the semiconductor integrated circuit device shown in FIGS. 5 and 6, if there is at least one defective memory cell in the memory cell array 2, it is discarded and therefore the yield is low, and the spare cell is also spared. In a semiconductor integrated circuit device including a memory cell array, the yield is improved,
If there are more defective memory cells in the memory cell array than the prepared spare memory cell columns, they will be discarded and it is necessary to form a large number of spare memory cell columns in order to improve the yield. However, there is a limit to the number of defects that can be formed, and the larger the number, the more complicated the defect relief circuit becomes.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is possible to make a normal memory cell in a memory cell array effective even if a defective memory cell exists in the memory cell array. It is an object of the present invention to obtain a semiconductor integrated circuit device that can be used for.

[0014]

A semiconductor integrated circuit device according to the present invention includes a memory cell array having a plurality of memory cells formed in a semiconductor chip, and a defective memory cell provided in the semiconductor chip. Defect position storage means for storing the position information in, the position information input to the semiconductor chip provided in the semiconductor chip, and the defect position information from the defect position storage means is input,
Defect position detecting means is provided for outputting the coincidence information when the two pieces of position information coincide with each other.

[0015]

According to the present invention, the defect position detecting means outputs coincidence information when the input position information and the defect position information from the defect position storing means match, and the input position information is stored in the memory cell array. The position information of the defective memory cell is shown from the outside of the semiconductor integrated circuit device.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a plan external view of a 1M DRAM which is a type of semiconductor integrated circuit device, and is different from the conventional semiconductor integrated circuit device shown in FIG.
The 5th terminal, which was the last used terminal, is used as a select input terminal SELECT to which an H-level select signal is input at the time of inspection, and the 23rd terminal, which is the last used terminal, is set to the position of the defective memory cell at the time of inspection. The terminal arrangement is different in that it is used as a match signal output terminal A = B for outputting a match signal of H level when the address shown is input.

In such a semiconductor integrated circuit device, the semiconductor chip has a structure as shown in FIG. 2, and the same symbols as those shown in FIG. 6 in FIG. 11 shows a corresponding portion, and 11 is a defect position storage means which is provided in the semiconductor chip 1 and stores the position information in the defective memory cells in the memory cell array 2. In this embodiment, one defective memory cell is provided. On the other hand, as shown in FIG. 3, a plurality of first pads 11A _{0 to} 11A ₉ and a plurality of second pads 11A _{00 to} 11A.
_09, and when 1 bit of the address of the defective memory cell indicates “0”, the corresponding first pad and second pad are connected by a wire, and 1 bit of the address of the defective memory cell is connected. When "1" indicates "1," the corresponding first pad and second pad are left open, and the address of the defective memory cell, that is, the position information is stored. A plurality of those shown are formed.

Reference numeral 12 is provided in the semiconductor chip 1, and the position information input to the semiconductor chip 1 and the defect position information from the defect position storage means 11 are input, and when the both position information match, the matching information is output. in the defect position detection means, the first input terminal a ₀ to a _9, which is connected to the address input pads a ₀ to a _9, as shown in FIG. 3 for one defective memory cell in this embodiment, the defect Second position detecting means 11
Second input terminals B _{0 to} B ₉ connected to the pads, and select input terminals SEL connected to the select input pads connected to the select input terminals SELECT via wires.
And an output end A = B connected to the coincidence signal output pad connected to the coincidence signal output terminal A = B by a wire, and an H level select signal is input to the select input end SEL. Are activated by the first input terminals A _{0 to} A ₉
The address input to the second input terminal B ₀ to the position information from the defect position storage means 11 input to the second input terminals B ₉ are compared bit by bit, and when all the bits match, a match signal is output. A = B is output, and a plurality of those shown in FIG. 3 are formed.

The semiconductor integrated circuit device thus constructed is manufactured by the manufacturing process shown in FIG. That is, as shown in step S1, first, a large number of semiconductor chips 1 shown in FIG. 2 are formed on a wafer by a wafer manufacturing process. Then, in step S2, all the memory cells in the memory cell array 2 are inspected for each semiconductor chip 1 on the wafer. If all the memory cells are normal, step S2 is performed.
3, the assembling process such as dicing, wire bonding, and resin molding is performed, and the process proceeds to step S4. The inspection is performed again in step S4, and if the inspection is acceptable, the product is shipped, and if the inspection is not accepted, the product is discarded.

If there is a defective memory cell in the memory cell array 2 in the inspection in step S2, the process proceeds to step S6, and the number (size) of defective memory cells in the memory cell array 2 and the position information of the defective memory cells (in this embodiment, in this embodiment). Column address). If the number of defective memory cells is larger than the number that can be stored in the defective position storage means 11, it is considered to be discarded, and if it is smaller, step S7.
Proceed to. In this step S7, assembling is performed in the same manner as in step S3, and during wire bonding, the first pads 11A ₀ to 1A in the defect position storage means 11 are further based on the address of the defective memory cell.
Wire connection between 1A ₉ and the second pads 11A _{00 to} 11A _09, and wire connection between the coincidence output terminal A = B and the coincidence output pad and between the select input terminal SELECT and the select input pad are performed. Be seen. After that, the process proceeds to step S8, and the inspection is performed again as in step S5. If the result is acceptable, the product is shipped, and if it is not acceptable, the product is discarded.

The read and write operations of the semiconductor integrated circuit device configured as described above are substantially the same as those of the conventional semiconductor integrated circuit device shown in FIGS. 5 and 6, but this semiconductor integrated circuit device is the same. Before using the device, it is necessary to detect whether there is a defective memory cell in the memory cell array 2 and, if there is a defective memory cell, obtain the position information of the defective memory cell.
The position information of this defective memory cell is obtained as follows. First, select input terminal SELECT to H
When the level select signal is input, the defect position detecting means 12 is activated.

When the column address signals are sequentially input from the address input terminals A _{0 to} A ₉ , the defect position detecting means 12
Then, the inputted column address signal is compared with the column address of the defective memory cell stored in the defective position storage means 11, and if they coincide with each other, an H level signal is outputted from the output end, and the coincidence signal output terminal A = B is outputted. A match signal is output, and the column address input to the address input terminals A _{0 to} A ₉ when this match signal is output indicates the column address of the defective memory cell.

Therefore, in the read and write operations in the semiconductor integrated circuit device, since the column address of the defective memory cell is known, the memory cell existing at this column address is not used. It is only necessary to skip the column address in which the data exists and read the data from the memory cell in the memory cell array 2 or write the data to the memory cell.

In the above embodiment, the defective position storage means 11 stores the column address of the defective memory cell, but it may store the row address, and the column address may be stored. Both the address and the row address may be stored. In the case of storing both the column address and the row address, since only the defective memory cell can be prevented from being used, all the normal memory cells can be effectively used.

Further, in the above-mentioned embodiment, the one using no spare memory cell column is shown, but it may be applied to the one using the spare memory cell column. When applied to the one using the spare memory cell column, if the number of defective memory cells can be relieved only by the spare memory cell column, the spare memory cell column is used for remedy, and the number of defective memory cells is equal to or larger than the spare memory cell column. If there is, the defect position storage means 11 stores the position information of the defective memory cell that cannot be repaired by the spare memory cell column.
The defective memory cell may be stored in the memory so that the defective memory cell is not used.

[0026]

As described above, according to the present invention, the defect position storage means, which is provided in the semiconductor chip and stores the position information of the defective memory cell in the memory cell array, is provided in the semiconductor chip. Since the position information input to the chip and the defect position information from the defect position storage unit are input and the defect position detection unit that outputs the matching information when both position information match is provided, the defective memory cell of the defective memory cell The position information can be known from the outside of the semiconductor integrated circuit device, and a normal memory cell can be effectively used without using a defective memory cell.

[Brief description of drawings]

FIG. 1 is an external plan view showing an embodiment of the present invention.

FIG. 2 is a block diagram in a semiconductor chip showing an embodiment of the present invention.

FIG. 3 is a block diagram showing a defect position storage means 11 and a defect position detection means 12 in an embodiment of the present invention.

FIG. 4 is a flowchart showing a manufacturing process of an embodiment of the present invention.

FIG. 5 is an external plan view showing a conventional semiconductor integrated circuit device.

FIG. 6 is a block diagram in a semiconductor chip showing a conventional semiconductor integrated circuit device.

FIG. 7 is a flowchart showing manufacturing steps of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1 Semiconductor Chip 2 Memory Cell Array 11 Defect Position Storage Means 12 Defect Position Detection Means

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/82 27/10 481 8728-4M

Claims (1)

[Claims] 1. A memory cell array having a plurality of memory cells formed in a semiconductor chip, defect position storage means provided in the semiconductor chip for storing position information of defective memory cells in the memory cell array, and the semiconductor. A semiconductor provided in a chip and provided with defect position detection means for inputting position information input to the semiconductor chip and defect position information from the defect position storage means and outputting coincidence information when both position information match. Integrated circuit device.