JPH0546747A - Method for setting up binarizing threshold - Google Patents

Abstract

PURPOSE:To set up an optimum binarizing threshold to obtain a binary image of a wiring pattern formed on a printed substrate. CONSTITUTION:Reflected light information and transmitted light information are electrically converted and digitized through A/D conversion parts 210, 220 as a printed substrate signal PS and a hole signal HS. The signal HS is binarized by a binarizing processing part 240 and delayed by a phase compensating part 280 as a delayed hole signal HDS. Both signals PS, HDS are logically synthesized by a masking processing part 230 and the value of the signal PS corresponding to a position on which the signal HDS is '1' is set up to '0' to obtain a compensated signal CS. A histogram forming part 250 forms a histogram G by using the signal CS, a binarizing threshold T is set up based upon the histogram G and a binarizing circuit 270 binarizes the signal PS. Consequently the information of a position on which light is reflected by a stage through a through hole is forcedly set up to a prescribed value and the position of masking processing can be accurately determined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of setting a threshold value, which is used in a wiring pattern inspection of a printed circuit board and which binarizes a board signal obtained by reading the wiring pattern.

[0002]

2. Description of the Related Art In the inspection of a printed circuit board, an image obtained by binarizing a wiring pattern by image processing is often obtained, and various inspections are performed on the image. In this binarization process, a method of determining an appropriate binarization threshold value is particularly important. For the determination of the binarization threshold,
Many methods have been proposed so far. For example, a method may be adopted in which the number of pixels in the grayscale image is obtained as a frequency distribution for each gradation value, and the gradation value having the minimum frequency is determined as a binarization threshold.

FIG. 8A shows an example thereof,
In the wiring pattern inspection of the printed circuit board, the intensity of light reflected from the board is converted into a signal having a gradation value of 8 bits, and the frequency distribution with respect to the gradation value of the pixel is examined (histogram). The hills appearing on the side with a high gradation value indicate the existence of a wiring pattern with a high reflection intensity, and the hills appearing on the side with a low gradation value indicate the presence of through holes (through holes) and a base material with a low reflection intensity. .. When it is desired to obtain binary data of the wiring pattern, the gradation value T ₁ having a small frequency of reflection intensity is adopted as the binarization threshold value.

[0004]

However, as will be described later, since the wiring pattern is inspected also by using the light transmitted through the through holes of the substrate, the substrate is mounted on a transparent stage such as glass. Are often inspected. In such a case, not only from the substrate but also in a portion where the substrate is not placed or through the through hole of the substrate,
Light may be reflected by the stage.

Reflection by this stage produces reflected light of a certain intensity, though not to the extent of the wiring pattern, so that as shown in FIG. 8 (b), a parasitic peak is observed in the curve of FIG. 8 (a). (The broken line indicates the curve in FIG. 8A). Then, the gradation value having a small frequency of the reflection intensity becomes T ₂ , which is larger than the gradation value T _{1 which} should be originally set as the binarization threshold value, and the binarization of the image of the wiring pattern on the substrate is optimized. There was a problem that I could not do it.

Further, due to the structure of the reading means, the pattern image data read using reflected light and the hole image data read using transmitted light are out of phase with each other.

The present invention has been made to solve the above problems, and an object thereof is to obtain an optimum binarization threshold value.

[0008]

A method of setting a binarization threshold value according to the present invention comprises: (a) a substrate having first and second main surfaces and a through hole and having a relatively low reflectance and a light shielding property. Further, a substrate having a pattern having a relatively high reflectance on the first main surface is placed on a stage having translucency, and (b) a first light source to the first main surface. Is irradiated with the first light, the intensity of the reflected light reflected by the first main surface is converted into an electric signal, and a substrate signal showing an image of the first main surface is obtained, and (c). The intensity of the transmitted light of the second light, which is obtained by irradiating the second main surface with the second light from the second light source and passing through the region of the stage where the substrate is not placed and the through hole. Is converted into an electric signal to obtain a hole signal showing an image of the region and the through hole, and (d) the Obtaining a binary Hall signal by binarizing the Le signal. Furthermore, (e) the binarized Hall signal is delayed by a predetermined amount to obtain a delayed Hall signal, and (f) the substrate signal and the delayed Hall signal are logically combined, and the delayed Hall signal A correction signal obtained by masking the substrate signal is obtained. Then, (g) a histogram relating to the reflection intensity of the first principal surface is created from the correction signal, and (h)
A binarization threshold value for binarizing the substrate signal is set from the histogram.

Preferably, (b) and (c) are performed by a plurality of reading means, and the predetermined amount of delay in (e) is set for each reading means.

[0010]

In the present invention, the delay hole signal is used to mask the effect of the light reflected in the region of the stage where the substrate is not mounted and the through hole on the substrate signal to generate a correction signal. By creating a histogram using this correction signal, it is possible to obtain a binarization threshold that is almost the same as when there is no light reflected from the stage.

Further, since the delay Hall signal is binarized, it can be easily delayed by a predetermined amount, and the correction signal can be generated in phase with the substrate signal.

[0012]

【Example】

A. Generation of Substrate Image and Hole Image FIG. 2 is a schematic diagram of an optical wiring pattern reader 100 used in an embodiment of the present invention.

The reading device 100 includes red LEDs 111, 1
1st light source 110 consisting of 12 and 113, infrared LED
A (second light source) 120, a lens system 140, a cold mirror 150, a reflected light image sensor 161, and a transmitted light image sensor 162 are provided.

On the other hand, the translucent stage 15 on which the substrate 20 to be inspected is placed is interposed in the reading device 100. The stage 15 moves in forward and reverse directions in two directions orthogonal to each other in a plane parallel to itself, so that the reading device 100 can read the entire upper surface of the substrate 20 placed on the stage 15. ..

This will be described with reference to FIG. 3, which is a schematic plan view. The stage 15 can be moved in the sub-scanning direction (± Y direction), and the printed circuit board 20 can be relatively scanned and read by the reading 100.

When a plurality of reading devices 100 are provided, it is difficult to provide them adjacent to each other without a gap, and they are located apart from each other as shown in the drawing. Further, when the number of the reading device 100 is one, the entire surface of the printed circuit board 20 cannot be read by one scanning. Therefore, regardless of whether the number of the reading devices 100 is one or plural, when it is desired to obtain the substrate signal PS ₀ over the entire surface of the printed circuit board 20, the scanning signal is once scanned in the + Y direction (or −Y direction). After the forward scanning, the stage 15 is moved in the main scanning direction (± X direction). Then, scanning is performed in the -Y direction (or + Y direction) (reverse scanning), and an area that cannot be read by the forward scanning is read. In FIG. 3, the relative strokes read by the third reading device 100 from the right are illustrated by arrows.

Returning to FIG. 2, the light emitted from the first light source 110 is reflected by the wiring pattern 22 and the base material 21 formed on the first main surface of the substrate 20, passes through the lens system 140, and is cold. Reach the mirror 150. Cold mirror 15
0 transmits infrared light but does not transmit red light, so
The light reflected by the first main surface side of the substrate 20 is further reflected by the cold mirror 150 and enters the reflected light image sensor 161 as reflected light LR. Image sensor for reflected light 1
Reference numeral 61 converts the intensity of the reflected light LR into a substrate signal PS ₀ which is an electrical signal.

On the other hand, the light emitted from the second light source 120 located on the second main surface side of the substrate 20 passes from the back surface 15a of the stage 15 to the front surface 15b, and the through hole (through hole) 25 provided in the substrate 20. The lens system 1 through the substrate or from an area (not shown) on which the substrate 20 is not placed.
Reaching 40. This light is infrared light and cold mirror 1
After passing through 50, it becomes the transmitted light LT and enters the transmitted light image sensor 162. The transmitted light image sensor 162 is
The intensity of the transmitted light LT is the Hall signal HS which is an electrical signal.
Convert to ₀ . The substrate signal PS ₀ and the hole signal HS ₀ are used to detect the wiring pattern 22 and the through hole 25, respectively.

However, the substrate signal PS ₀ and the hall signal HS
₀ means that the same place is not always detected on the printed circuit board to be inspected. Image sensor 16
Due to the mounting error of 1, 162, a certain reading device 100
In this case, the substrate signal PS ₀ may precede the hall signal HS ₀ (prefetch information in the direction opposite to the stage moving direction). Further, in the other reading device 100, the hall signal HS ₀
May precede the substrate signal PS ₀ . Which one precedes is also reversed depending on whether the stage 15 is forward or reverse in the sub-scanning direction, that is, forward scanning or backward scanning.

B. Generation of Correction Image FIG. 1 shows a pattern 2 used in one embodiment of the present invention.
3 is a block diagram of a binarization processing unit 200. FIG. The pattern binarization processing unit 200 generates a signal PIS that binarizes the image of the substrate using an optimal binarization threshold based on the substrate signal PS ₀ and the Hall signal HS ₀ obtained from the reading device 100. To do. The signal PIS is then subjected to a pattern break inspection or the like depending on the purpose.

The A / D converters 210 and 220 A / D-convert the board signal PS ₀ and the hall signal HS ₀ , respectively, and digitize the board which is a digital signal having a gradation value of 8 bits (= 256), for example. The signal PS and the digitized Hall signal HS are obtained.

The substrate signal PS is supplied to the mask processing sections 230 and 2
It is sent to the digitization circuit 270. In the binarization circuit 270,
The substrate signal PS is binarized by the optimum binarization threshold value T obtained as described later to generate the signal PIS.

The hall signal HS is binarized by the binarization processing unit 240 to be a binarized hall signal HIS. This signal HIS is an image P created by the substrate signal PS.
The hole portion H of I is designated and distinguished from the other non-hole portions NH (FIG. 4). As will be described later in detail, in the mask processing section 230, the hole portion H of the substrate signal PS is
By setting the portion corresponding to the predetermined value to a predetermined value, an unnecessary signal in the portion where the substrate 20 is not mounted or the portion where the light is reflected by the stage 15 through the through hole 25 of the substrate 20. To remove the correction signal C
S can be generated.

Now, in the reading device 100, the hall signal HS is generated due to an attachment error of the image sensors 161 and 162.
₀ preceding the substrate signal PS ₀ (reader 10
When 0 is singular, consider the case of scanning in such a direction). The substrate signal PS ₀ to be masked is delayed from the Hall signal HS ₀ , and even if the binarized Hall signal HIS is sent to the mask processing unit 230 as it is, the portion of the substrate signal PS to be masked is correct. Not masked. Therefore, the binarized Hall signal HIS
Is sent to the phase correction unit 280 once and becomes a delayed Hall signal HDS whose phase is matched with the substrate signal PS, and then sent to the mask processing unit 230. The phase amount to be delayed in the phase correction unit 280 can be easily set for each reading device 100 by measuring the attachment error in advance.

On the other hand, in the reader 100, the board signal P
If S ₀ precedes the Hall signal HS ₀ (when the reading device 100 is singular and scans in such a direction), the delayed Hall signal HDS is not generated. This is because it is not possible to match the phase with the substrate signal PS even with the delay. In this case, the mask processing unit 230 also does not generate the correction signal CS.

As described above, which of the substrate signal PS and the hall signal HS precedes, that is, whether or not the correction signal CS is generated depends on whether the stage 15 moves in the reverse direction. To do.

The histogram creating section 250 creates a histogram G by plotting the pixel frequency for each gradation value from the correction signal CS. The binarization threshold setting unit 260 obtains a gradation value T having the minimum frequency based on the histogram G, and sets it as a binarization threshold.

Next, the operation of the processing units 230 and 240 will be described in detail. First, the binarization processing unit 240 binarizes the hall signal HS using a certain threshold value TH _h . A region having a value equal to or greater than the threshold value TH _h is determined to be the hole portion H, and the other portion is determined to be the non-hole portion NH (the hole portion H is not only the portion corresponding to the through hole 25, but also the substrate). The area on the stage 15 where the 20 is not mounted is also included.). FIG. 4 shows the relation between the Hall signal HS read on the line AA ′ and the substrate 20.

FIG. 5 shows the relationship between the substrate signal PS and the substrate 20,
It is shown similarly to FIG. Through hole 25
There is a reflection signal RF due to the reflection of light by the stage 15 corresponding to the position of. Such reflected signal RF
Is caused by the front surface 15b and the back surface 15a of the first light source 110, and therefore occurs in a region where there is no light shielding on the stage 15, that is, in a region determined to be the hole portion H. Therefore, the delayed hall signal HDS having the information indicating whether the attention place is the hole portion H or the non-hole portion NH is the reflected signal R
The area where F occurs can be masked.

Specifically, for example, in the mask processing section 230, the AND of the substrate signal PS and the inverted signal of the delay Hall signal HDS may be taken. In such a case, the mask processing unit 230 can be configured only by including the AND circuit 231 as shown in FIG. The value of the signal corresponding to the hole portion H in the correction signal CS becomes “0”, and a signal indicating the wiring pattern 22 in which the influence of the reflection signal RF is suppressed can be obtained.

In the correction signal CS, the value of the signal corresponding to the hole portion H is not limited to "0", and may be another value that makes it easy to determine the binarization threshold value T from the histogram G generated later. You can also do so. In this case, a predetermined value (corresponding to the gradation value) is output only when the delayed hall signal HDS is "1" (corresponding to the hall portion H) and "0" (corresponding to the non-hall portion NH). In the case of), the mask processing section 230 can be configured using a multiplexer that outputs the substrate signal PS.

C. Generation of Histogram and Setting of Threshold for Binarization FIG. 7 shows a histogram G of reflection intensity when the value of the correction signal CS at the hole portion H is set to T ₃ . Such a histogram G is obtained by counting the distribution of the frequency of the reflection intensity for each gradation value. Since the gradation value in the hole portion H is set to T ₃ , the histogram G shows the gradation value T
₃ has one peak, but if the gradation value T ₃ is kept sufficiently small, the shape of the histogram in the vicinity of the gradation value T ₁ is not affected, and as shown in FIG. A gradation value T ₁ ′ which is almost equal to the gradation value (binarization threshold value) T ₁ set for an ideal histogram can be set as the binarization threshold value.

In many cases, the histogram G is not necessarily created over the entire printed circuit board to be inspected. This is because the data (correction signal CS) for creating the histogram G is given only when the Hall signal HS ₀ precedes the substrate signal PS ₀ as described above. However, 2 determined from the histogram G created in this way
Using the threshold value, the board signal P of the entire printed board 20
Even if the binarized signal that binarizes S is determined, the problem as shown in FIG. 8B can be avoided. This is because the relationship of the reflection intensity distribution between the reflected light from the wiring pattern and the reflected light from the stage 15 does not differ greatly depending on the position of the printed board 20.

[0034]

As described above, according to the binarization threshold value setting method of the present invention, the substrate signal is masked by the delayed hall signal delayed so as to be in phase with the substrate signal, and the correction signal is obtained. Is generated, accurate mask processing is possible. Further, a histogram relating to the reflection intensity of the first main surface is created based on this correction signal, and the binarization threshold value is set from this histogram, so that the image of the first main surface of the substrate on which the pattern is provided is set to 2 When the value is converted, it is possible to remove the influence of the light reflected by the stage from the region where the substrate is not placed or through the through hole.
Further, in the present invention, since the binarized Hall signal is used to obtain the delayed Hall signal, it is possible to easily obtain the delayed Hall signal as compared with the case of delaying the multilevel signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a pattern binarization processing unit 200 used in an embodiment of the present invention.

FIG. 2 is a schematic diagram of an optical wiring pattern reading device 100 used in an embodiment of the present invention.

3 is a schematic plan view showing the positional relationship between the reading device 100 and the substrate 20. FIG.

FIG. 4 is a diagram showing a relationship between a hole signal HS and a through hole 25.

5 is a diagram showing a relationship between a substrate signal PS and a reflection signal RF due to reflection from the stage 15. FIG.

FIG. 6 is a circuit diagram showing a configuration of a mask processing section 230.

7 is a diagram showing a histogram G. FIG.

FIG. 8 is an explanatory diagram showing a conventional technique.

[Explanation of symbols]

15 stage 20 printed circuit board 22 wiring pattern 25 through hole 110 first light source 120 second light source 210, 220 A / D conversion section 230 mask processing section 240 binarization processing section 250 histogram creation section 260 binarization threshold setting section PS ₀ Board signal PS Digitized board signal HS ₀ Hall signal HS Digitized Hall signal HIS Binarized Hall signal HDS Delayed Hall signal CS Correction signal G Histogram T Binarized threshold

[Procedure amendment]

[Submission date] October 17, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

This will be described with reference to FIG. 3, which is a schematic plan view. By moving the stage 15 in the sub-scanning direction (± Y directions), the reading device 100 can relatively scan the printed circuit board 20 to read it.

Claims (2)

[Claims] 1. A substrate having (a) first and second main surfaces and a through hole, having a relatively low reflectance and a light-shielding property, and further having a relatively high reflectance on the first main surface. Mounting a substrate having a high pattern on a stage having a light-transmitting property, and (b) irradiating the first light from the first light source to the first main surface, Converting the intensity of the reflected light reflected by the surface into an electric signal to obtain a substrate signal indicating an image of the first main surface, and (c) a second light source to the second main surface. 2 of the light is radiated to convert the intensity of the transmitted light of the second light which passes through the region of the stage on which the substrate is not mounted and the through hole into an electric signal to A step of obtaining a hall signal indicating an image of a hole, and (d) binarizing the hall signal to binarize the hall signal. (E) delaying the binarized Hall signal by a predetermined amount to obtain a delayed Hall signal, (f) logically combining the substrate signal and the delayed Hall signal, and Obtaining a correction signal obtained by masking the substrate signal with a delay Hall signal; (g) creating a histogram of the reflection intensity of the first principal surface from the correction signal; and (h) using the histogram, A step of setting a binarization threshold value for binarizing the substrate signal, and a method of setting the binarization threshold value. 2. The method according to claim 1, wherein the steps (b) and (c) are performed by a plurality of reading means, and the predetermined amount of the step (e) is set for each of the reading means. How to set the threshold value.