JPH0546529A - Direct memory access system - Google Patents

Abstract

PURPOSE:To shorten a dead cycle and to transfer the data at a high speed by transmitting a bus idle signal to a direct memory access controller DMAC from a processor and attaining the transfer of data between a memory and an input/output device in a transfer unit of plural direct memory accesses DMA within a bus idle period. CONSTITUTION:When the internal processing time covers a period of the internal processing cycle number larger then the cycle number required for the single DMA transfer, a processor 2 produces a bus idle signal 4 and supplies this signal to a DMAC 8. Then the DMAC 8 transfers the data to a memory 3 from a reception data buffer 9 or to a transmission data buffer 10 from the memory 3 by a quantity equivalent to the frequency decided by the signal 4 in response to the signal 4 and a reception data transfer request signal (1) produced by the buffer 9 or a transmission data transfer request signal (12) produced by the buffer 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access system for effectively utilizing an unused bus while a processor is in internal processing.

In a conventional data processing system, its microprocessor unit (MPU) transfers data between an internal memory (RAM) and an external input / output device (eg, data link, floppy drive controller, etc.). However, the direct memory access method (hereinafter, D
It is called MA method. ) Is used. This DMA system
This is to take advantage of the fact that normal data transfer can be performed at a higher speed than when the MPU transfers input / output data via a buffer provided on the RAM.

[0003]

2. Description of the Related Art The conventional DMA system will be outlined below with reference to FIG. This conventional DMA system is
The MPU 30 loads the program from the ROM 33 to the data bus 3
When the input / output device 35 needs to transfer data to / from the RAM 32 during the execution of the program read via 1, the address counter 101 in the direct memory access controller (hereinafter, referred to as DMAC) 36. , And the number-of-bytes register 104 (see FIG. 8) are set to the start address and the DMA transfer size (for example, the number of bytes) according to the data transfer, and the DMA transfer start state is set.

After entering this state, the transmission register 3
8 or DM from the reception register 37 to the DMAC 36
A request (3) (see (3) in FIG. 9) is transmitted. That DMA
The C 36 sends a bus release request signal (4) (see (4) in FIG. 9) to the MPU 30 via the control line 39. Upon receiving the bus release request signal (4), the MPU 30 completes the processing of the instruction being executed at that time (at this time, the tri-state buffer circuit at the input / output end of the MPU 30 with the data bus 31 becomes high impedance). After that, the bus release signal (5) (see (5) in FIG. 9) is DMed via the control line 40.
It returns to the AC 36 and releases the data bus 31.

The DMAC that has returned this bus release signal
After the exclusive right of the data bus 31 is acquired, the DMA transfer unit (for example, 1 byte) set in the reception register 37 from the input / output device 35 is transferred to the RAM 32 via the data bus 31. RAM stored in the storage area of the RAM 32 designated by the address counter 101 or designated by the address counter 101
A DMA transfer unit (for example, 1 byte) read from the storage area 32 is set in the transmission register 38 via the data bus 31, and then transferred to the input / output device 35.
The DMA transfer is terminated every time such one DMA transfer is completed. Then, for each data transfer request generated thereafter, a similar DMA transfer control procedure for the next DMA transfer is taken.

As described above, for each data transfer request generated thereafter, the above-mentioned DMA transfer is performed by updating the head address set in the address counter 101 to the counted-up address.
Continues intermittently for the transfer size. When the number of bytes set in the number-of-bytes register 104 and the count value of the byte counter 103 match and an output signal (designated number-of-bytes transfer completion signal) is generated from the comparison circuit 105 to complete the DMA transfer, The completion notification to the MPU 50 is performed by register display or by sending an interrupt signal.

In this way, the MPU 30 and the DMAC 3
By sharing the data bus 31 with the exclusive right of the data bus 31 in a time-sharing manner with R.
Data is exchanged between the AM 32 and the input / output device 35 by the MPU.
It can be transferred without going through 30.

[0008]

However, the conventional DMA system described above has the following problems. That is,
As shown in (5) of FIG. 9, the MPU 30 sends a bus release signal to the bus release request signal (4) sent from the DMAC 36.
When (5) (see (5) in FIG. 9) is returned to the DMAC 36, the operation state of the above-mentioned tri-state buffer circuit on the MPU 30 side is as shown in (6) in FIG. 31 has been sent out, and is in a hi-jet state (high-impedance state). However, the switching to the high-jet (HZ) state does not shift to an ideal form as shown in the figure, but the operation of the tri-state buffer circuit shifts to the high-jet state from a certain time value before the high-jet state. Because it will be switched,
For stable data transfer, Δt _d as shown
Only good to take extra dead time into account. And
After the bus release signal (5) is returned, the DMA transfer from the RAM 32 to the input / output device 35 or the DMA transfer from the input / output device 35 to the RAM 32 is started under the control of the DMAC 36 (see FIG. 9). 7) From time T0,
It is from the time when t _{D has} passed. Therefore, the above-mentioned DMA
In the method, in order to perform stable data transfer, the time t _D (dead cycle) is wastefully spent every time the exclusive right of the data bus 31 is switched (1 DMA transfer unit).

The value of such a dead cycle does not become apparent when the above-described switching is performed at relatively long intervals, but the switching is performed in a data transfer environment handling a large amount of data. If it is performed frequently, it becomes a factor that hinders high-speed data transfer.

The present invention has been made in view of the above technical problems, and provides a direct memory access method capable of performing high-speed data transfer while minimizing the dead cycle as described above. That is the purpose.

[0011]

FIG. 1 shows a principle block diagram of the invention according to claim 1, and FIG. 2 shows a principle block diagram of the invention according to claim 2.

According to the first aspect of the present invention, as shown in FIG. 1, when the internal processing period during which the processor 2 does not access the memory 3 via the bus 5 is longer than the number of cycles required for one direct memory access transfer, the bus Idle signal
Direct memory access in response to the bus idle signal (4) and the received data transfer request signal generated from the received data buffer 9 or the transmitted data transfer request signal generated from the transmitted data buffer 10 The controller 8 is characterized by transferring data from the reception data buffer 9 to the memory 3 or from the memory 3 to the transmission data buffer 10 by the number of direct memory access transfers determined by the bus idle signal (4).

The invention according to claim 2 is, as shown in FIG. 2, in the direct memory access method according to claim 1, during transfer of data received from the input / output device to the reception data buffer 9 to the memory 3. Immediately before the reception data buffer 9 is full, or immediately before the transmission data buffer 10 becomes empty during transfer of the data written in the transmission data buffer 10 from the memory 3 to the input / output device, the direct memory access controller 8 Even if the bus idle signal (4) is not received by the direct memory access controller 8, the direct memory access controller 8 receives the forced reception data forced transfer request signal from the reception data buffer 9 or the reception data forced transfer request signal from the transmission data buffer 10. In response to the request, the bus exclusive use permission request signal (6) is sent to the processor 2, and the processor 2 downloads it. And performing data transfer by direct memory access by returning the bus occupation permission notification signal to the Direct Memory Access controller 8 (7).

[0014]

When the internal processing time of the instruction to be executed in the processor 2 exceeds the number of internal processing cycles required for one direct memory access transfer, the bus idle signal 4 is generated from the processor 2. Are supplied to the direct memory access controller 8.

The direct memory access controller 8 responding to the bus idle signal (4) and the received data transfer request signal generated from the received data buffer 9 or the transmitted data transfer request signal generated from the transmitted data buffer 10 is Direct memory access determined by the bus idle signal (4) from the reception data buffer 9 to the memory 3 is transferred, or data is transferred from the memory 3 to the transmission data buffer 10 by the bus idle signal (4). Transfer data for the number of access transfers.

Therefore, when the internal processing time of the instruction is larger than the number of cycles required for one direct memory access transfer, the DMA transfer control processing is repeated once for each direct memory access transfer as in the prior art. The number of dead cycles consumed for each DMA transfer control process is reduced, the DMA transfer performance is improved, and the processing efficiency of the processor is prevented from being lowered.

Then, when the above-mentioned transfer is continued, immediately before the reception data buffer 9 is full or just before the transmission data buffer 10 is empty, the reception data buffer 9 is forced to receive data. A transfer request signal or a transmission data forced transfer request signal from the transmission data buffer 10 is supplied to the direct memory access controller 8.

The direct memory access controller 8 sends a bus exclusive use permission request signal (6) to the processor 2. The processor 2 returns the bus exclusive permission notification signal (7) to the direct memory access controller 8 to perform the direct memory access processing.

Therefore, the discarding of data in the reception data buffer 9 and the occurrence of data breaks in the transmission data buffer 10 are prevented.

[0020]

FIG. 3 shows an embodiment of the present invention. Figure 4
FIG. 3 is a detailed view of a main part of the embodiment. As shown in FIG.
Reference numeral 50 denotes a tri-state buffer circuit 61 connected to the data bus 31, and the tri-state buffer circuit 61.
Arithmetic circuit 60 having an input connected to the output of
A tristate buffer circuit 62 connected between the output of 0 and the data bus 31, an instruction decoder 63 connected to the output of the tristate buffer circuit 61, a bus control circuit 64 connected to the instruction decoder 63, and a bus. And an idle signal generation circuit 65.

The bus control circuit 64 outputs a bus occupation permission notification signal (7) in response to the bus occupation permission request signal (6) from the DMAC 56. The bus idle signal generation circuit 65
Output the bus idle signal (4). This bus idle signal (4) is sent via the line 51 to the DM via the following control while the MPU 50 is performing internal processing such as arithmetic processing.
It is sent to AC56. This Bus Idle Signal (4)
The control of sending the data is determined by determining the number of internal operation cycles required to execute the instruction fetched by the MPU 50 at the time of fetching the instruction, and when the number of internal operation cycles is equal to or greater than the predetermined number of internal operation cycles, the predetermined number is determined. The number of the calculated internal operation cycles is sent to the line 51 for a predetermined period which is larger than the number of transfer cycles required for one DMA transfer. This predetermined period is before the time when the internal processing is completed,
This is the time before the time required for one DMA transfer.

The tristate buffer circuits 61 and 62 are set to the HZ state during the time (for example, one cycle) from the time when the bus idle signal is sent to the time when data can be stably transferred via the bus. In this HZ state, the bus control circuit 64 also requests the bus exclusive permission request signal from the DMAC 56.
Even when the bus exclusive permission notification signal (7) is output in response to (6), the time from the output time of the bus exclusive permission notification signal (7) to the time when data can be transferred stably via the bus ( For example, one cycle).

As described above, the MPU 50 and the DMAC 56 constitute the main part of the present invention. As described above, the data bus 31, the line 51 for sending the bus idle signal from the MPU 50, and the bus exclusive permission request signal (6). The line 52 for transferring the data from the DMAC 56 and the bus exclusive permission notification signal (7) to M
In addition to being connected by the line 53 that transfers from the PU 50,
Other lines not shown are also stretched between the DMAC 56 and the MPU 50. These other lines are not shown for the sake of clarity, since they belong to the known technical field and are incidental in the context of the invention.

The DMAC 56 is a reception data bus 9 which will be described later.
A tristate buffer circuit 70 for connecting 0 to the data bus 31, a tristate buffer circuit 71 for connecting a transmission data bus 91, which will be described later, to the data bus 31,
It has a gate signal generation circuit system for controlling the gates of both tri-state buffer circuits 70 and 71. This gate signal generation circuit system includes an OR circuit 78, a buffer exclusive use permission request signal generation circuit 77, and AND circuits 75 and 76.
, OR circuits 73 and 74, and bus timing generation circuit 7
2 and.

One input of the AND circuit 75 is a DMAC.
Wire 9 wired between 56 and I / O controller 54
2 are connected. The line 92 is a line for transferring the received data transfer request signal from the I / O controller 54. One input of the AND circuit 76 is connected to the DMAC 56 and the I
A line 93 connected to the / O controller 54 is connected. This line 93 transmits the transmission data transfer request signal by I / O.
It is a line transferred from the O controller 54. The above-mentioned line 51 is connected to the other inputs of the AND circuits 75 and 76. The AND circuit 75 is connected to the bus timing generation circuit 72 via the OR circuit 73, and when an output is generated from the AND circuit 75, the bus timing generation circuit 72 is connected to the tristate buffer circuit 7
Generate a signal that puts 0 into a low impedance state. The AND circuit 76 is connected to the bus timing generation circuit 72 via the OR circuit 74, and when an output is generated from the AND circuit 76, the bus timing generation circuit 72 outputs a signal that puts the tri-state buffer circuit 71 into a low impedance state. To occur.

The OR circuit 78 includes a DMAC 56 and an I / O.
The lines 94 and 95 wired between the controller 54 and the controller 54 are connected. The line 94 is connected to one input of the AND circuit 81, and the line 95 is connected to one input of the AND circuit 82. The line 94 is a line that transfers the reception data forced transfer request signal from the I / O controller 54, and the line 95 is a line that transfers the transmission data forced transfer request signal from the I / O controller 54. The output of the OR circuit 78 is connected to the bus exclusive permission request signal generation circuit 77. The buffer exclusive permission request signal generation circuit 77 generates a buffer exclusive permission request signal (Hold RQ) on the line 52 when the output is generated from the OR circuit 78. In response to the buffer exclusive use permission request signal, the line 53 from the bus control circuit 64
Buffer exclusive permission notification signal (Hol
d ACK) is supplied to the other inputs of the AND circuits 81 and 82. The outputs of the AND circuits 81 and 82 are supplied to the bus timing generation circuit 72 via the OR circuit 73 and the OR circuit 74, respectively.

In addition to the above, the DMAC 56 has a conventionally known control circuit for controlling the transfer data amount of the DMA transfer.
That is, the AND circuit 100, the address counter 101, and the byte counter 1 shown in FIG. 8 described in the [Prior Art] section.
03, a byte number register 104, and a comparison circuit 105.

Further, the I / O controller 54 uses the reception FI.
It has a FO 98 and a transmission FIFO 99. Receive FIF
O98 sequentially stores the data received from the input / output device 35, and outputs the received data transfer request signal to the line 92 while the received data is being stored by the storage. Immediately before such reception and storage progresses and just before the vacancy is exhausted, a reception data forced transfer request signal is transmitted to the line 94. From the reception FIFO 98, when DMA transfer starts,
The data stored in the first-in first-out format is sequentially sent to the reception data bus 90. Transmission FIF
The O99 sequentially stores the transmission data via the transmission data bus 91, and if there is still a space in the storage, transmits the transmission data transfer request signal to the line 93. Send FI
The data stored in the FO 99 is sequentially transmitted to the input / output device 35 in a first-in-first-out format at the start of DMA transfer. By this transmission, the input / output device 35
If there is less data to be stored on the transmission data bus 91 than to the data to be transmitted to, the transmission FIFO 99 will eventually become empty when the above transmission is performed, but immediately before that, on the line 95. Send the transmission data forced transfer request signal.

Reception FIFO 98 and transmission FIFO 99
Has a buffer capacity of a DMA transfer unit larger than a predetermined DMA transfer unit that can be transferred in one DMA transfer. There is a predetermined functional relationship between this capacity and the predetermined number of internal operation cycles and the transfer rate with the input / output device 35.

FIG. 5 and FIG. 6 constitute one drawing by joining the lines V-V. 3 and 4
In, the MPU 50 is the processor 2 of FIGS.
The RAM 32 corresponds to the memory 3 in FIGS. 1 and 2. The data bus 31 corresponds to the bus 5 of FIGS. 1 and 2, and the direct memory access controller 56 is
This corresponds to the direct memory access controller 8 of FIGS. 1 and 2. The reception FIFO 98 corresponds to the reception data buffer 9 of FIGS. 1 and 2, and the transmission FIFO 99 corresponds to the transmission data buffer 10 of FIGS. 1 and 2.

The operation of the present invention configured as described above will be described below. D in the system constructed according to the present invention
Also in the MA transfer, when it is necessary to perform the DMA transfer from the RAM 32 to the input / output device 35 or the DMA transfer from the input / output device 35 to the RAM 32 as in the conventional case, the MP transfer is performed.
The start address and the number of DMA transfer units (for example, 1 byte) are transferred from U50 to the DMAC 56 via the data bus 31, the start address is set in the address counter 101 as shown in FIG. There is no change in setting the number of transfer bytes and entering the DMA transfer control. However, when the following processing state of the MPU 50 or the processing state of the I / O controller 54 occurs, the DMAC 56 is connected to the data bus 31 of the data bus 31. The feature of the present invention lies in that the exclusive right is obtained.

When an instruction is fetched from the ROM 33 and the instruction is decoded by the instruction decoder 63, if the internal operation cycle number, for example, 10 is a predetermined internal operation cycle number, for example, 5 or more ((( 1) and (2)), even if the processing of the instruction is not completed, the bus idle signal (4) (4 in FIG. 5) is provided on the line 51 during the period determined according to the fetched instruction as described above. (See (4)).

As a result, as shown in FIG. 4, the reception data transfer request signal or the transmission data transfer request signal sent from the I / O controller 54 to the DMAC 56 by the bus idle signal (4) is transmitted to the AND circuit 7
5, or the AND circuit 76, and the OR circuit 73 or the OR circuit 74 to the bus timing generation circuit 72.
It is supplied as an MA execution instruction signal or a transmission DMA execution instruction signal. The bus timing generation circuit 72 is responsive to the received receive DMA execution instruction signal or the transmit DMA execution instruction signal to supply the tristate buffer circuit 70,
Alternatively, a control signal is supplied to the tri-state buffer circuit 71 to put it in a low impedance state.

As described above, the start address of DMA transfer and the number of transfer bytes are transferred from the MPU 50 to the DMAC 56 in the same manner as in the conventional case, and the start address is set in the address counter 101 via the AND gate circuit 100. The number of bytes to be transferred is set in the byte number counter 65 in the same manner as in the conventional case, so that 1-byte DMA transfer is performed in the same manner as in the conventional case. In this example, while the DMA transfer takes only 4 cycles, the byte idle signal generated from the decoding of the fetched instruction by the instruction decoder 63 (see 200 in FIG. 5) is not completed until the first DMA transfer completion time. Has been generated (see 201 in FIG. 5). First DM
The A transfer is started by the identification of the first cycle of the byte idle signal. Then, at the predetermined time (the immediately preceding cycle) before the completion of the first DMA transfer, the bus timing generation circuit 72 identifies the immediately preceding cycle as described above and does not follow the conventional DMA transfer control procedure. , The second DMA transfer is immediately started.

As described above, according to the present invention, by judging the number of cycles required for the internal operation of the fetched instruction,
DM without the conventional DMA transfer control procedure
A transfer can be continuously performed. Therefore, as can be seen from this example, as the number of bus cycles required for the internal operation of the fetched instruction increases, the number of times the conventional DMA transfer control procedure is performed can be reduced. Inevitably DM in the procedure
It is possible to reduce the wasteful time (dead cycle) that comes in as the time for the entire A transfer as much as possible.

However, it is possible to perform the DMA transfer without the conventional DMA transfer control procedure as described above.
The number of cycles required for the internal operation of the fetched instruction is
Since the number of cycles is greater than the number of cycles required for one DMA transfer, the number of internal operation cycles of the fetched instruction is less than the number of cycles required for one DMA transfer. Is 2 in FIG.
No bus idle signal is generated as shown at 05 and 206. Therefore, while such an instruction is being executed,
The data transferred from the input / output device 35 is received FI.
The data is sequentially stored in the FO 98, and the data stored in the transmission FIFO 99 is sequentially transferred to the input / output device 35.

Therefore, in the manner as described above, sequentially D
When the MA transfer is performed, for example, during the transfer from the input / output device 35 to the receive FIFO 98, a situation occurs in which data is received from the input / output device 35 to the full capacity of the receive FIFO 98, and input / output from the transmit FIFO 99 is performed. It is possible that the transmit FIFO 99 becomes empty during the transfer to the device 35. Of these states, in the former case,
Immediately before it becomes full, DM the received data forced transfer signal
It is sent from the AC 56 to the MPU 50. In the latter case,
Immediately before the transmission FIFO 99 becomes empty, the transmission data forced transfer signal is sent from the DMAC 56 to the MPU 50. The received data forced transfer signal or the transmitted data forced transfer signal is supplied to the buffer exclusive permission request signal generation circuit 77 via the OR circuit 78, and the AND circuit 81,
Alternatively, it is supplied to the AND circuit 82.

The buffer exclusive use request signal generation circuit 77 which receives the received data forced transfer signal or the transmitted data forced transfer signal (see 210 in FIG. 6) sends the bus exclusive use request signal (to the MPU 50 via the line 52). 6) is sent. MPU5 which received this bus exclusive permission request signal (6)
The bus control circuit 64 of 0 enters the interruption processing of the memory access by the MPU 50 (see 211 in FIG. 5), and after the time required for the processing, sets the tri-state buffer circuit 61 or the tri-state buffer circuit 62 to the HZ state and the data bus. 31 release and bus exclusive permission notification signal
(7) is sent to the line 53 (see 212 in FIG. 5). The buffer exclusive permission notification signal is the received data forced transfer request signal,
Alternatively, the signal is supplied to the bus timing generation circuit 72 via the AND circuit 81 or the AND circuit 82 which satisfies the AND condition by the transmission data forced transfer request signal, and the OR circuit 73 or the OR circuit 74. From this point onward, DM is performed by performing only one DMA transfer as in the conventional DMA transfer control.
Except for the fact that the A transfer is terminated (see (5) in FIG. 6), it is the same as the case where the bus idle signal is generated, and therefore its detailed description is omitted.

In this way, it is possible to prevent the discarding of data from the reception FIFO 98 or the occurrence of data loss in the transmission FIFO 99. Therefore, conventional 1-byte DMA
In the transfer, it is possible to reduce the frequency of occurrence of dead cycles, which are particularly likely to occur in the transfer of a large amount of data, and it is possible to perform continuous DMA transfer without discarding or interruption of data. As a result, it also improves the processing capability of the MPU 50.

The generation period of the bus idle signal (4) in the above embodiment is determined as described above.
The present invention cannot be implemented only with this signal. It may be another type of bus idle signal. In that case, control according to the signal generation format is performed by the MPU 50.
Interface with the DMAC 56. In short, the present invention intends to perform the DMA transfer as much as possible by using the bus idle signal.

[0041]

As described above, according to the present invention, a bus idle signal is sent from the processor to the DMAC, and data of a plurality of DMA transfer units are transferred between the memory and the input / output device during the period of the bus idle signal. Since the data can be transferred between them, it is possible to greatly suppress the occurrence of a dead cycle that would occur in the conventional DMA transfer for each transfer unit, especially in a large amount of data transfer. This also prevents the processing efficiency of the processor from decreasing.
In addition, it is possible to prevent the discard of the transferred data and the occurrence of breaks.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the invention according to claim 1.

FIG. 2 is a principle block diagram of an invention according to claim 2;

FIG. 3 is a diagram showing an embodiment of the invention according to claim 1 and claim 2;

FIG. 4 is a detailed view of a main part of the DMAC of the embodiment shown in FIG.

5 is a diagram showing a part of a timing chart in the detailed diagram shown in FIG. 4;

FIG. 6 is a diagram showing the remaining part of the timing chart in the detailed diagram shown in FIG. 4;

FIG. 7 is a system configuration diagram adopting a conventional DMA method.

FIG. 8 is a detailed view of a main part of a conventional DMAC.

9 is a diagram showing a timing chart in the system shown in FIG.

[Explanation of symbols]

 2 Processor 3 Memory (4) Bus idle signal 5 Bus 8 Direct memory access controller 9 Receive data buffer 10 Send data buffer Receive data forced transfer request signal Receive data forced transfer request signal (6) Bus exclusive permission request signal (7) Bus exclusive Permission notification signal 31 Data bus 32 RAM 50 MPU 56 Direct memory access controller 98 Reception FIFO 99 Transmission FIFO

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Megumi Shibata 3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture, Fujitsu Communication Center Systems Co., Ltd. (72) Inventor Yamato, Kohoku Ward, Yokohama City, Kanagawa Prefecture Shin-Yokohama 3-9-18 Fujitsu Communication Systems Co., Ltd. (72) Inventor Takayuki Moriyama 3-9-18 Shin-Yokohama Yokohama Kohoku Ward, Kanagawa Prefecture Fujitsu Communication Systems Co., Ltd. (72) Inventor Minoru Nakahara 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa, Fujitsu Communication Center Systems Ltd.

Claims (2)

[Claims] 1. A bus idle signal (4) is generated when an internal processing period during which the processor (2) does not access the memory (3) via the bus (5) is longer than the number of cycles required for one direct memory access transfer. And a direct memory access controller responsive to the bus idle signal (4) and the received data transfer request signal generated from the received data buffer (9) or the transmitted data transfer request signal generated from the transmitted data buffer (10) (8) transfers data from the reception data buffer (9) to the memory (3) or from the memory (3) to the transmission data buffer (10) for the number of direct memory access transfers determined by the bus idle signal (4). Direct memory access method characterized by: 2. The direct memory access method according to claim 1, wherein the reception data buffer (9) is full during transfer of data received from the input / output device to the reception data buffer (9) to the memory (3). Immediately before, or immediately before the transmission data buffer (10) becomes empty during the transfer of the data written in the transmission data buffer (10) from the memory (3) to the input / output device, the direct memory access controller (8 ) Said bus idle signal (4)
The direct memory access controller (8) responds to the reception data forced transfer request signal from the reception data buffer (9) or the reception data forced transfer request signal from the transmission data buffer (10) even if the reception data is not received. Bus exclusive permission request signal to the processor (2)
(6) is sent to the processor (2), and data is transferred by direct memory access by returning the bus exclusive permission notification signal (7) from the processor (2) to the direct memory access controller (8). Direct memory access method.