JPH0541675A - Radio transmitter-receiver - Google Patents

Abstract

PURPOSE:To obtain the transmitter-receiver not generating an unlock alarm in a phase synchronization loop (PLL) synthesizer which is used as a local oscillation signal source for transmission and reception even when an out of phase synchronism of the frequency changeover transition period occurs in the TDMA communication system transmitter-receiver. CONSTITUTION:A transmission/reception part 10 includes a PLL synthesizer 5 supplying a local oscillation signal S13 with the frequency responding to a control signal S16a from a control part 6 to a transmission part 3 and a reception part 4. When an unlock of the phase synchronization occurs in the PLL synthesizer 5, an unlock alarm is displayed on an LCD display part 7 by control signals S16b and S19 from the synthesizer 5 and the control part 6. During the period of the unlock occurred on a frequency switch over transition period caused accompanying the frequency changeover of a transmission signal S11 and a reception signal S12, the PLL synthesizer 5 prohibits the generation of the unlock alarm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase locked loop (PL
Frequency synthesizer including L) (hereinafter, PLL synthesizer) unlock alarm (Unlock Alar)
m, out-of-synchronization alarm) is one of the device alarms related to a wireless transceiver (hereinafter referred to as transceiver),
Frequency-switching TDMA (Time Division)
(Mul-tiple Access, time division multiple access)
The present invention relates to a transceiver of this type, which is suitable for a wireless communication system such as a communication system that switches a transmission frequency at high speed and frequently.

[0002]

2. Description of the Related Art The TDMA communication system is GSM (Grou
It is used in many wireless communication systems such as a digital mobile phone system based on the pe Special Mobile-standard. Since a transmitter and a receiver for the TDMA communication system do not perform transmission and reception at the same time, one PLL synthesizer is shared as a local oscillation signal source of a reception unit and a transmission unit. In a transceiver for the above-mentioned digital automobile system, which requires a high degree of frequency accuracy and miniaturization of the entire apparatus, it is essential to share the transmission and reception of this PLL synthesizer. Further, in the TDMA communication system such as the above digital car telephone system, it is necessary to switch the transmission / reception frequency within a relatively narrow frequency range, that is, perform frequency hopping in order to secure communication quality. To meet this need, the P
The LL synthesizer must be able to withstand fast and frequent frequency switching.

For the PLL synthesizer to operate normally, P
It is essential for the LL to remain in phase synchronization, and loss of synchronization must be detected quickly and corrective measures taken.
Therefore, the PLL synthesizer usually includes an unlock detection circuit that detects the unlock of the PLL. On the other hand, the PLL synthesizer used in the transceiver that performs the frequency hopping causes phase synchronization loss (hereinafter, initial phase synchronization loss) immediately after each frequency switching, and thus an unlock alarm is generated each time. It will be. .. In the conventional PLL synthesizer, an unlock alarm is generated even when the normal phase synchronization is lost in the initial stage of the signal frequency switching, and therefore the transceiver determines that the normal PLL synthesizer is in abnormal operation. The initial phase shift is unavoidably generated in the PLL synthesizer as long as the transceiver performs frequency hopping. Therefore, an initial phase shift that causes an unlock alarm each time and a phase synchronization shift that requires a phase synchronization recovery measure are taken. It becomes impossible to distinguish.

[0004]

Therefore, the first aspect of the present invention
The purpose of is a transmitter / receiver that frequently switches the frequency of a transmission / reception signal, such as a TDMA communication system with frequency hopping, in which one PLL synthesizer is shared as a transmission and reception local oscillation signal source. In this machine, there is provided a transceiver configured so that an unlock alarm is not generated even if the PLL synthesizer is out of phase synchronization for a certain period immediately after the frequency switching.

A second object of the present invention is to provide a PLL synthesizer which prohibits the generation of an unlock alarm for a certain period immediately after the frequency switching.

[0006]

A PLL synthesizer that characterizes the transceiver of the present invention has a transmission frequency and a reception frequency which are different from each other at a high speed and frequently, as in a TDMA communication system for performing frequency hopping. It is suitable for transceivers of the communication system that switches the frequency.

This PLL synthesizer divides the output of a voltage controlled oscillator (VCO) by a frequency divider, adds a frequency division output (referred to as a comparison signal) and a reference signal from a reference oscillator to a phase comparator, and outputs a phase difference. A PLL oscillator for generating a signal and controlling the oscillation frequency of the VCO based on the phase difference signal is provided. The switching of the frequency of the PLL synthesizer is started by adding a frequency control signal instructing the frequency divider to change the frequency division ratio. The phase comparator is
In the out-of-phase state where there is a phase difference between the comparison signal and the reference signal, not only the phase difference signal is generated but also a phase difference detection signal corresponding to the phase difference is generated. Audible and / or visible alarms are displayed on the alarm display of the transceiver in response to the phase difference detection signal. The PLL synthesizer according to the present invention includes an unlock alarm prohibition circuit that prohibits the response of the alarm display unit to the phase difference detection signal for a predetermined time from the issuance of the detection signal.

The output frequency of this PLL synthesizer is
The frequency switching signal is switched each time the frequency division ratio data signal and the data setting signal that constitutes the frequency control signal are supplied, but the phase synchronization is lost during the transient period immediately after the frequency switching at a very short time. However, the unlock alarm prohibition circuit prohibits the generation of the unlock alarm for at least this transition period. Therefore,
If this PLL synthesizer is used in a transceiver having a high frequency switching frequency, the above-mentioned problem that an unlock alarm is generated each time the signal frequency is switched is solved.

[0009]

The present invention will be described below with reference to the drawings.

Referring to the block diagram of FIG. 1, the mobile transceiver of the GSM standard digital mobile telephone system embodying the present invention sends a transmission signal S11 to a base station (not shown) and at the same time The antenna 1 which receives the radio frequency signal from the antenna 1 and supplies it as the reception signal S12 to the reception unit 4, and the input call signal S14 are frequency-converted and amplified to generate the transmission signal S11 and the reception signal S12.
The transmitter / receiver 10 converts 12 into a call signal S18, and the handset 8 that generates the call signal S14 and receives the call signal S18. A control signal S20 for call connection is provided between the transceiver 10 and the handset 8.
a and S20b are exchanged.

The transmitter / receiver 10 includes an SPDT type RF switch 2 having a common terminal connected to the antenna 1 and a control signal S.
15 and a transmitter 3 that generates a transmission signal S11 in response to a call signal S14 from the handset 8 and sends the signal S11 to the antenna 1 via the first switching terminal of the RF switch 2, the antenna 1 and the RF switch. The reception signal S12 input via the second switching terminal of the control signal S1
7b and a call signal S18 is sent to the handset 8.
And a PLL synthesizer 5 whose frequency is controlled by the frequency control signal S16a and which supplies the local oscillation signal S13 to the transmitter 3 and the receiver 4. Further, the transmitting / receiving unit 10 controls the control signals S15, S17a, S based on the control signal S20b and the control signal S17b.
16a and S20a are respectively transmitted to control the transmitter 3, the receiver 4, the PLL synthesizer 5 and the handset 8, frequency selection of the transmission signal S11 and the reception signal S12, ON / OFF control of the transmission carrier wave, and the above base station. Control unit 6 for controlling call connection with
Equipped with. Further, the transmission / reception unit 10 displays an LCD (Liquid Cry) such as an operation abnormality of the transceiver 10 according to an instruction of the control signal S19 from the control unit 6.
A display unit 7 is provided. In addition,
The transmitter / receiver 10 includes a battery package and the like in addition to the circuits shown in the figure, but these are not shown because they are not related to the present invention.

The PLL synthesizer 5 of FIG. 1 supplies the unlock alarm detected by the unlock alarm generating means incorporated therein to the control unit 6 in the form of a control signal S16b. The control unit 6 performs predetermined signal processing including the operation abnormality alarm from other circuits, supplies the control signal S19 to the LCD display unit 7, and instructs the LCD display unit 7 to display an alarm. But P
The LL synthesizer 5 responds to the frequency control signal S16a from the control unit 6 to end the frequency switching, and during the transition period until the phase locked state is restored, the unlock alarm prohibiting means, which will be described later, controls the unlock alarm. The transmission of (control signal S16b) is prohibited. Therefore, since the unlock alarm is not supplied to the control unit 6 during the transition period, the erroneous unlock alarm is not displayed on the LCD display unit 7.

Next, the frequency hopping operation in the transmitting / receiving section 10 of FIG. 1 will be described with reference to the timing chart of FIG. First, the signal form of the TDMA signal will be described. This transmission / reception unit 10 uses a downlink (Downli-n) from a base station in a cell (se-riving cell) to which the current position of the vehicle is mounted.
k) As frequency channels, three channels c0, c1 and c2 can be used, and as uplink frequency channels to the base station, three channels c0, c1 and c2 can also be used. However, even in the same frequency channel, the frequencies of transmission (uplink) and reception (downlink) are different. A plurality of adjacent cells (a
frequency channel d of d-jace-nt cells)
0 and e0 are represented as monitor channels for electric field strength monitoring. The transmission and reception frequency channel switching sequence (frequency hopping sequence) is sent from the base station to the control unit 6 through the control channel (the reception signal S12 and the control signal S17b of the reception unit 4) before the call channel is opened. This hopping sequence is stored. In addition, 1TDM in GSM standard
The A frame (1 frame = 4.615 ms) consists of 8 bursts (1 burst = 0.577 ms).

First, the reception signal S12 from the base station is supplied to the reception unit 3 through the third burst of the downlink c0 channel (RX1). Next, the transmitter 4 sends out the transmission signal S11 through the uplink of the same channel, the same frame and the same burst (TX2). The uplink burst is set to be transmitted with a delay of three burst periods from the downlink burst.
Then, the receiving unit 3 checks whether there is an adjacent cell that can obtain better communication quality than the cell to which the current position of the onboard vehicle belongs, in order to check the burst (RX) for the next frame.
At the appropriate time during the 5 bursts until receiving 2),
The electric field of the d0 channel of the adjacent cell is monitored through the reception signal S12 (Monitor 1). After monitoring the electric field of the adjacent cell, the receiving unit 3 enters the receiving system for the next frame, and receives the received signal S12 by frequency hopping to the c2 channel, though it is the same third burst as the previous one (RX2). Then, the transmission unit 4 sends the transmission signal S11 by the third burst of the same c2 channel as the previous reception (TX2). The electric field monitor of the adjacent cell after this is
The electric field of the e0 channel of a cell different from the above is monitored (Monitor 2).

The hopping sequence is executed by switching the frequency of the local oscillation signal S13 supplied by the PLL synthesizer 5 under the control of the frequency control signal S16a from the control unit 6. Therefore, the frequency of the local oscillation signal S13 supplied from the PLL synthesizer 5 to the transmitting unit 3 and the receiving unit 4 needs to be switched for each burst of transmission and reception. The PLL synthesizer 5 of the transceiver that performs frequency hopping in this way has a high-speed and frequent local oscillation signal S13 that is once or more within one frame period.
The frequency is switched. In addition, the transmitting / receiving unit 10
The transmission or reception operation is performed only during 3 burst periods of the 8 bursts of the frame, and the transmission and reception operations are suspended during the other burst periods.

The PLL synthesizer 5 loses phase synchronization each time the frequency of the local oscillation signal S13 is switched and at each transient period immediately after the frequency switching. This loss of phase synchronization is PL
It occurs even if the function of the L synthesizer 5 is normal. Therefore, the PLL synthesizer 5 performs frequency switching during the pause period of the transmission and reception operations of the transmission / reception unit 10 and prohibits the unlock alarm from being out of phase synchronization during the transition period. Here, the control signal S16a for instructing the frequency switching of the PLL synthesizer 5 includes a frequency division ratio data signal S37 for designating the frequency of the local oscillation signal S13 and a data setting signal S38 for activating this signal S37, as described later. Made of. Frequency division ratio data signal S
37 is supplied from the control unit 6 at the same time when the transmitter 3 and the receiver 4 start burst transmission and reception, and the data setting signal S38 is supplied after the burst transmission and reception are completed. The PLL synthesizer 5 uses the data setting signal S3.
Although the frequency switching of the local oscillation signal S13 is started by the supply of 8, the initial phase synchronization is lost during the transient period determined by the performance of the PLL synthesizer 5 at the initial stage of the frequency switching. The PLL synthesizer 5 completes the phase synchronization operation by the start of transmission or reception of the next burst, that is, within the transmission and reception operation idle period for the duration of one burst or 1.5 times the burst period. Then, the local oscillation signal S13 having the required frequency is generated. On the other hand, the unlock alarm prohibiting means generates the unlock alarm for a period T including some allowable error in the period in which the initial phase synchronization is lost after the data setting signal S38 is applied to the PLL synthesizer 5. Prohibit

Referring to the block diagram of FIG.
The L synthesizer 5 supplies a local oscillation frequency signal S36 having a frequency determined in response to the control voltage S31 to the synthesizer output terminal 501, and a frequency division number supplied from the frequency division ratio data input terminal 502 to specify the frequency division number. The variable frequency division ratio data signal S37 and the variable frequency division control signal generated by the data setting signal input terminal 503 and controlled by the data setting signal activating the frequency division ratio data signal S37 to generate the comparison signal S34 by dividing the signal S36. 55, a reference oscillator 54 that supplies a reference signal S33 having a reference frequency, a phase comparator 53 that compares the comparison signal S34 and the reference signal S33 in phase to generate a phase difference signal S32, and the phase difference signal S
And a low-pass filter 52 that integrates 32 to generate the control voltage S31. here,
Local oscillation signal S supplied by the PLL synthesizer 5 of FIG.
13 corresponds to the frequency signal S36, and the local oscillation signal S13
The frequency control signal S16a for controlling the frequency is divided into a frequency division ratio data signal S37 and a data setting signal S38.

The phase comparator 53 of FIG. 3 has a comparison signal S34.
In the unlocked state of the PLL synthesizer 5 in which there is a phase difference between the reference signal S33 and the reference signal S33, the phase difference detection signal S35 of the pulse corresponding to the phase difference together with the phase difference signal S32 is provided.
Is output. The phase difference detection signal S35 is supplied to the gate circuit 57 which produces an output pulse signal S40 having the same waveform as that of the signal S35 supplied when the gate is ON and zero potential when the gate is OFF. Output pulse signal S4
0 is further supplied to a pulse detection circuit 58 for converting it into an alarm output S41 representative of the alarm of the PLL synthesizer 5, and the pulse detection circuit 58 uses this alarm output S41 at the alarm terminal 504 as one of the device alarms.
Occurs in the control unit 6 of. The above circuit constitutes the unlock alarm generating means described with reference to FIG.

Further referring to FIG. 3, a pulse generating circuit 56 including a one-shot multivibrator and the like.
Generates a gate pulse signal S39 having a constant time width T in response to a data setting signal S38 such as a trigger pulse. This signal S39 turns off the gate circuit 57. Therefore, the pulse detection circuit 58 does not generate the alarm output S41 at the alarm output terminal 504 until a predetermined time T has elapsed from the start of supplying the data setting signal S38. The circuit described above constitutes the unlock alarm prohibiting means described with reference to FIG.

As described above, the PLL synthesizer 5 shown in FIG.
Is the division ratio data signal S37 and the data setting signal S3.
Although the frequency of the frequency signal S36 is switched every time 8 inputs are made, even if the circuit function is normal, the phase synchronization is lost during the transient period immediately after the frequency switching. However, during the period in which the initial phase synchronization is lost, the pulse generation circuit 5
An unlock alarm (alarm output S4
The occurrence of 1) is prohibited.

Therefore, the PLL synthesizer 5 does not issue an alarm for the loss of synchronization in the normal operation, so that it is easy to discriminate the true operation abnormality. This PLL
If the synthesizer 5 is used as the local oscillator (PLL synthesizer 5) of the transceiver of FIG. 1 having the frequency hopping function, the false unlock alarm does not occur even if the frequency is switched at high speed and frequently.

Referring to the circuit diagram of FIG. 4, in the example of the pulse detection circuit 58 of FIG. 3, the gate outputs the pulse signal S40.
FET transistor TR1 whose input terminal is the grounded source, and whose cathode is connected to the drain of FET transistor TR1 and whose anode is the alarm output terminal 5
04, a diode D1, a capacitor C1 connected between the anode of the diode D1 and ground, and a resistor R1 connected between the positive power supply Vcc and the anode of the diode D1. This pulse detection circuit 58 is
When the output pulse signal S40 is not supplied, the voltage of the alarm output terminal 504 (alarm output S
21) is set to a high level and the alarm output S21 is set to a low level as soon as the output pulse signal S40 is detected, and this low level is used as an unlock alarm indicating unlocking of the PLL synthesizer 5.

Referring to FIG. 5 together with FIG. 3 showing waveform diagrams of some signals related to unlock alarms during normal operation of the PLL synthesizer 5 of FIG. 3, the reference oscillator 54 has a rectangular wave-shaped reference signal S33. Is being supplied.
The frequency divider 55 supplies the comparison signal S34 obtained by dividing the frequency signal S36 (not shown). When the data setting signal S38 is supplied to the variable frequency divider 55 at the time t2, this signal S38 is the frequency division ratio data signal S already input.
Activate 37 (not shown). Then, the variable frequency divider 5
Since the frequency division ratio of 5 changes, the frequency of the comparison signal S34 changes, and the PLL synthesizer 5 is out of phase synchronization, and a phase difference occurs between the reference signal S33 and the comparison signal S34. As a result, a pulsed phase difference detection signal S35 corresponding to the phase difference between the reference signal S33 and the comparison signal S34 is generated. This phase difference detection signal S35 is the PLL
Although showing the unlocked state of the synthesizer 5, this unlocked state naturally occurs in the initial stage of the frequency switching of the frequency signal S36, and the PLL synthesizer 5 is normally operating. The unlocked state is time t determined by the performance of the PLL synthesizer 5.
Continue to 3.

On the other hand, when the pulse generating circuit 56 of FIG. 3 receives the data setting signal S38, the unlock time (time t2 to time t immediately after the frequency switching of the PLL synthesizer 5 is performed.
3 (time until 3) plus an allowable error T (time t2)
From time t4) to the gate pulse signal S39. That is, the rising edge of the gate pulse signal S39 coincides with the rising time t2 of the data setting signal S38,
The trailing edge coincides with time t4 when time T has elapsed from time t2. When the pulse width T of the gate pulse signal S39 is set in this way, if the PLL synthesizer 5 is normal, even if the phase difference detection signal S35 occurs immediately after the frequency switching of the frequency signal S36, the output pulse signal from the gate circuit 57 S40 is always at a low level as shown.
Therefore, the alarm output S4 output from the pulse detection circuit 58
1 is always high level, and the PLL synthesizer 5 does not send an alarm.

The phase comparator 53 performs phase comparison with each other with reference to the falling edges of the supplied reference signal S33 and comparison signal S34, and outputs a phase difference detection signal S35 and the phase difference signal S32. These phase difference signal S32 and reference signal S3 shown in FIG.
3. The phase comparator 53 for inputting / outputting the comparison signal S34 and the phase difference detection signal S35 is integrated in a part of the μPC2833C type PLL frequency synthesizer LSI (manufactured by NEC Corporation) and has a frequency of at least 1 MHz. The signal phases can be compared.

Referring to the signal waveform diagram of FIG. 6 together with FIG. 3, it relates to an unlock alarm at the time of abnormal operation of the PLL synthesizer 5 which is in an unlocked state other than when the frequency of the frequency signal S36 is switched. The waveforms of some signals are shown.

As in the case of FIG. 5, the PLL synthesizer 5 has a normal initial unlock period T between the times t2 and t4.
However, the phase comparator 53 uses the other time t1,
Also at t5, t6 and t7, the phase difference detection signal S35
Is occurring. Therefore, the PLL synthesizer 5 is in an abnormal operation state. The pulse generation circuit 56 turns on the gate circuit 57 except during the period T in which the data setting signal S38 is received and the gate pulse signal S39 is generated.
At time t1, t5, t6 and time t7, the phase difference detection signal S35 is output as it is as the output pulse signal S40. When this signal S40 is supplied to the pulse detection circuit 58, the alarm output S41 generated at the alarm output terminal 504 immediately becomes low level, which indicates the alarm generation state of the PLL synthesizer 5.

[0028]

As described above, the PLL synthesizer in the transceiver of the present invention prohibits the unlock alarm transmission during the unlock period immediately after the frequency switching.
Therefore, according to the present invention, T with frequency hopping
In a transceiver that switches the transmission and reception signal frequencies at high speed and frequently so as to be suitable for the DMA communication system, it is possible to prohibit the generation of an unlock alarm in the normal unlocked state of the PLL synthesizer immediately after the frequency switching. , The true unlocked state and the normal unlocked state can be distinguished from each other, and the obstacle to communication can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a transmitter / receiver for a GSM standard TDMA communication system embodying the present invention.

FIG. 2 is a timing chart diagram for explaining a frequency hopping operation of the transceiver of FIG.

3 is a block diagram of a PLL synthesizer forming a part of the transceiver of FIG. 1. FIG.

4 is a circuit diagram of a pulse detection circuit forming a part of the PLL synthesizer of FIG.

5 is a signal waveform diagram of the PLL synthesizer of FIG. 3 during normal operation.

6 is a signal waveform diagram during abnormal operation of the PLL synthesizer of FIG.

[Explanation of symbols]

1 Antenna 2 RF Switch 3 Transmitter 4 Receiver 5 Synthesizer 6 Controller 7 LCD Display 8 Handset 10 Transmitter / receiver 51 Voltage Controlled Oscillator 52 Low Pass Filter 53 Phase Comparator 54 Reference Oscillator 55 Variable Divider 56 Pulse Generator 57 Gate Circuit 58 Pulse detection circuit 501 Synthesizer output terminal 502 Dividing ratio data input terminal 503 Data setting signal input terminal 504 Alarm output terminal S11 Transmission signal S12 Reception signal S13 Local oscillation signal S14, S18 Speech signal S15, S16b, S17a, S17b, S19 , S2
0a, S20b Control signal S16a Frequency control signal S31 Control voltage S32 Phase difference signal S33 Reference signal S34 Comparison signal S35 Phase difference detection signal S36 Local oscillation frequency signal S37 Frequency division ratio data signal S38 Data setting signal S39 Gate pulse signal S40 Output pulse signal S41 Alarm output C1 Capacitor D1 Diode R1 Resistor TR1 FET Vcc Positive power supply

Claims (18)

[Claims] 1. A transmitting means for transmitting a first radio frequency carrier modulated by an information signal to be transmitted through an antenna, and a second radio frequency carrier modulated by an information signal to be received by the antenna. A local oscillation signal having a frequency having a predetermined relationship with the first and second frequencies, including a receiving means for receiving via a phase locked loop (PLL), is commonly supplied to the transmitting means and the receiving means. PLL synthesizer, alarm display means for displaying a device alarm in response to a display control signal, and frequency for controlling the transmitting means, the receiving means and the PLL synthesizer so as to switch the frequencies of the first and second radio frequency carriers. A wireless transceiver comprising a control means and a display control means for supplying the display control signal, wherein: The transmitting means is a TDMA-compliant transmitting / receiving means for ON / OFF controlling the first and second radio frequency carriers and transmitting / receiving in bursts, and the PLL synthesizer is a frequency control signal from the frequency controlling means. In response to the frequency switching means for switching the frequency of the local oscillation signal, an alarm generating means for supplying an alarm signal to the display control means in response to the out-of-phase of the phase locked loop, and in response to the frequency control means. And an alarm prohibition means for prohibiting the alarm signal generation by the alarm generation means for a predetermined period immediately after the frequency switching of the first and second radio frequency carriers is performed. Transceiver. 2. The frequency control signal includes a frequency designation signal that designates a frequency of the local oscillation signal, and a data setting signal that is supplied later than the frequency designation signal and activates the frequency designation signal. The wireless transceiver according to claim 1, wherein 3. The radio transceiver according to claim 2, wherein the prohibition of the alarm signal generation is started in response to the data setting signal. 4. A radio transceiver for a TDMA communication system, wherein the radio transceiver is capable of selectively setting a timing for turning on the first and second radio frequency carriers and a frequency of these carriers, The wireless transceiver according to claim 1, wherein the alarm generation prohibition period is shorter than a period in which the first and second radio frequency carriers are not in an ON state. 5. A transmitting means for transmitting a first radio frequency carrier modulated by an information signal to be transmitted through an antenna, and a second radio frequency carrier modulated by an information signal to be received by the antenna. A local oscillation signal having a frequency having a predetermined relationship with the first and second frequencies, including a receiving means for receiving via a phase locked loop (PLL), is commonly supplied to the transmitting means and the receiving means. PLL synthesizer, alarm display means for displaying a device alarm in response to a display control signal, and frequency for controlling the transmitting means, the receiving means and the PLL synthesizer so as to switch the frequencies of the first and second radio frequency carriers. A wireless transceiver comprising a control means and a display control means for supplying the display control signal, wherein: The transmitting means is a TDMA-compliant transmitting / receiving means for ON / OFF controlling the first and second radio frequency carriers and transmitting / receiving in a burst form, and the PLL synthesizer responds to a control voltage with an arbitrary frequency. A voltage-controlled oscillator for generating a local oscillation signal, a frequency division ratio data signal from the frequency control means for instructing a frequency division ratio, and a data setting signal for activating the frequency division ratio data signal. Variable frequency dividing means for dividing the oscillation signal to generate a comparison signal, reference oscillation means for generating a reference signal of a reference frequency, and a phase difference signal in response to a phase difference between the comparison signal and the reference signal. A phase comparison means for generating and generating a control signal, a low-pass filter means for integrating the control signal and supplying it as the control voltage to the voltage controlled oscillation means, and the phase A wireless system comprising: an unlock alarm generating means for generating an unlock alarm from a signal; and an unlock alarm prohibiting means for controlling the unlock alarm generating means to prohibit generation of the unlock alarm for a predetermined time. Transceiver. 6. The wireless transceiver according to claim 5, wherein the prohibition of the unlock alarm is initiated in response to the data setting signal. 7. The wireless transceiver for TDMA communication system, wherein the wireless transceiver is capable of selectively setting the timing of turning on the first and second radio frequency carriers and the frequencies of these carriers, The wireless transceiver according to claim 5, wherein the alarm generation prohibited period is set shorter than a period in which the first and second radio frequency carriers are not in an ON state. 8. A transmitting means for transmitting a first radio frequency carrier modulated by an information signal to be transmitted via an antenna, and a second radio frequency carrier modulated by an information signal to be received by the antenna. A local oscillation signal having a frequency having a predetermined relationship with the first and second frequencies, including a receiving means for receiving via a phase locked loop (PLL), is commonly supplied to the transmitting means and the receiving means. PLL synthesizer, alarm display means for displaying a device alarm in response to a display control signal, and frequency for controlling the transmitting means, the receiving means and the PLL synthesizer so as to switch the frequencies of the first and second radio frequency carriers. A wireless transceiver comprising a control means and a display control means for supplying the display control signal, wherein: The transmitting means is a TDMA-compliant transmitting / receiving means for ON / OFF controlling the first and second radio frequency carriers and transmitting / receiving in a burst form, and the PLL synthesizer responds to a control voltage with an arbitrary frequency. A voltage-controlled oscillator for generating a local oscillation signal, a frequency division ratio data signal from the frequency control means for instructing a frequency division ratio, and a data setting signal for activating the frequency division ratio data signal. Variable frequency dividing means for dividing the oscillation signal to generate a comparison signal, reference oscillation means for generating a reference signal of a reference frequency, and a phase difference signal in response to a phase difference between the comparison signal and the reference signal. A phase comparison means for generating a control signal and a control signal, a low-pass filter means for integrating the control signal and supplying it as the control voltage to the voltage controlled oscillating means, Pulse generating means for generating a gate pulse signal having a predetermined width in response to a setting signal; gate means for generating an output pulse signal by gated on the phase difference signal in response to the gate pulse signal; And a pulse detecting means for generating an unlock alarm signal in response to the signal. 9. The pulse detection means generates the unlock alarm signal which goes to a high level with a constant time constant when the output pulse signal is not detected and immediately goes to a low level when the output pulse signal is detected. 9. The wireless transceiver according to claim 8, wherein 10. The pulse detection means comprises: an FET having a gate serving as an input terminal for the output pulse signal and a source grounded; a cathode connected to the drain of the FET and an anode serving as an output terminal for the unlock alarm signal. 9. The wireless transceiver according to claim 8, further comprising: a diode connected between the anode of the diode and the ground, and a resistor connected between a positive power supply and the anode of the diode. Machine. 11. A P that produces a high frequency output having a frequency that varies in response to a frequency control signal including a phase locked loop.
In an LL synthesizer, an unlock alarm generating means for generating an unlock alarm in response to loss of synchronization of the phase locked loop, and prohibiting generation of the unlock alarm for a predetermined period immediately after frequency switching by the frequency control signal. And an unlocking alarm prohibiting means.
LL synthesizer. 12. The frequency control signal includes a frequency designation signal that designates a frequency of the local oscillation signal, and a data setting signal that is supplied after the frequency designation signal and activates the frequency designation signal. The PLL synthesizer according to claim 11, characterized in that. 13. The PLL synthesizer according to claim 12, wherein the prohibition of the unlock alarm generation is started in response to the data setting signal. 14. A voltage controlled oscillator for generating a local oscillation signal of an arbitrary frequency in response to a control voltage, a frequency division ratio data signal for instructing a frequency division ratio from said frequency control means, and said frequency division ratio data signal. Variable dividing means for dividing the local oscillation signal to generate a comparison signal in response to a data setting signal for activating, a reference oscillation means for generating a reference signal of a reference frequency, the comparison signal and the Phase comparison means for generating a phase difference signal and a control signal in response to a phase difference with a reference signal; and low-pass filter means for integrating the control signal and supplying the control voltage to the voltage controlled oscillation means. An unlock alarm generating means for generating an unlock alarm from the phase difference signal; and controlling the unlock alarm generating means to generate the unlock alarm for a predetermined time. A PLL synthesizer comprising: an unlock alarm prohibiting means for prohibiting only the above. 15. The PLL synthesizer according to claim 14, wherein the prohibition of the unlock alarm generation is started in response to the data setting signal. 16. A voltage controlled oscillator for generating a local oscillation signal of an arbitrary frequency in response to a control voltage, a frequency division ratio data signal indicating a frequency division ratio from said frequency control means, and said frequency division ratio data signal. Variable dividing means for dividing the local oscillation signal to generate a comparison signal in response to a data setting signal for activating, a reference oscillation means for generating a reference signal of a reference frequency, the comparison signal and the Phase comparison means for generating a phase difference signal and a control signal in response to a phase difference with a reference signal; and low-pass filter means for integrating the control signal and supplying the control voltage to the voltage controlled oscillation means. Pulse generation means for generating a gate pulse signal having a predetermined width in response to the data setting signal, and an output pulse signal for gated the phase difference signal in response to the gate pulse signal. A PLL synthesizer comprising: gate means for generating a signal; and pulse detecting means for generating an unlock alarm signal in response to the output pulse signal. 17. The pulse detection means generates the unlock alarm signal which goes to a high level with a constant time constant when the output pulse signal is not detected and immediately goes to a low level when the output pulse signal is detected. The PLL synthesizer according to claim 16, characterized in that 18. The pulse detection means comprises: a FET having a gate serving as an input terminal for the output pulse signal and a source grounded; a cathode connected to a drain of the FET and an anode serving as an output terminal for the unlock alarm signal; 18. The PL according to claim 17, further comprising: a diode connected to the diode, a capacitor connected between the anode of the diode and the ground, and a resistor connected between a positive power supply and the anode of the diode.
L synthesizer.