JPH0537785A - Coding method for definite bit picture - Google Patents

Abstract

PURPOSE:To improve the compression rate when a definite bit picture is coded by detecting coincidence/dissidence between a coded picture element and a surrounding picture element and coding the picture depending on the detection. CONSTITUTION:A picture data signal 100 (4 bits) inputted from a picture input means 10 is inputted to a line memory 12, in which several lines of data are stored. A coincidence detection circuit 11 discriminates to which picture element of surrounding picture elements the coded picture element is coincident and outputs a 2-bit signal 102. The discrimination is implemented for scanning of all pattern to obtain a data of a first half of coding and the result is stored in a memory 15. A bit stream generator 13 collects each bit of a coded picture element around which no coincident picture element is in existence and sends the result to a coding section 14, in which the signal is coded and the result is stored in the memory 15 as a latter half coding data. The stored data is subjected to decode processing by a decoder 16 and the result is displayed on a display device 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is limited to a color image processing apparatus which is limited to the number of colors represented by several bits (for example, 16 colors represented by 4 bits) due to the limitation of the capacity of a digital memory. The present invention relates to a bit image encoding method.

[0002]

2. Description of the Related Art As a conventional image encoding method, a run length encoding method represented by G3 and G4 facsimiles generally recommended by CCITT (International Telegraph and Telephone Consultative Committee) is used. This encoding method counts the length (run length) of white or black pixels,
This is a method of determining a code corresponding to the count value from a code table prepared in advance. The code table used here is characterized by assigning a relatively short code to a long white run which is often found in a document image.

[0003]

By the way, as a method for encoding an image of several bits per pixel, a method in which the above method is applied to each bit plane of several bit images is conceivable. There is a problem that the compression rate does not increase because the correlation information of is not used.

The present invention provides a limited bit image encoding method which eliminates the above-mentioned conventional drawbacks and which efficiently encodes a limited bit image at a high compression rate.

[0005]

In order to solve this problem, a limited bit image encoding method of the present invention is a limited bit image encoding for encoding a limited bit image represented by several bits per pixel. In this method, the match / mismatch between the coded pixel and the surrounding pixels is detected, if there is a matching surrounding pixel, the coding is performed based on the position of the matching pixel, and if there is no matching surrounding pixel, each code is used. Encoding is performed based on the bit of the encoded pixel. Here, the bit-based encoding of each encoded pixel is a predictive encoding for predicting an encoded pixel based on surrounding pixels.

According to the present invention, by detecting the coincidence with the surrounding pixels, and encoding the signal indicating the coincident position and each bit of the pixel value for the non-coincident pixels, the several-bit image can be efficiently displayed. Compress.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an image display device which realizes the encoding method of the present invention. Particularly, in the image display device, the processing by the limited bit is often performed due to the limitation of the capacity of the display digital memory.

The image data signal 100 (4 bits) input from the image input means 10 is stored in the line memory 12 for several lines. The match detection circuit 11 determines which of the surrounding pixels the coded pixel matches with the pixel value. For example, as shown in FIG. 2, "00" if it matches the left neighbor, "10" if it matches the upper left, "01" if it matches directly above, and " A 2-bit signal 102 is output, such as 11 ″. This is scanned for the entire screen and is used as data in the first half of encoding, and is stored in the memory 15 such as a disk.

The bit stream generator 13 collects each bit of coded pixels having no matching pixel around the coded pixel, sends the bit to the coding section 14 using arithmetic code, and codes the latter half of the code. It is stored in the memory 15 as data. The data once accumulated is decoded by the decoder 16 and displayed on the monitor of the display unit 17 or the like.

FIG. 3 shows the structure of the coded data. The first half of the coded data of one image is the result of matching judgment with surrounding pixels for all images, and the latter half is when there is no matching pixel in the surroundings. The encoded data of each bit of the encoded pixels of

FIG. 4 shows a schematic flow chart of the encoding procedure of this embodiment. First, in step S1, a matching pixel is detected, and in step S2 the result is output. Step S
In 3, the encoding is performed for each bit only for pixels that do not match. Next, in step S4, the coding result is output.

The respective constituent elements of FIG. 1 will be described in more detail below with reference to FIGS.

FIG. 5 is a block diagram of the coincidence detection circuit 11 with the surrounding pixels. The line memory 12 outputs the data 101 of the three pixels 41 surrounding the pixel of interest 40, and these are compared with the original signal by the comparators 42a to 42c. Decision circuit 4
3, the match signal 10 is output from the outputs of the comparators 42a to 42c.
Generates 2. Here, there is a possibility that a plurality of pixel values may match, so that priorities are set in the order of, for example, left-neighboring> right above> upper-left. When the left-hand side and the right-hand top match, the left-hand side match signal "00" is output, and when the left-hand side and the right top match, the right-hand top match signal "01" is output.

FIG. 6 is a block diagram of the encoding unit 14.
The 4-bit signal 103 of the encoded pixel having no corresponding surrounding pixel from the bit stream generator 13 enters the parallel-serial conversion circuit 60 and is sent to the encoding circuit 62 in 1-bit units. At the same time, a signal 120 indicating what the bit number of the original signal is is sent to the prediction state determination circuit 61.

FIG. 7 is a block diagram of the prediction state determination circuit.

The data buffer 70 (70-0 to 70-
3) is bit 0 of the signal 104 from the line memory 12.
~ For each bit plane divided into bit 3, it is possible to refer to the surrounding 7 pixels. The information of 7 pixels is input to the selector 71 and switched by 2 bits of the signal 120.

Further, the coded pixel data of interest 72 is encoded.
(72-3 to 72-1) is passed through the gate portion 73. When the encoding bit is the first (bit 3), all are "0".
At the time of the second (bit 2), only bit 3 is valid and the subsequent "0" is set, and at the time of the third (bit 1), bit 3 and bit 2 are valid and the subsequent "0" is set and the fourth (bit 0). ), All bits are valid. The above 7 + 3 = 10 bits are output to the encoding circuit 62 as the signal 123.

By the above operation, each coded bit refers to the same bit of its surrounding pixels by 7 bits, and from the second bit onward, the bit of the coded pixel which has already been coded is referred to determine the prediction state. You are doing it.

FIG. 8 is a block diagram of the dynamic arithmetic encoder included in the encoding circuit 62, and 80 stores the index indicating the state corresponding to the signal 123 output from the prediction state determining circuit 61. Prediction state memory 81 is an arithmetic parameter RO for outputting the probability P of the inferior symbol according to the index value output from the prediction state memory 80.
M and 83 are arithmetic encoders that dynamically perform arithmetic encoding based on the probability P output from the arithmetic parameter ROM 81 and the dominant symbol MPS and the encoded symbol Xn, and 82 is a match / mismatch between the dominant symbol MPS and the encoded symbol Xn. Is a prediction updater for updating the value of the prediction state memory 80 based on the signal YN.

The signal LS is a signal indicating the final bit of the encoded signal, and is given to the arithmetic encoder from a controller (not shown). Further, the signal NS is given to the buffer controller as a request signal for the next coded symbol.

FIG. 9 shows an example of data stored in the arithmetic parameter ROM 81 and the UPDATE ROM in the prediction updater 82.

FIG. 10 is a block diagram of the arithmetic encoder 83 shown in FIG. Reference numeral 125 is a subtractor, 126a to 126c are multipliers, 127a to 127b are selectors, and 128a and 12a.
Reference numeral 8b is a latch (in the following flow, 128a is described as a 16-bit register A, 128b is described as a 17-bit register C), 129 is a comparator, 130 is a code output device, and 131 is an adder. Incidentally, the arithmetic encoder 8 of FIG.
The operation of No. 3 will be described in detail below according to the flow chart.

The encoding is performed with the above configuration, and its operation will be described below with reference to the flow charts of FIGS. In the following flow charts, the flow of operation is emphasized, not the correspondence with the details of the above configuration.

In the ENCODE subroutine, first, in step 11, the initial set is performed, and the process jumps to the INIT subroutine (FIG. 12). In the INIT subroutine, in step S111, the register C, the buffer B, and the counter SC are "0", the register A is "FFFF" (HEX), and the flag ST is set.
The FLG is set to "1" and the CT is set to "11", and the process returns to FIG. Next, in step S12, the encoded symbol Xn is read out, and in step S13, the ENCODE routine (see FIG.
Fly to 3).

In the ENCODE subroutine, the index is read from the prediction state memory 80 and the arithmetic parameter P is determined in step S131. Next, step S
At 132, the register A is multiplied by the arithmetic parameter P to obtain A1.
And subtract A1 from A to obtain A0. Next, in step S133, Xn and MPS are compared, and Xn and MPS are compared.
When the values match (when the predictions match), step S13
Proceed to 4 and substitute A into A0. A at step S135
If the MSB (most significant bit) of is 0, step S1
At 36, the index is updated according to the NMPS table, and at step S137, the RENORME subroutine (FIG. 14) is reached.

When Xn and MPS do not match, the process proceeds to step S138, C0 is added with A0 to update C, and A
Substitute 1 for A. When the switch corresponding to the index is "1" in step S139, step S139 is executed.
The MPS is inverted at 140. The update of the index value follows the NLPS table as in step S141, and jumps to the RENORME subroutine (FIG. 14) in step S142.

In the RENORME subroutine of FIG. 14, the MSB of the register A in steps S145 and S146.
A and C are left-shifted until is "1", and the counter CT is decremented. When CT reaches 0, the process proceeds from step S147 to step S148 to jump to the BYTEOUT subroutine (FIG. 15).

In the BYTEOUT subroutine, in step S151, the 19th bit to the 28th bit of C are selected.
Extract to temp register. If temp is larger than "FF" X (if carry is present at the 27th bit), the process proceeds from step S152 to S153, where the value of the BUFFER register is incremented by "1" and the OUTPUT subroutine (Fig. 1).
Fly to 6).

In the OUTPUT subroutine, step S
At 165, it is determined whether STFLG is "1". When it is "1", STFLG = 0 is changed, and the process returns to (FIG. 15). This is a process for invalidating only the first OUTPUT process because the initial value of the C register is input.
After the second time, 1-byte data is output to the outside (file, line) and the process returns to FIG.

If SC is not 0, step S15
4, SC "00" X is output in S155. next,
At step S156, the lower 8 bits of temp are set to the register BU.
Write to FFER.

On the other hand, if temp is "FF" X, the flow advances from step S157 to S162 to increment the counter SC. If temp is less than "FF", step S
The process proceeds from S157 to S158 and jumps to the OUTPUT subroutine (FIG. 16). Next, steps S159 and S160.
Output SC of "FF". And step S161
Write the lower 8 bits of temp to register BUFFER. Next, in step S163, the bit output in the C register is cleared, and CT is returned to 8. The processes of steps S12 to S14 are repeated until all the pixels are completed, and when the process of the final pixel is completed, the process proceeds from step S14 to S15 to jump to the FLUSH subroutine (FIG. 17).

In the FLUSH subroutine, the code remaining in the C register is finally output. First, step S17
Te the upper 16 bits from the calculation result of (C + A-1)
If it is taken out to mp and temp is C or less, step S172
To S173, add "8000" X to temp and C
And If not, proceed to step S174.
Substitute C for temp.

Then, in step S175, C is left-shifted by the CT bit. If C is larger than "7FFFFFF", the process proceeds from step S176 to S177 and BUFFE.
Add 1 to R and jump to the OUTPUT subroutine. Next, in steps S178 and S179, SC "00" X are output. If C is smaller than "7FFFFFF", the process proceeds from step S176 to S180 and BUFFE.
The contents of R are output and "F" is output in steps S181 and S182.
Then, SC "F" X are output. Finally, in step S183, the 19th bit to the 11th bit of the C register are output and the process returns to Fig. 11. The above process is repeated until the final pixel is encoded.

As described above, by providing the means for detecting the coincidence with the surrounding pixels, the bit stream generating means for synthesizing the signal indicating the coincident position and the original signal, and the means for encoding the bit stream. , It is possible to efficiently compress a few bit images.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0036]

According to the present invention, it is possible to provide a limited bit image encoding method for encoding a limited bit image efficiently and with an increased compression rate.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an image display device that realizes an encoding method of the present invention.

FIG. 2 is a diagram showing an input / output relationship of a coincidence detector.

FIG. 3 is a diagram showing an example of code data of one image.

FIG. 4 is a flowchart of the processing procedure of the code data generator.

FIG. 5 is a block diagram of a match detection circuit.

FIG. 6 is a block diagram of an encoding unit.

FIG. 7 is a block diagram of a prediction state determination circuit.

FIG. 8 is a block diagram of an encoding circuit.

FIG. 9: UP in arithmetic parameter ROM and prediction updater
It is a figure which shows the content of DATE ROM.

FIG. 10 is a block diagram of an arithmetic encoder.

FIG. 11:

FIG. 17 is a flowchart of an encoding procedure.

[Explanation of symbols]

10 ... Image input means, 11 ... Match detection circuit, 12 ... Line memory, 13 ... Bit stream generator, 14 ... Encoding section, 15 ... Memory, 16 ... Decoder, 17 ... Display

Claims (2)

[Claims] 1. A limited bit image encoding method for encoding a limited bit image represented by a few bits per pixel, the method comprising: detecting a match / mismatch between a coded pixel and a surrounding pixel; A limited bit image coding method characterized in that if there is a matching pixel, coding is performed based on the position of the matching pixel, and if there is no matching surrounding pixel, coding is performed based on the bit of each coding pixel. 2. The limited bit image encoding according to claim 1, wherein the bit-based encoding of each encoded pixel is a predictive encoding for predicting an encoded pixel based on surrounding pixels. Method.