JPH0537511A - Unique word detection circuit - Google Patents
Unique word detection circuitInfo
- Publication number
- JPH0537511A JPH0537511A JP21276991A JP21276991A JPH0537511A JP H0537511 A JPH0537511 A JP H0537511A JP 21276991 A JP21276991 A JP 21276991A JP 21276991 A JP21276991 A JP 21276991A JP H0537511 A JPH0537511 A JP H0537511A
- Authority
- JP
- Japan
- Prior art keywords
- unique word
- data string
- detection circuit
- word detection
- correlation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/10—Arrangements for initial synchronisation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、連続するフレーム信号
からなるＰＳＫ受信信号に含まれるユニークワードを検
出するユニークワード検出回路に係り、特に受信信号周
波数に大きな誤差がある時のユニークワード検出方式に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unique word detection circuit for detecting a unique word included in a PSK reception signal composed of continuous frame signals, and particularly to a unique word detection system when there is a large error in the reception signal frequency. Regarding
【０００２】[0002]
【従来の技術】本発明が対象とするユニークワード検出
回路は、各フレームの先頭に配置されるユニークワード
を検出する回路であるが、この種のユニークワード検出
回路としては、従来、例えば図２に示すものが知られて
いる。2. Description of the Related Art A unique word detection circuit to which the present invention is directed is a circuit for detecting a unique word placed at the beginning of each frame. As a unique word detection circuit of this kind, a conventional one, for example, FIG. The ones shown in are known.
【０００３】図２において、相関器２１は、ＰＳＫ受信
信号をディジタルサンプルした入力データ列Ｄn ′とユ
ニークワードパターンＵk ′（１≦ｋ≦Ｋ）との相互相
関値Ｃn ′を計算し、それを比較器２２へ出力する。In FIG. 2, a correlator 21 calculates a cross-correlation value C n ′ between an input data string D n ′ obtained by digitally sampling a PSK received signal and a unique word pattern U k ′ (1 ≦ k ≦ K). , And outputs it to the comparator 22.
【０００４】ここで、入力データ列Ｄn ′は、ＰＳＫ受
信信号が直交検波されたものであるので、搬送波位相同
期のとられた複素信号である。そして、入力データ列Ｄ
n ′は、信号成分（即ち、送信信号）Ｓn ′と雑音成分
Ｎn とからなるが、信号成分Ｓn ′には長さＫビットの
ユニークワード（そのビットパターンをＵk ′とする）
が含まれている。今、ユニークワードがｎ＝ｎ0 の時点
まで挿入されているとすると、信号成分とユニークワー
ドとの関係は次の数式２で表せる。Here, the input data sequence D n ′ is a complex signal in which the carrier phase is locked because the PSK received signal is obtained by quadrature detection. Then, the input data string D
n ′ is composed of a signal component (that is, a transmission signal) S n ′ and a noise component N n, and the signal component S n ′ has a unique word of length K bits (the bit pattern is U k ′).
It is included. Now, assuming that the unique word is inserted up to the point of n = n 0 , the relationship between the signal component and the unique word can be expressed by the following mathematical formula 2.
【０００５】[0005]
【数２】 [Equation 2]
【０００６】一方、相関器２１の出力（相互相関値）Ｃ
n ′は次の数式３で表せる。On the other hand, the output (cross-correlation value) C of the correlator 21
n ′ can be expressed by the following Equation 3.
【０００７】[0007]
【数３】 [Equation 3]
【０００８】従って、ｎ＝ｎ0 の時の相互相関値Ｃn0′
は、雑音成分Ｎn を無視すれば、次の数式４で示され、
極大値Ｋをとる。Therefore, the cross-correlation value C n0 ′ when n = n 0
Is given by Equation 4 below, ignoring the noise component N n :
Take the maximum value K.
【０００９】[0009]
【数４】 [Equation 4]
【００１０】そこで、比較器２２では、相互相関値Ｃ
n ′の絶対値│Ｃn ′│と予め定めた閾値Ａ′とを比較
し、│Ｃn ′│≧Ａ′となった時、ｎ＝ｎ0 であると判
定し、ユニークワード検出信号を出力する。Therefore, in the comparator 22, the cross-correlation value C
'comparing the, │C n' threshold A determined in advance and │ 'absolute value ￨C n of' n when he became │ ≧ A ', is determined that the n = n 0, the unique word detection signal Output.
【００１１】[0011]
【発明が解決しようとする課題】上述した従来のユニー
クワード検出回路では、入力データ列Ｄn ′の搬送波同
期がとれていない時、即ち、入力データ列Ｄn ′に周波
数誤差Δｆがある時、相互相関値Ｃn0は、次の数式５と
なり、│Ｃn0′│は極大値とならないので、ユニークワ
ードを検出できない。In the conventional unique word detection circuit described above, when the carrier wave of the input data string D n ′ is not synchronized, that is, when there is a frequency error Δf in the input data string D n ′, The cross-correlation value C n0 is given by the following expression 5, and | C n0 ′ | does not have the maximum value, so that the unique word cannot be detected.
【００１２】[0012]
【数５】 [Equation 5]
【００１３】つまり、従来のユニークワード検出回路で
は、入力データ列Ｄn ′は予め搬送波同期が確立されて
いることが必要である。従って、周波数誤差Δｆが大き
い時には、搬送波同期に相当の時間を要するので、ユニ
ークワードの検出に長時間を要するという問題がある。That is, in the conventional unique word detection circuit, it is necessary that carrier synchronization is established in advance for the input data string D n ′. Therefore, when the frequency error Δf is large, it takes a considerable time to synchronize the carrier wave, and thus it takes a long time to detect the unique word.
【００１４】本発明の目的は、入力データ列に大きな周
波数誤差があるときでも即時にユニークワードの検出を
行うことのできるユニークワード検出回路を提供するこ
とにある。It is an object of the present invention to provide a unique word detection circuit which can immediately detect a unique word even when there is a large frequency error in an input data string.
【００１５】[0015]
【課題を解決するための手段】前記目的を達成するため
に、本発明のユニークワード検出回路は次の如き構成を
有する。即ち、本発明のユニークワード検出回路は、連
続するフレーム信号からなるＰＳＫ受信信号中のユニー
クワード（各フレームの先頭に配置される）を検出する
ユニークワード検出回路であって； このユニークワー
ド検出回路は、フレームの長さをｎF ビット、ユニーク
ワードの長さをＫビットとし、隣接する２つのフレーム
におけるユニークワードの各ビットをＵk 1、Ｕk 2（１≦
ｋ≦Ｋ）としたとき、前記ＰＳＫ受信信号をディジタル
サンプルしたデータ列Ｄn をｎF ビット遅延させたデー
タ列Ｄn-nFを出力する遅延回路と； 前記データ列Ｄn
と前記遅延回路の出力Ｄn-nFとを受けてIn order to achieve the above object, the unique word detection circuit of the present invention has the following configuration. That is, the unique word detection circuit of the present invention is a unique word detection circuit that detects a unique word (arranged at the beginning of each frame) in a PSK reception signal composed of continuous frame signals. Has a frame length of n F bits and a unique word length of K bits, and each bit of the unique words in two adjacent frames is U k 1 , U k 2 (1 ≦
When k ≦ K), a delay circuit for outputting a data string D n- n F obtained by delaying the data string D n obtained by digitally sampling the PSK received signal by n F bits; and the data string D n.
And the output D n-nF of the delay circuit
【００１６】[0016]
【数６】 [Equation 6]
【００１７】で表される相関値Ｃn を出力する相関器
と； 前記相関値Ｃn が予め定められた閾値を越えたと
きユニークワード検出信号を出力する比較器と； を備
えることを特徴とするものである。A correlator that outputs a correlation value C n represented by: a comparator that outputs a unique word detection signal when the correlation value C n exceeds a predetermined threshold value; To do.
【００１８】[0018]
【作用】次に、前記の如く構成される本発明のユニーク
ワード検出回路の作用を説明する。本発明では、データ
列Ｄn をｎF ビット遅延させたデータ列Ｄn-nFと遅延し
ていないデータ列Ｄn との相関をとる。その結果、相関
値の絶対値は周波数誤差の影響を全く受けないものとな
る。Next, the operation of the unique word detection circuit of the present invention constructed as described above will be described. In the present invention, the data string D n-nF obtained by delaying the data string D n by n F bits is correlated with the data string D n which is not delayed. As a result, the absolute value of the correlation value is completely unaffected by the frequency error.
【００１９】従って、本発明によれば、データ列Ｄn に
大きな周波数誤差があるときでも即時にユニークワード
の検出ができる。Therefore, according to the present invention, the unique word can be detected immediately even when the data string D n has a large frequency error.
【００２０】[0020]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図１（ａ）は、本発明の一実施例に係るユニーク
ワード検出回路を示す。本発明では、遅延回路１を設
け、遅延回路１にて遅延した遅延データ列と遅延してい
ない本来のデータ列とを相関器２に入力させるようにし
てある。図１（ｂ）は伝送フレームのフォーマットを示
すが、フレームの長さをｎF ビット、ユニークワードの
長さをＫビットとし、隣接する２つのフレームにおける
ユニークワードの各ビットパターンをＵk 1、Ｕk 2（１≦
ｋ≦Ｋ）とし、以下本発明のユニークワード検出回路の
動作を説明する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows a unique word detection circuit according to an embodiment of the present invention. In the present invention, the delay circuit 1 is provided, and the delayed data string delayed by the delay circuit 1 and the original data string not delayed are input to the correlator 2. FIG. 1B shows the format of a transmission frame. The frame length is n F bits, the unique word length is K bits, and each unique word bit pattern in two adjacent frames is U k 1 , U k 2 (1 ≦
The operation of the unique word detection circuit of the present invention will be described below with k ≦ K).
【００２１】まず、信号成分（送信信号）Ｓn とユニー
クワードとの関係は、２つ目のユニークワードＵk 2の最
終ビットの時刻をｎ＝ｎ0 とすると、次の数式７、同８
と表せる。First, regarding the relationship between the signal component (transmission signal) S n and the unique word, when the time of the last bit of the second unique word U k 2 is n = n 0 , the following equations 7 and 8 are given.
Can be expressed as
【００２２】[0022]
【数７】 [Equation 7]
【００２３】[0023]
【数８】 [Equation 8]
【００２４】また、周波数誤差Δｆを持つ入力データ列
Ｄn は、次の数式９で表せる。The input data string D n having the frequency error Δf can be expressed by the following equation 9.
【００２５】[0025]
【数９】 [Equation 9]
【００２６】遅延回路１は、入力データ列Ｄn をｎF ビ
ット遅延させるので、相関器２は遅延データ列Ｄn-nFと
入力データ列Ｄn との相関をとり、前記数式６で表され
る相関値Ｃn を出力する。Since the delay circuit 1 delays the input data sequence D n by n F bits, the correlator 2 correlates the delay data sequence D n-nF with the input data sequence D n and is expressed by the above equation (6). And outputs a correlation value C n .
【００２７】ここで、数式６に同９を代入すると、次の
数式１０のようになる。Here, by substituting the same 9 into the equation 6, the following equation 10 is obtained.
【００２８】[0028]
【数１０】 [Equation 10]
【００２９】そして、ｎ＝ｎ0 のときは、数式１０に前
記数式７、同８を代入すると、Ｃn0は次の数式１１とな
る。When n = n 0 , substituting the equations 7 and 8 into the equation 10, C n0 becomes the following equation 11.
【００３０】[0030]
【数１１】 [Equation 11]
【００３１】すると、比較器３は、前述したように相関
値Ｃn の絶対値│Ｃn │と予め定められた閾値Ａとの大
小関係を比較し、│Ｃn │≧Ａの時、ｎ＝ｎ0 と判定し
て、ユニークワード検出信号を出力するが、│Ｃn0│＝
Ｋであるから、周波数誤差があってもそれとは無関係に
確実に、且つ、即時にユニークワードを検出できる。Then, the comparator 3 compares the absolute value | C n | of the correlation value C n with the predetermined threshold value A as described above, and when | C n | ≧ A, n is satisfied. = N 0 , a unique word detection signal is output, but | C n0 | =
Since it is K, even if there is a frequency error, the unique word can be detected reliably and immediately regardless of it.
【００３２】[0032]
【発明の効果】以上説明したように、本発明のユニーク
ワード検出回路によれば、入力データ列Ｄn をｎF ビッ
ト遅延させた遅延データ列Ｄn-nFと遅延していない本来
の入力データ列Ｄn との相関をとり、その相関値の絶対
値が周波数誤差の影響を全く受けないものとなるように
したので、入力データ列Ｄn に大きな周波数誤差がある
ときでも確実且つ即時にユニークワードを検出できる効
果がある。As described above, according to the unique word detection circuit of the present invention, the input data string D n is delayed by n F bits and the delayed data string D n-nF is not delayed from the original input data. Correlation with the column D n is performed so that the absolute value of the correlation value is completely unaffected by the frequency error. Therefore, even when the input data sequence D n has a large frequency error, it can be surely and immediately unique. It has the effect of detecting words.
【図１】図（ａ）は本発明の一実施例に係るユニークワ
ード検出回路の構成ブロック図、図（ｂ）は伝送フレー
ムのフォーマットである。FIG. 1A is a configuration block diagram of a unique word detection circuit according to an embodiment of the present invention, and FIG. 1B is a format of a transmission frame.
【図２】従来のユニークワード検出回路の構成ブロック
図である。FIG. 2 is a configuration block diagram of a conventional unique word detection circuit.
１ 遅延回路 ２ 相関器 ３ 比較器 1 Delay circuit 2 Correlator 3 Comparator
Claims (1)
信信号中のユニークワード（各フレームの先頭に配置さ
れる）を検出するユニークワード検出回路であって；
このユニークワード検出回路は、フレームの長さをｎF
ビット、ユニークワードの長さをＫビットとし、隣接す
る２つのフレームにおけるユニークワードの各ビットを
Ｕk 1、Ｕk 2（１≦ｋ≦Ｋ）としたとき、前記ＰＳＫ受信
信号をディジタルサンプルしたデータ列Ｄn をｎF ビッ
ト遅延させたデータ列Ｄn-nFを出力する遅延回路と；
前記データ列Ｄn と前記遅延回路の出力Ｄn-nFとを受け
て 【数１】 で表される相関値Ｃn を出力する相関器と； 前記相関
値Ｃnが予め定められた閾値を越えたときユニークワー
ド検出信号を出力する比較器と； を備えることを特徴
とするユニークワード検出回路。Claim: What is claimed is: 1. A unique word detection circuit for detecting a unique word (arranged at the beginning of each frame) in a PSK reception signal composed of continuous frame signals;
This unique word detection circuit determines the frame length to be n F
When the bit and the length of the unique word are K bits and each bit of the unique word in two adjacent frames is U k 1 and U k 2 (1 ≦ k ≦ K), the PSK received signal is digitally sampled. A delay circuit that outputs a data string D n-nF by delaying the data string D n by n F bits;
Receiving the data string D n and the output D n-nF of the delay circuit, A correlator that outputs a correlation value C n represented by: a comparator that outputs a unique word detection signal when the correlation value C n exceeds a predetermined threshold value; Detection circuit.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21276991A JPH0537511A (en) | 1991-07-30 | 1991-07-30 | Unique word detection circuit |
| EP92112922A EP0526833B1 (en) | 1991-07-30 | 1992-07-29 | Carrier frequency error detector capable of accurately detecting a carrier frequency error |
| EP96114081A EP0750411B1 (en) | 1991-07-30 | 1992-07-29 | Unique word detector for use in a coherent demodulator |
| AU20663/92A AU656098B2 (en) | 1991-07-30 | 1992-07-29 | Carrier frequency error detector capable of accurately detecting a carrier frequency error |
| DE69233096T DE69233096T2 (en) | 1991-07-30 | 1992-07-29 | Single word detector circuit for use in a coherent demodulator |
| DE69224687T DE69224687T2 (en) | 1991-07-30 | 1992-07-29 | Carrier frequency error detector circuit for accurate detection of a carrier frequency error |
| CA002074889A CA2074889C (en) | 1991-07-30 | 1992-07-29 | Carrier frequency error detector capable of accurately detecting a carrier frequency error |
| US07/921,711 US5276710A (en) | 1991-07-30 | 1992-07-30 | Carrier frequency error detector capable of accurately detecting a carrier frequency error |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21276991A JPH0537511A (en) | 1991-07-30 | 1991-07-30 | Unique word detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0537511A true JPH0537511A (en) | 1993-02-12 |
Family
ID=16628096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21276991A Pending JPH0537511A (en) | 1991-07-30 | 1991-07-30 | Unique word detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0537511A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660561A1 (en) * | 1993-12-23 | 1995-06-28 | STMicroelectronics S.A. | Circuit for recognition of a sequence of words in a modem |
| US6111922A (en) * | 1994-12-20 | 2000-08-29 | Sgs-Thomson Microelectronics S.A. | Circuit for detecting word sequences in a modem |
| EP1237319A1 (en) * | 2001-02-26 | 2002-09-04 | Juniper Networks, Inc. | Methods and apparatus for efficient and accurate coarse timing synchronization in burst demodulators |
| JP2003244763A (en) * | 2002-02-14 | 2003-08-29 | Ntt Docomo Inc | Mobile communication system, channel synchronization establishing method, and mobile station |
| USRE38391E1 (en) | 1993-12-23 | 2004-01-20 | Stmicroelectronics S.A. | Circuit for detecting word sequences in a modem |
| JP2007135230A (en) * | 1995-10-31 | 2007-05-31 | Thomson Multimedia Sa | Method for cascading detachable conditional access modules, circuit for inserting predetermined sequence and circuit for detecting said sequence in order to implement the method |
| WO2010023843A1 (en) | 2008-08-27 | 2010-03-04 | 日野自動車株式会社 | Cross member-integrated trunnion bracket |
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| JPS63196129A (en) * | 1987-02-10 | 1988-08-15 | Matsushita Electric Ind Co Ltd | Spread spectrum communication receiver |
| JPH04346532A (en) * | 1991-05-24 | 1992-12-02 | Kokusai Denshin Denwa Co Ltd <Kdd> | Method and device for frame synchronization |
-
1991
- 1991-07-30 JP JP21276991A patent/JPH0537511A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49114309A (en) * | 1973-02-12 | 1974-10-31 | ||
| JPS63196129A (en) * | 1987-02-10 | 1988-08-15 | Matsushita Electric Ind Co Ltd | Spread spectrum communication receiver |
| JPH04346532A (en) * | 1991-05-24 | 1992-12-02 | Kokusai Denshin Denwa Co Ltd <Kdd> | Method and device for frame synchronization |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE38391E1 (en) | 1993-12-23 | 2004-01-20 | Stmicroelectronics S.A. | Circuit for detecting word sequences in a modem |
| FR2714558A1 (en) * | 1993-12-23 | 1995-06-30 | Sgs Thomson Microelectronics | Circuit for recognizing a sequence of words in a modem. |
| US5661752A (en) * | 1993-12-23 | 1997-08-26 | Sgs-Thomson Microelectronics S.A. | Circuit for detecting word sequences in a modem |
| EP0660561A1 (en) * | 1993-12-23 | 1995-06-28 | STMicroelectronics S.A. | Circuit for recognition of a sequence of words in a modem |
| US6111922A (en) * | 1994-12-20 | 2000-08-29 | Sgs-Thomson Microelectronics S.A. | Circuit for detecting word sequences in a modem |
| JP2007135230A (en) * | 1995-10-31 | 2007-05-31 | Thomson Multimedia Sa | Method for cascading detachable conditional access modules, circuit for inserting predetermined sequence and circuit for detecting said sequence in order to implement the method |
| JP4611967B2 (en) * | 1995-10-31 | 2011-01-12 | トムソン マルチメデイア | Method for cascading removable conditional access modules and a predetermined sequence insertion circuit and detection circuit for executing the method |
| EP1237319A1 (en) * | 2001-02-26 | 2002-09-04 | Juniper Networks, Inc. | Methods and apparatus for efficient and accurate coarse timing synchronization in burst demodulators |
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