JPH0536853U - Gate array - Google Patents

Abstract

(57) [Abstract] [Purpose] To alleviate the inefficiency due to the imbalance between the number of I / O pins, the number of built-in gates, and the number of used gates, and reduce the development cost. [Structure] An input pin 4 is shared by at least two or more functional elements 1 and 2 of a plurality of functional elements 1, 2 and 3 having respective functions provided on one chip, and the input pin 4 is supported. The selector 8 selects the outputs of these functional elements 1 and 2 according to the mode select signal and outputs them to share the output pin 10.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a gate array, and more particularly to a gate array in which one type of gate array has a plurality of functions and can be used for each purpose.

[0002]

[Prior Art]

 Conventionally, from the viewpoint of downsizing the system, making it economical, or shortening the development period, a method has been adopted in which glue logic on the system is collected into one chip by a gate array.

[0003]

[Problems to be solved by the device]

 In this way, the gate array integrated into one chip for the purpose of developing one system uses fewer gates than the number of built-in gates with respect to the ratio of the number of input / output pins, and even when the gate usage rate is extremely low. No, it was inefficient. Also, for the development of multiple systems, the gate array has been designed for each system, so the number of gate array products has increased, and development costs are increased because each gate array requires development costs. there were.

Further, due to the miniaturization of the process due to the recent improvement of the process technology, the chip size becomes smaller and the number of input / output pins will decrease if the number of gates is the same. The rate was declining even further, the number of gate array products was increasing, and development costs tended to increase with the development of multiple systems. An object of the present invention is to provide a gate array which can alleviate the inefficiency due to the imbalance between the number of input / output pins, the number of built-in gates, and the number of used gates and reduce the development cost.

[0005]

[Means for Solving the Problems]

 In the gate array according to the present invention, a plurality of functional elements having respective functions are provided on one chip, the input pin is shared by at least two or more functional elements, and those functional elements corresponding to the input pins are provided. A selector is provided to select and output the output by a select signal.

Further, a plurality of functional elements having respective functions are provided on one chip, and an input pin is shared by at least two or more functional elements, and the input pin and two or more corresponding functions are provided. A conduction selection circuit for electrically connecting the input pin and a predetermined functional element by a switching signal may be provided between the element and the element.

[0007]

[Action]

 In the present invention, among a plurality of functional elements having respective functions provided on one chip, at least two or more functional elements share an input pin, and outputs of these functional elements corresponding to the input pin are provided. Is selected by the selector according to the mode select signal and is output to share the output pin, or the conduction select circuit provided between the selector and the functional element corresponding to the input pin is turned on by the switch signal. By connecting the input pin and a predetermined functional element to each other so that two or more functional elements share the input pin or the input pin also serves as the output pin, the input / output pins for the two or more functional elements are connected. Since it is designed to be shared, the number of used gates increases with respect to the ratio of the number of I / O pins, while increasing the used gate ratio, multiple functions can be added to a single chip. It is possible to produce a gate array with a made.

[0008]

【Example】

 FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a first functional element I composed of several types of LSI, 2 is a second functional element II having a different function from the first functional element I, 3 is a first and second functional element I, Third functional element III having a different function from II, 4 is a first input pin to which an input signal is input, 5 is a second input pin to which an input signal is input, and 6 is a first input pin 4 The first buffer is connected to the output side of the first buffer, the output side of which is connected to the first, second and third functional elements I, II, III 1, 2, 3. Reference numeral 7 is a second buffer connected to the second input pin 5, the output side of which is connected to the first and second functional elements I, II1, II2. 8 is a selector connected to the output sides of the first, second and third functional elements I, II, III 1, 2, 3; 9 is a buffer connected to the output side of the selector 8; 10 is a buffer 9; Output pin connected to the output side of. The gate array of this embodiment is composed of the first functional element I1 to the output pin 10.

Next, the operation of the above embodiment will be described.

For example, when signals α1 and β1 for driving the first functional element I1 are input to the first input pin 4 and the second input pin 5, the signals α1 and β1 are output to the respective functional elements I and II. , 1 and 2, only the signal j1 is input to the functional element III 3 via the buffers 6 and 7. The first functional element I1 operates normally and outputs a signal having a specific purpose to the selector 8, and the other functional elements I, II, and III output a signal having no specific purpose to the selector 8. .. In the selector 8, the signal of the first functional element I1 is output from the selector 8 by the mode select signal set on the substrate on which the gate array is mounted, for example, the mode select signal for outputting the signal of the first functional element I1. It is output to the output pin 10 via 9, and the output signal of the first functional element I1 is output from the output pin 10 to the outside. Further, when the signals α2 and β2 for driving the second functional element II 2 are input to the first input pin 4 and the second input pin 5, the second functional element II2 has a specific purpose. The signal is output to the selector 8, and the selector 8 outputs the signal of the second functional element II2 to the output pin 10 according to the mode select signal. Further, when the signal α3 for driving the third functional element III 3 is input to the first input pin 4, the third functional element III 3 outputs a signal having a specific purpose to the selector 8, 8 outputs the signal of the first functional element I1 or the second functional element II2 to the output pin 10 according to the mode select signal.

As described above, the first input pin is provided for, for example, the three first, second and third functional elements I, II, III 1, 2, 3 having respective functions provided in one chip. 4 are used in common, and the output of these functional elements I, II, III 1, 2, 3 corresponding to the first input pin 4 is selected by the selector 8 according to the mode select signal and output, and the output pin 10 is also output. By sharing them, the first input pin 4 and the output pin 10 for the three functional elements I, II, III 1, 2, 3 can be shared. Therefore, the number of used gates is increased with respect to the ratio of the number of input / output pins 4, 5, 10 and the used gate rate is increased. It is also possible to manufacture a gate array with multiple functions in one chip while increasing the gate usage rate, and the type of gate array to be developed is different from the case of manufacturing a gate array for each function. The number of products has been reduced, the product names have been reduced, and management has become easier.

FIG. 2 is a block diagram showing another embodiment of the present invention. In the figure, 11 is a first functional element I consisting of several kinds of LSIs, 12 is a second functional element II having a different function from the first functional element I11, 13 is an input pin to which an input signal is inputted, 1 4 is a buffer connected to the input pin 13, 15 is a first AND gate provided between the buffer 14 and the first functional element I11, 16 is between the buffer 14 and the second functional element II12 Is connected to the input side of the second AND gate 16, and 18 is connected to the output side of the first and second functional elements I, II 11 and 12. A selector, 19 is a signal line for a switching signal, and is connected to the input side of the first AND gate 15, the input side of the inverter 17, and the selector 18, respectively. The gate array of this embodiment is composed of the first functional element I11 to the signal line 19. Further, the first AND gate 15, the second AND gate 16, the inverter 17, and the signal line 19 are electrically connected to make the input pin 13 and the first functional element I11 or the second functional element II12 conductive by a switching signal. The selection circuit 20 is configured.

Next, the operation of the above embodiment will be described.

For example, when an element drive signal is input to the input pin 13, the element drive signal is input to one input side of each of the first AND gate 15 and the second AND gate 16 via the buffer 14. To be done. On the other hand, when, for example, an ON switching signal set on the substrate on which the gate array is mounted is input to the signal line 19, the switching signal is input to the other input side of the first AND gate 15, The first AND gate 15 is brought into an open conductive state, and the element drive signal is input to the first functional element I11. Then, the first functional element I11 outputs a signal having an operating purpose to the selector 18. Further, the ON switching signal input to the signal line 19 is inverted by the inverter 17 to become an OFF switching signal and is input to the other input side of the second AND gate 16, so that the second switching signal is input. The AND gate 16 is closed and non-conductive, and the element drive signal is not input to the second functional element II12. Further, the ON switching signal input to the signal line 19 is input to the selector 18, and the selector 18 outputs the signal output from the first functional element I 11.

When an OFF switching signal is input to the signal line 19, the switching signal is input to the other input side of the first AND gate 15, so the first AND gate 15 is closed. It becomes non-conductive, and the element drive signal is not input to the first functional element I11. Further, since the OFF switching signal is inverted by the inverter 17 and becomes an ON switching signal and is input to the other input side of the second AND gate 16, the second AND gate 16 is in an open conductive state. The element drive signal is input to the second functional element II12. The second functional element II12 outputs a signal having an operating purpose to the selector 18. Further, the selector 18, which has received the OFF switching signal, outputs the signal output from the second functional element II12.

Also in this embodiment, the input pin 13 is shared by the two first and second functional elements I, II, 11 and 12 each having a function on one chip. In the embodiment shown in FIG. 1, the input signal input to the input pin 4 is input to, for example, three functional elements I, II, III 1, 2, and 3, so that the functional element is not used for a certain purpose. Is also input and the functional element outputs an unnecessary signal, which may cause a problem in the simulation or tester, but in the embodiment shown in FIG. Since the element drive signal, which is the input signal input to pin 13, is not input, only the functional element used for a certain purpose can be operated independently, which causes problems in simulations and testers. There is no.

FIG. 3 is a block diagram showing another embodiment of the present invention.

In the figure, 21 is a first functional element I consisting of several kinds of LSI, 22 is a second functional element II having a function different from that of the first functional element I 21, and 23 is an input signal input or output. An input / output pin for outputting a signal, 24 is a forward-direction buffer provided between the input / output pin 23 and the first functional element I 21, and 25 is an input / output pin 23 and the second functional element II 22. A reverse-direction buffer provided between and is a signal line 26 for input / output switching signals, and is connected to the gates of the buffer 24 and the buffer 25, respectively. The gate array of this embodiment is composed of the first functional element I21 to the signal line 26. Further, the bidirectional buffers 24 and 25 and the signal line 26 constitute a conduction selection circuit 27 for conducting the input / output pin 23 and the first functional element I21 or the second functional element II22 by the input / output switching signal. Has been done.

Next, the operation of the above embodiment will be described.

For example, when an element drive signal is input to the input / output pin 23, the element drive signal is input to the buffer 25, respectively. At this time, when a high / low input / output switching signal set on the substrate on which the gate array is mounted is input to the signal line 26, the input / output switching signal is input to the gate of the buffer 24 and the buffer 24 is opened. Then, the element drive signal is input to the first functional element I21. The high input / output switching signal is also input to the gate of the buffer 25, but the gate receives the signal by inverting the signal, so that the buffer 25 is closed and non-conductive, and the second functional element II22 outputs. The output signal does not affect the input / output pin 23.

When a signal indicating that the second functional element II 22 is operating is output in a state where no element drive signal is input to the input / output pin 23, a low input / output switching signal is input to the signal line 26. Then, even if the input / output switching signal is input to the gate of the buffer 24, the buffer 24 is closed and non-conductive. Further, when the input / output switching signal is input to the gate of the buffer 25, the gate inverts and receives the signal, so that the buffer 25 is opened and the signal output from the second functional element II22 is output. It is output to the input / output pin 23 via the buffer 25, and the input / output pin 23 functions as an output pin.

Therefore, in this embodiment, it is possible to share the input pin 23 with the output pin for the two first and second function elements I and II21, 22 having the respective functions on one chip. It has been done. Therefore, the number of used gates is increased with respect to the ratio of the number of input / output pins, and the used gate ratio is said to have increased. It is also possible to fabricate a gate array with multiple functions on a single chip while increasing the gate rate used.

FIG. 4 is a block diagram showing another embodiment of the present invention.

In the figure, 31 is a first functional element I composed of several kinds of LSIs, 32 is a second functional element II having a function different from that of the first functional element I 31, 33 is a first and second functional element. A third functional element III, 34 having a function different from that of I, II is an input / output pin to which an input signal is input or an output signal is output, and 35 is a forward-direction first element connected to the input / output pin 34. A buffer, 36 is a second forward-direction buffer connected to the input / output pin 34, 37 is a third backward-direction buffer connected to the input / output pin 34, and 38 is a first buffer 35 and a first buffer 35. , A first AND gate provided between the second buffer 36 and the second functional element II 32, and 40, an input / output switching signal. Signal line of the first, second and third It is connected to the gate of § 35, 36 and 37. Reference numeral 41 denotes a signal line for a switching signal, which is connected to the input side of the first AND gate 38 and the input side of the second AND gate 39, respectively.

The gate array of this embodiment is a combination of the embodiments shown in FIGS. 2 and 3, and is composed of the first functional element I31 to the signal line 41.

Next, the operation of the above embodiment will be described.

For example, when an element drive signal is input to the input / output pin 34, the element drive signal is input to the first, second and third buffers 35, 36 and 37, respectively. At this time, when a high input / output switching signal is input to the signal line 40, the input / output switching signal is input to the gates of the first, second and third buffers 35, 36 and 37, respectively. Then, the second buffer 36 is in an open conductive state, and the third buffer 37 is in a closed nonconductive state. Further, when the ON switching signal is input to the signal line 41, the switching signal is input to the input side of the first AND gate 38, the first AND gate 38 is brought into the open conductive state, and the input pin 34 is input. The element drive signal input to the first functional element I31 is input to the first functional element I31 via the first buffer 35 and the first AND gate 38. Further, an ON switching signal is input to the input side of the second AND gate 39, but since it is inverted, the second AND gate 39 is in a closed non-conduction state, and the element drive signal is the second functional element. Not entered in II32. Furthermore, the output signal of the third functional element II I 31 does not affect the input / output pin 34 because the third buffer 37 is closed. Therefore, only the first functional element 31 is operated.

Next, when the element drive signal is input to the input pin 34 and the high input / output switching signal is input to the signal line 40, when the OFF switching signal is input to the signal line 41, Contrary to the above, the first AND gate 38 becomes non-conductive and the second AND gate 39 becomes conductive, so that only the second functional element II32 is operated. Further, when the element drive signal is not input to the input pin 34 and the switching signal is not input to the signal line 41, when a low input / output switching signal is input to the signal line 40, the switching signal is input to the signal line 41. Since this is not done, the first and second AND gates 38 and 39 are both rendered non-conductive, and the first and second functional elements 31, 32I and II do not operate. Further, by inputting a low input / output switching signal to the signal line 40, the first and second buffers 35 and 36 are rendered non-conductive, the third buffer 37 is rendered conductive, and the third function is achieved. The signal output from the element III 33 is output to the input / output pin 34 via the third buffer 37. Therefore, the input / output pin 34 should be shared as an input pin for the first and second functional elements I, II 31, 32, and the input / output pin 34 should function as an output pin for the third functional element III 33. Becomes

[0029]

[Effect of the device]

 INDUSTRIAL APPLICABILITY As described above, the present invention allows at least two or more functional elements among a plurality of functional elements having respective functions provided on one chip to share an input pin, and these functional elements corresponding to the input pins are shared. The selector selects the output according to the mode select signal and outputs it so that the output pin is shared, or the conduction selection circuit provided between these functional elements corresponding to the input pin changes according to the switching signal. By connecting the input pin to a predetermined functional element and sharing the input pin with at least two or more functional elements or sharing the input pin as an output pin. Since it can be shared, the number of gates used increases with respect to the ratio of the number of pins of input / output pins. Function can be manufactured of a gate array having a fewer types of Getoare over the development, an effect that Product name both management and the like is facilitated by fewer it is possible to reduce the development costs for it.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 Functional element I 2 Functional element II 3 Functional element III 4 Input pin 5 Input pin 8 Selector 10 Output pin

Claims (2)

[Scope of utility model registration request] 1. A plurality of functional elements having respective functions provided on one chip, an input pin shared by at least two or more functional elements, and an output mode of these functional elements corresponding to the input pins. A gate array comprising a selector that selects and outputs the selected signal. 2. A plurality of functional elements having respective functions provided on one chip, an input pin shared by at least two or more functional elements, and an input pin and two or more functional elements corresponding thereto. And a conduction selection circuit which is provided between the input pin and a predetermined functional element in response to a switching signal.