JPH0536754A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0536754A JPH0536754A JP19160691A JP19160691A JPH0536754A JP H0536754 A JPH0536754 A JP H0536754A JP 19160691 A JP19160691 A JP 19160691A JP 19160691 A JP19160691 A JP 19160691A JP H0536754 A JPH0536754 A JP H0536754A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- bump
- layer
- copper
- palladium layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、超小型,軽量機器に用
いられる配線基板に半導体素子を直接接続した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element is directly connected to a wiring board used for ultra-compact and lightweight equipment.
【0002】[0002]
【従来の技術】従来、配線基板に半導体素子を直接接続
した半導体装置は、図3に示すように、半導体素子1の
電極2上にバンプ3が形成されており、通常金などの金
属バンプあるいは半田などの合金バンプが使用されてい
る。配線基板4には配線電極5が形成されており、通常
銅電極である。また銅電極上に銅の酸化防止のために、
半田層がめっきあるいはレベラーにより形成されて配線
電極5としている場合もある。バンプ3と配線電極5と
の接続は、バンプ3と相対する位置にメタルマスクにて
クリーム半田6を適量スクリーン印刷し、半導体素子1
を位置合わせし搭載後、リフローあるいは熱圧着してい
る。または配線電極5の表面積が半田層で形成されてい
る場合は、クリーム半田6の印刷は行わず、半田層をリ
フローあるいは熱圧着により溶解させ接続することもあ
る。また、バンプ3が半田の場合も、クリーム半田6を
印刷せず、バンプ3自体を溶解して接続する場合もあ
る。2. Description of the Related Art Conventionally, in a semiconductor device in which a semiconductor element is directly connected to a wiring board, a bump 3 is formed on an electrode 2 of a semiconductor element 1, as shown in FIG. Alloy bumps such as solder are used. A wiring electrode 5 is formed on the wiring board 4 and is usually a copper electrode. Also, to prevent copper oxidation on the copper electrode,
In some cases, the solder layer is formed by plating or a leveler to form the wiring electrode 5. The bump 3 and the wiring electrode 5 are connected to each other by screen-printing an appropriate amount of cream solder 6 with a metal mask at a position facing the bump 3 to form the semiconductor element 1.
After positioning and mounting, reflow or thermocompression bonding is performed. Alternatively, when the surface area of the wiring electrode 5 is formed of a solder layer, the cream solder 6 may not be printed, and the solder layer may be melted and connected by reflow or thermocompression bonding. Even when the bumps 3 are solder, the bumps 3 themselves may be melted and connected without printing the cream solder 6.
【0003】さらには、図4に示すように、配線基板4
の配線電極5として、銅電極7上にニッケルめっき8お
よび金めっき9を施した基板を用いることもある。Further, as shown in FIG.
As the wiring electrode 5, a substrate having a copper electrode 7 plated with nickel 8 and gold 9 may be used.
【0004】[0004]
【発明が解決しようとする課題】しかし、上記図3の構
成では、必ず配線電極5である銅電極と半田が直接接続
するため、使用時に雰囲気中の温度と半導体素子1の自
己発熱などにより時間経過とともに銅電極と半田組成中
のすずの合金化が進み、すずの銅中への拡散により銅電
極に接する半田層に巣が発生するという欠陥があった。
また、配線基板4上に半導体素子1を直接接続している
ため、半導体素子1と配線基板4の膨張率の差が接続部
に直接応力としてかかり、接続信頼性を著しく劣化させ
るという課題が発生していた。However, in the structure shown in FIG. 3, since the copper electrode, which is the wiring electrode 5, is always directly connected to the solder, the temperature in the atmosphere and the self-heating of the semiconductor element 1 may cause a time delay during use. As a result, alloying of the copper electrode with tin in the solder composition progressed, and there was a defect that tin was diffused into the copper to form a nest in the solder layer in contact with the copper electrode.
Further, since the semiconductor element 1 is directly connected to the wiring board 4, a difference in expansion coefficient between the semiconductor element 1 and the wiring board 4 is directly applied to the connection portion as stress, which causes a problem that connection reliability is significantly deteriorated. Was.
【0005】また、図4の構成のすずと銅の合金化を抑
制するために施した銅電極7上のニッケルめっき8およ
び金めっき9は効果的ではあるが、材料費自体も高く、
かつ2種類のめっきのため、工程も複雑であり、コスト
がかかるという課題があった。Further, the nickel plating 8 and the gold plating 9 on the copper electrode 7 for suppressing the alloying of tin and copper in the structure of FIG. 4 are effective, but the material cost itself is high,
Moreover, since there are two types of plating, there are problems that the process is complicated and the cost is high.
【0006】本発明は上記従来の課題を解決するもの
で、簡単な構成で信頼性の向上とコストの低減をはかっ
た半導体装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device having a simple structure with improved reliability and cost reduction.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置は、配線基板の銅電極上にパラジ
ウム層を形成、またはその後半田層を形成した構成によ
る。In order to achieve the above object, a semiconductor device of the present invention has a structure in which a palladium layer is formed on a copper electrode of a wiring board, or a solder layer is formed thereafter.
【0008】[0008]
【作用】上記構成により、配線基板の銅電極と半田はパ
ラジウム層により直接接触せず、かつパラジウムと銅と
すずそれぞれとの拡散速度が著しく遅いために銅層と半
田層の間に従来のような鉛過剰にもとづくもろい巣が発
生せず信頼性の向上がはかれるものである。With the above structure, the copper electrode of the wiring board and the solder are not in direct contact with each other due to the palladium layer, and the diffusion speeds of palladium, copper and tin are extremely slow. The reliability is improved without the generation of fragile nests due to excess lead.
【0009】また、パラジウムは無電解めっきにより簡
単に形成することができ、加熱による表面酸化も少な
く、半田漏れ性も良好であり、ニッケルと金めっき表面
処理システムより材料費自体も安く、かつ工程も単純で
あり、コストの低減をはかれるものである。[0009] Further, palladium can be easily formed by electroless plating, has little surface oxidation by heating, has a good solder leak property, has a lower material cost than the nickel and gold plating surface treatment system, and has a process Is also simple and reduces the cost.
【0010】[0010]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図1は第1の実施例を示し、1,2および3は図
3の従来例と同じであるので説明を省略する。10は銅
電極、11は銅電極10上に形成されたパラジウム層で
ある。すなわち配線電極が銅電極10等の金属電極とパ
ラジウム層11とからなっている。上記のパラジウム層
11の形成により配線基板12上の銅電極10とクリー
ム半田13により形成された半田層はパラジウム層11
により直接は接触せず、銅とすずの拡散による合金化を
防いでいる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment, and since 1, 2, and 3 are the same as the conventional example of FIG. 3, their explanations are omitted. Reference numeral 10 is a copper electrode, and 11 is a palladium layer formed on the copper electrode 10. That is, the wiring electrode is composed of a metal electrode such as the copper electrode 10 and the palladium layer 11. The solder layer formed by the copper electrode 10 and the cream solder 13 on the wiring substrate 12 by the formation of the palladium layer 11 is the palladium layer 11
Prevents direct alloying due to diffusion of copper and tin.
【0011】図2は、第2の実施例を示し、14は半田
バンプである。上記の構成において、半田バンプ14と
銅電極10もパラジウム層11により直接は接触してい
ない。FIG. 2 shows a second embodiment, and 14 is a solder bump. In the above structure, the solder bumps 14 and the copper electrodes 10 are also not in direct contact with each other due to the palladium layer 11.
【0012】なお、パラジウム層11は0.1μm程度
の厚さで十分であり、無電解めっきにより形成できるも
のである。なお、パラジウム層11,クリーム半田13
は少なくともバンプに接する領域に存在すれば役目を果
たす。The palladium layer 11 may have a thickness of about 0.1 μm and can be formed by electroless plating. In addition, the palladium layer 11 and the cream solder 13
Plays a role if it exists at least in the area in contact with the bump.
【0013】[0013]
【発明の効果】以上のように本発明は、配線電極が銅等
の金属電極の上の、少なくともバンプに接する領域にパ
ラジウム層を形成した構成によるので、配線基板の銅電
極と半田はパラジウム層により直接は接触せず、かつパ
ラジウムと銅およびすずそれぞれとの拡散による合金化
が著しく遅いため、半田中の巣の発生がなく、半導体素
子の配線基板上への直接の接続にもかかわらず、きわめ
て信頼性が高く、しかもパラジウム自体酸化しにくく、
半田漏れ性も良好でニッケル,金めっきの置き換えが可
能であり、さらに無電解めっきにより形成できるなど、
材料の構成,製造工程の合理化によりコストの低減がは
かれる半導体装置を提供できる。As described above, according to the present invention, since the wiring electrode has the palladium layer formed on the metal electrode such as copper at least in the region in contact with the bump, the copper electrode and the solder of the wiring board are formed by the palladium layer. Due to the fact that they do not come into direct contact with each other, and because the alloying due to diffusion of palladium and copper and tin respectively is extremely slow, there is no generation of cavities in the solder, and despite the direct connection to the wiring board of the semiconductor element, It is extremely reliable, and palladium itself is difficult to oxidize,
It has good solder leakability, can replace nickel and gold plating, and can be formed by electroless plating.
It is possible to provide a semiconductor device whose cost can be reduced by streamlining the material structure and manufacturing process.
【図1】本発明の第1の実施例であるクリーム半田を用
いた場合の半導体装置の断面図FIG. 1 is a sectional view of a semiconductor device using a cream solder according to a first embodiment of the present invention.
【図2】本発明の第2の実施例である半田バンプを用い
た場合の半導体装置の断面図FIG. 2 is a sectional view of a semiconductor device using a solder bump which is a second embodiment of the present invention.
【図3】従来の半導体装置の断面図FIG. 3 is a sectional view of a conventional semiconductor device.
【図4】図3の従来の半導体装置に用いて配線基板の他
の例の断面図FIG. 4 is a cross-sectional view of another example of a wiring board used in the conventional semiconductor device of FIG.
1 半導体素子 2 電極 3 バンプ 10 銅電極 11 パラジウム層 12 配線基板 13 クリーム半田 14 半田バンプ(バンプ) 1 Semiconductor element 2 electrodes 3 bumps 10 Copper electrode 11 Palladium layer 12 wiring board 13 cream solder 14 Solder bump
Claims (2)
金のバンプを介して接続された半導体素子からなる半導
体装置において、前記配線電極が銅等の金属電極の上
の、少なくとも前記バンプに接する領域に少なくともパ
ラジウム層を形成してなることを特徴とする半導体装
置。1. A semiconductor device comprising a semiconductor element connected to a wiring electrode on a wiring board via a metal or alloy bump, wherein the wiring electrode is in contact with at least the bump on a metal electrode such as copper. A semiconductor device comprising at least a palladium layer formed in a region.
接する領域に半田層を形成してなることを特徴とする請
求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein a solder layer is formed on at least a region of the palladium layer which is in contact with the bump.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19160691A JPH0536754A (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19160691A JPH0536754A (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0536754A true JPH0536754A (en) | 1993-02-12 |
Family
ID=16277438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19160691A Pending JPH0536754A (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0536754A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5969424A (en) * | 1997-03-19 | 1999-10-19 | Fujitsu Limited | Semiconductor device with pad structure |
US6066551A (en) * | 1995-11-15 | 2000-05-23 | Citizen Watch Co., Ltd. | Method for forming bump of semiconductor device |
US6436730B1 (en) * | 1993-10-04 | 2002-08-20 | Motorola, Inc. | Microelectronic package comprising tin copper solder bump interconnections and method for forming same |
US8531157B2 (en) | 2008-02-25 | 2013-09-10 | Iwasaki Electric Co., Ltd. | Charging apparatus having overcharge protection and charging method for the same |
-
1991
- 1991-07-31 JP JP19160691A patent/JPH0536754A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6436730B1 (en) * | 1993-10-04 | 2002-08-20 | Motorola, Inc. | Microelectronic package comprising tin copper solder bump interconnections and method for forming same |
US6066551A (en) * | 1995-11-15 | 2000-05-23 | Citizen Watch Co., Ltd. | Method for forming bump of semiconductor device |
US5969424A (en) * | 1997-03-19 | 1999-10-19 | Fujitsu Limited | Semiconductor device with pad structure |
US6232147B1 (en) | 1997-03-19 | 2001-05-15 | Fujitsu Limited | Method for manufacturing semiconductor device with pad structure |
US8531157B2 (en) | 2008-02-25 | 2013-09-10 | Iwasaki Electric Co., Ltd. | Charging apparatus having overcharge protection and charging method for the same |
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