JPH0536716A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the margin of the etching of a gate electrode and set the thicknesses of the gate oxide film on a low-concentration impurity region of an LDD and the gate oxide film on a channel properly, exchanging them with each other, in a MOSFET where the low-concentration region of the LDD and a gate electrode lies one upon the other. CONSTITUTION:This device has a first insulating film 2 on the surface of a p-type silicon substrate 1, and has a first conductive film 3 in the specified region of the first insulating film 2, and has first impurity regions 4a and 4b on the right and left ares, with the first conductive film 3 between, of a silicon substrate 1, and a second insulating film 5 to cover the first conductive film 3, and has a second conductive film 6, which covers the first conductive film 3 above the second insulating film 5 and extends over the first impurity regions 4a and 4b, and has second impurity regions 7a and 7b higher in impurity concentration than the first impurity regions 4a and 4b a, on the right and left areas sandwiching the second conductive film 6, of the silicon substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOSFET having an LDD structure.

[0002]

2. Description of the Related Art MOSFET having a conventional LDD structure
An example of this will be explained by citing the distribution. The tribute is technical digest, International Electron
Devices Meeting, 1987, pp. 38-41 (Technical Digest, Intern
national Electron Devices M
Meeting, 1987, pp 38-41). The contents will be described with reference to the vertical sectional view shown in FIG.

For example, a film having a thickness of 1 is formed on the surface of the P-type silicon substrate 1.
It has a first insulating film 2 of silicon oxide having a thickness of 5 nm, and has a film thickness of, for example, 0.5 to 1 nm in a predetermined region on the first insulating film 2.
Natural oxide film 9 between them, and has a first conductive film 3 of, for example, phosphorus-doped polycrystalline silicon, and a second insulating film 5 of silicon oxide having a film thickness of, for example, 200 nm is formed on the first conductive film 3.
And has sidewalls 8a and 8b of, for example, silicon oxide on the side surfaces of the first conductive film 3 and the second insulating film 5, and the silicon substrate 1 has first impurity regions 4a and 4b doped with phosphorus.
And arsenic-doped second impurity regions 7a and 7b having an impurity concentration higher than those of the first impurity regions 4a and 4b, and the first impurity regions 4a and 4b and the second impurity region 7 are included.
a, 7b, the first impurity regions 4a, 4b and the second impurity regions 7a, 7b are source and drain regions having an LDD structure, and the first insulating film 2 is a gate oxide film. The conductive film 3 of 1 is a gate electrode, and these form a MOSFET.

The MOSFET having the LDD structure is
Since the first impurity regions 4a and 4b and the first conductive film 3 are overlapped with each other, an M having an ordinary LDD structure with the same gate length is provided.
Compared with OSFET, it has advantages of good hot carrier resistance and large mutual conductance.

[0005]

In the conventional MOSFET having the LDD structure, when etching the first conductive film, the etching is stopped by the natural oxide film sandwiched between the first conductive film and the first conductive film. Since the first conductive film must be left on the impurity region of No. 3, etching with an extremely high selection ratio was required. Further, since the gate oxide film has the same film thickness on the channel and on the first impurity region, there is a problem that the optimum film thickness cannot be set for each.

[0006]

The semiconductor device of the present invention comprises:
A first conductive film is provided on one main surface of the one conductivity type silicon substrate, and a first conductive film is provided in a predetermined region of the first conductive film;
There is a first impurity region of opposite conductivity type on the left and right silicon substrates sandwiching the first conductive film, a second insulating film covering the first conductive film, and a first insulating film on the second insulating film. Covering the conductive film of the first
A second conductive film extending over the impurity region of the second conductive film, and a second impurity region of an opposite conductivity type having a higher impurity concentration than that of the first impurity region is formed on the left and right silicon substrates sandwiching the second conductive film. It is characterized by having.

A method of manufacturing a semiconductor device according to the present invention comprises a step of sequentially forming a first insulating film and a second conductive film on one main surface of a one conductivity type silicon substrate, and a first step using a photoetching method. Patterning the conductive film, forming a first impurity region on the left and right silicon substrates sandwiching the first conductive film by ion-implanting impurities of opposite conductivity type on the entire surface, and the first conductive film. A step of forming a second insulating film that covers the first conductive film, a step of forming a second conductive film over the entire surface, and a photoetching method so as to cover the first conductive film and extend over the first impurity region. Patterning the second conductive film by using the first conductive film and the second conductive film having the impurity concentration higher than that of the first impurity region in the left and right silicon substrates sandwiching the second conductive film by ion-implanting impurities of the opposite conductivity type. And forming a second impurity region. The features.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a vertical sectional view of a first embodiment of the present invention.

A first insulating film 2 of silicon oxide having a film thickness of, for example, 15 nm is formed on the surface of a P-type silicon substrate 1,
Has a first conductive film 3 of polycrystalline silicon doped with phosphorus of 1 × 10 ²⁰ cm ⁻³ and has a film thickness of 200 nm in a predetermined region on the insulating film 2. On the silicon substrate 1, for example, a depth of 200 nm and a concentration of 2 × 10 ¹⁸ c
m ⁻³ phosphorus-doped first impurity regions 4a and 4b, and a second insulating film 5 of, eg, a 10 nm-thickness silicon oxide film so as to cover the first conductive film 3. The first conductive film 3 is covered with the insulating film 5, and the first impurity regions 4a and 4b are formed.
A second layer of polycrystalline silicon having a thickness of, for example, 100 nm and a thickness of, for example, 100 nm and doped with 1 × 10 ²⁰ cm ⁻³ of phosphorus.
And a second impurity region 7a, 7b doped with arsenic having a depth of 250 nm and a concentration of 1 × 10 ²⁰ cm ⁻³ , for example, on the left and right sides sandwiching the second conductive film 6.

The first impurity regions 4a and 4b and the second impurity regions 7a and 7b are source and drain regions, the first insulating film 2 is a gate oxide film, the first conductive film 3 and the first conductive film 3 and The conductive film 6 of 2 is partially electrically connected and is a gate electrode.
ET is formed.

FIG. 2 is a vertical cross-sectional view in the main steps of the manufacturing method for the semiconductor device of the embodiment. 2 and 1
A method of manufacturing the semiconductor device of this embodiment will be described with reference to FIG.

The surface of the P-type silicon substrate 1 is oxidized to form a first insulating film 2 made of, for example, silicon oxide and a first conductive film 3 made of, for example, polycrystalline silicon.
2 is doped into the conductive film 3 and patterned by using a photoetching method to obtain the structure shown in FIG.

Next, phosphorus is ion-implanted into the entire surface to form first ion impurity regions 4a and 4b, and the second insulating film 5 made of, for example, silicon oxide and the second conductive film 6 made of polycrystalline silicon are formed by the CVD method. Are sequentially formed, and second phosphorus is formed by thermal diffusion.
The conductive film 6 is doped to obtain the structure shown in FIG.

Next, the second conductive film 6 is patterned by using a photoetching method to form 7a and 7b on the entire surface to obtain the structure shown in FIG.

FIG. 3 is a vertical sectional view of the second embodiment of the present invention. In this embodiment, the first insulating film 2 is provided only under the first conductive film 3. In addition, the second insulating film 5 and the second conductive film 6 are separated from each other on the side surface of the first conductive film 3 by, for example, a film thickness of 20.
The side wall 8a, 8b of the second conductive film 6 having the side wall 8a, 8b of 0 nm silicon oxide is in contact with the second insulating film 5.
Only the part that contacts b.

In the manufacturing method of the first embodiment, the first conductive film 3 is patterned by using a photoetching method, and then the first insulating film 2 is etched using the first conductive film 3 as a mask. To do. After doping the second conductive film 6 with phosphorus, a silicon oxide film having a thickness of 200 nm is formed by, for example, a CVD method, and anisotropic etching is performed on the silicon oxide to form the side wall 8.
When forming a and 8b and patterning the second conductive film 6 by using the photo etching method, only the region surrounded by the sidewalls 8a and 8b is protected by the photoresist.

In this embodiment, the first impurity regions 4a, 4
Since the insulating film sandwiched between b and the second conductive film 6 is only the second insulating film 5, the resistance of the first impurity regions 4a and 4b is further lowered when the MOSFET is turned on. . Further, since the width of overlap between the first impurity regions 4a and 4b and the second conductive film 6 is determined only by the width of the side walls 8a and 8b, the second conductive film 6 is patterned by photoetching. The accuracy of mask alignment is directly
This has an advantage that the overlapping width between the impurity regions 4a and 4b and the second conductive film 6 is not affected.

[0019]

As described above, according to the present invention, when etching the first conductive film and the second conductive film, the first conductive film and the second conductive film are respectively etched.
Since the etching is stopped by this insulating film and the second insulating film, there is an effect that the margin of etching is larger than that by the natural oxide film. For example, the thickness of the first insulating film is 1
5 nm If the second insulating film has a film thickness of 10 nm, it is 5 nm each when the first conductive film and the second conductive film are etched.
It can be tolerated even if the film thickness is gradually decreased. Natural oxide film is 0.5
Since it is ~ 1 nm, the same film thickness reduction cannot be tolerated.

Since the thickness of the gate oxide film on the first impurity region is determined by the first insulating film and the second insulating film, an appropriate film thickness different from the gate oxide film on the channel is set. It also has the effect of being able to.

When the thickness of the gate oxide film on the first impurity region is increased, the capacitance of the overlap between the gate electrode and the source / drain regions is reduced, and the film of the gate oxide film on the first impurity region is reduced. When the thickness is reduced, the resistance of the first impurity region is reduced when the MOSFET is turned on. For example, assuming that the gate oxide film on the first impurity region is 15 nm and the gate oxide film on the channel is 10 nm, the overlapping capacitance between the gate electrode and the source / drain region is equal to the gate on the first impurity region. When the depletion layer is ignored, it is 67% as compared with the case where the film thickness of the oxide film is the same as the film thickness of the gate oxide film on the channel.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view in the main process for explaining the manufacturing method according to the semiconductor device of the first embodiment of the present invention.

FIG. 3 is a vertical sectional view for explaining a second embodiment of the present invention.

FIG. 4 is a vertical sectional view for explaining a conventional LDD structure MOSFET.

[Explanation of symbols]

1 Silicon substrate 2 First insulating film 3 First conductive film 4a, 4b First impurity region 5 Second insulating film 6 Second conductive film 7a, 7b Second impurity region 8a, 8b Side wall 9 Natural oxide film

Claims (2)

[Claims] 1. A first conductive type silicon substrate having a first surface on a main surface thereof.
An insulating film, a first conductive film is provided in a predetermined region on the first insulating film, and a first conductivity type impurity is provided on the left and right silicon substrates sandwiching the first conductive film. A region, a second insulating film covering the first conductive film, covering the first conductive film on the second insulating film, and extending on the first impurity region. A second conductive film, and the second conductive film having opposite conductivity type second impurity regions having an impurity concentration higher than that of the first impurity region on the left and right silicon substrates sandwiching the second conductive film. Semiconductor device. 2. A first conductive type silicon substrate having a first surface on a main surface thereof.
Sequentially forming the conductive film, and patterning the first conductive film by using a photo-etching method. Left and right sandwiching the first conductive film by ion-implanting impurities of opposite conductivity type into the entire surface. Forming a first impurity region on the silicon substrate; forming a second insulating film covering the first conductive film; forming a second conductive film on the entire surface; Patterning the second conductive film by using a photoetching method so as to cover the first conductive film and extend over the first impurity region; and ion-implanting impurities of opposite conductivity type on the entire surface. Forming a second impurity region having a higher impurity concentration than the first impurity region on the left and right silicon substrates sandwiching the second conductive film. .