JPH0536602A - Crystal growth method of hexagonal crystal semiconductor - Google Patents
Crystal growth method of hexagonal crystal semiconductorInfo
- Publication number
- JPH0536602A JPH0536602A JP18910891A JP18910891A JPH0536602A JP H0536602 A JPH0536602 A JP H0536602A JP 18910891 A JP18910891 A JP 18910891A JP 18910891 A JP18910891 A JP 18910891A JP H0536602 A JPH0536602 A JP H0536602A
- Authority
- JP
- Japan
- Prior art keywords
- crystal
- substrate
- growth
- plane
- grown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は可視発光ダイオードまた
は耐環境素子に使用する六方晶半導体の結晶成長方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for growing a hexagonal semiconductor for use in a visible light emitting diode or an environment resistant device.
【０００２】[0002]
【従来の技術】炭化珪素は広い禁制帯幅を持ち（２．２
〜３．３ｅＶ）、かつｐｎ接合やモス（ＭＯＳ）構造を
容易につくることができる。このため、高温動作素子、
大電力素子、放射線検出器、可視発光素子として期待が
なされている。しかし、工業的な生産が行えない理由
は、結晶成長が難しいという欠点があるためである。2. Description of the Related Art Silicon carbide has a wide band gap (2.2
.About.3.3 eV), and a pn junction or a MOS (MOS) structure can be easily formed. Therefore, the high temperature operating element,
It is expected as a high power device, a radiation detector, and a visible light emitting device. However, the reason why industrial production cannot be performed is that crystal growth is difficult.
【０００３】デバイスをつくるような高品質な結晶は単
結晶基板上にエピタキシャル成長を行うことにより得ら
れる。その方法としては、グラファイト坩堝中にＳｉ融
液を溜めた後、基板を該融液に浸し、坩堝から溶け出し
たカーボンを基板上に析出させるという液相成長（ＬＰ
Ｅ）法、及び、ＳｉとＣの水素化物または塩化物のガス
を基板上に導入し熱分解させ成長させる化学堆積（ＣＶ
Ｄ）法の２通りが主に行われている。しかし、これまで
ＣＶＤ法では発光素子として使用できる程度の結晶が得
られていない。これに対し、ＬＰＥ法ではたとえばＪｐ
ｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．，２６，Ｌ１８１５（１
９７９）に示されているように、螺旋転位による異常成
長が起こり表面モフォロジーが悪くなるという問題があ
った。このような結晶で作成したダイオードは通電中に
特性が劣化するといった問題があった。これを解決する
方法として特開昭６３−１７９５１６号に示されるよう
に基板の方向をずらした基板（以下オフ（ｏｆｆ）基板
と称す）を使うという方法が用いられていた。しかし、
この方法では図３に示すように、膜厚を厚く成長すると
表面に１方向のうねりができ、その後の製造プロセスで
電極パターンがきれいにできず、歩留りが悪かった。ま
た、オフ基板を切り出すとき、オフしない基板より一つ
のインゴットからとれる枚数が少なく、基板表面の研磨
も難しいなどの問題があった。また、結晶欠陥といった
観点から見てもオフ基板が得られるわけではなく、イン
クルージョンの様な大きな結晶欠陥に対しては、オフ基
板でない方が欠陥が広がらないことが判ってきた。High quality crystals for making devices can be obtained by epitaxial growth on a single crystal substrate. As a method for this, a liquid phase growth (LP) in which a Si melt is stored in a graphite crucible, the substrate is immersed in the melt, and carbon melted from the crucible is deposited on the substrate
E) method, and chemical vapor deposition (CV) in which a hydride or chloride gas of Si and C is introduced on the substrate and thermally decomposed and grown.
D) Method 2 is mainly used. However, until now, a crystal that can be used as a light emitting device has not been obtained by the CVD method. On the other hand, in the LPE method, for example, Jp
n. J. Appl. Phys. , 26, L1815 (1
979), there is a problem that abnormal growth due to screw dislocation occurs and the surface morphology deteriorates. A diode made of such a crystal has a problem that its characteristics deteriorate during energization. As a method for solving this, there has been used a method of using a substrate (hereinafter referred to as an off substrate) in which the direction of the substrate is shifted as shown in JP-A-63-179516. But,
In this method, as shown in FIG. 3, when the film was grown thick, undulations were formed in one direction on the surface, the electrode pattern could not be cleaned in the subsequent manufacturing process, and the yield was poor. In addition, when cutting off off-substrates, the number of sheets that can be taken from one ingot is smaller than that of non-off substrates, and it is difficult to polish the substrate surface. Further, from the viewpoint of crystal defects, it is not possible to obtain an off-substrate, and it has been found that, with respect to large crystal defects such as inclusions, the defects do not spread if they are not off-substrates.
【０００４】[0004]
【発明が解決しようとする課題】このように従来の成長
方法で成長した結晶は、基板表面のモフォロジーが悪
く、製品化を行ったとき歩留りを低下させる原因となっ
ていた。The crystal thus grown by the conventional growth method has a poor morphology of the substrate surface, which has been a cause of lowering the yield when the product is commercialized.
【０００５】本発明は上記事情を考慮しなされたもの
で、その目的とするところは、ＳｉＣ結晶において、欠
陥の少なく表面モフォロジーの良好なＳｉＣ結晶の成長
方法を提供することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for growing a SiC crystal having few defects and good surface morphology.
【０００６】[0006]
【課題を解決するための手段】本発明に係る六方晶半導
体の結晶成長方法は、（０００１）面を有する六方晶半
導体基板を用意する工程と、前記基板の主面に線状の凹
凸部を形成する工程と、前記主面に前記基板と同じ結晶
構造の半導体単結晶を成長形成する工程を含むことを特
徴とする。A hexagonal semiconductor crystal growth method according to the present invention comprises a step of preparing a hexagonal semiconductor substrate having a (0001) plane, and a linear uneven portion on the main surface of the substrate. The method is characterized by including a step of forming and a step of growing and forming a semiconductor single crystal having the same crystal structure as the substrate on the main surface.
【０００７】[0007]
【作用】六方晶半導体例えばＳｉＣにおいては、（００
０１）面が最も成長する速度が遅く、そのため成長面を
（０００１）面からずらすとずらした方向に非常に成長
しやすい。このため、従来（０００１）面から数度ずら
した面を使用して成長速度を高くして結晶成長を行って
いた。また、このような成長条件で行った結晶には欠陥
が少ないことが判っていた。しかし、このような成長で
は細かい（０００１）面のステップが多く存在し、これ
が表面モフォロジーを悪くする原因となっている。本発
明では（０００１）面からずらすことなく表面に溝を形
成し、溝の側面から、結晶を成長を行っている。このよ
うにすると、結晶は溝を埋めさらに成長する。また、こ
のようにして成長した結晶の表面は非常に平滑であるこ
とが発明者の実験結果で判った。In a hexagonal semiconductor such as SiC, (00
The growth rate of the (01) plane is the slowest, and therefore, when the growth plane is shifted from the (0001) plane, the growth is very easy. For this reason, the crystal growth has been performed by using a plane that is shifted from the (0001) plane by several degrees and increasing the growth rate. Further, it has been known that crystals grown under such growth conditions have few defects. However, in such growth, there are many fine (0001) plane steps, which causes deterioration of the surface morphology. In the present invention, a groove is formed on the surface without shifting from the (0001) plane, and a crystal is grown from the side surface of the groove. In this way, the crystal fills the groove and grows further. Further, it has been found from the experimental result by the inventor that the surface of the crystal thus grown is very smooth.
【０００８】なお、本発明は従来用いられているグラフ
エピタキシーといわれる方法とはまったく作用の異なる
ものである。グラフエピタキシーでは基板は成長結晶と
はまったく異なった別の結晶か、単結晶ではない基板を
用いて、その表面に水平方向のパターンを形成し、その
構造に沿ってまず優先核を成長させそれを種結晶として
成長をするものである。しかし本方法では優先核の成長
は起こらない。本発明ではＳｉＣにおいては〈０００
１〉方向とそれ以外の方向で結晶成長速度が異なること
を使用しているもので成長がもっとも遅い〈０００１〉
以外の方向に成長を行うようにしている。このようにす
ることにより、もっとも成長の遅い〈０００１〉方向に
垂直な（０００１）面が現れることを使用するものであ
る。従来のオフ基板を使用する方法でも成長速度の差を
利用するがこの場合成長しやすい（０００１）面は基板
の表面とはある角度を有している。このため、オフ基板
では基板の表面にうねりを生じることとなる。このよう
に、平滑な面をつくる為には、（０００１）面上に成長
を行わなくてはならない。本発明はこの（０００１）面
上に成長し、且つ成長速度の面依存性を利用するといっ
た従来互いに矛盾することを実現使用とするものであ
る。The present invention has a completely different action from the conventionally used method called graph epitaxy. In graph epitaxy, the substrate is a different crystal from the grown crystal, or a substrate that is not a single crystal, is used to form a horizontal pattern on its surface, and preferential nuclei are grown first along the structure. It grows as a seed crystal. However, this method does not cause the growth of priority nuclei. In the present invention, in SiC, <000
It uses the fact that the crystal growth rate is different between the 1> direction and the other directions, and the slowest growth <0001>
We try to grow in other directions. By doing so, it is used that the (0001) plane perpendicular to the <0001> direction, which has the slowest growth, appears. The conventional method using an off-substrate also utilizes the difference in growth rate, but in this case, the (0001) plane where growth is likely to occur has an angle with the surface of the substrate. Therefore, in the off-substrate, the surface of the substrate is wavily formed. Thus, in order to form a smooth surface, it is necessary to grow on the (0001) plane. The present invention realizes and uses the conventional contradictions of growing on the (0001) plane and utilizing the plane dependence of the growth rate.
【０００９】[0009]
【実施例】以下、本発明の実施例について説明する。図
１に本発明に使用する基板を断面図で示す。基板１はア
チソン法で作製された基板を用い、（０００１）面に平
行に研磨する。その後、（１１２０）または（１１０
０）方向に表面をダイアモンドの針で表面に線を切るこ
とによって溝１１が形成された基板（０００１）面１ａ
が形成される。その後、Ｓｉ融液を溶媒とした液相エピ
タキシャル（ＬＰＥ）法により表面に結晶を成長させ
る。ＬＰＥの成長法は以下のように行う。まず、グラフ
ァイト製の坩堝にシリコンを収容し高周波で加熱する。
グラファイト坩堝には温度差を設け、低温部にＳｉＣ基
板を浸す。そして、成長温度は１６５０℃、成長雰囲気
はＡｒで行った。EXAMPLES Examples of the present invention will be described below. FIG. 1 is a sectional view showing a substrate used in the present invention. As the substrate 1, a substrate manufactured by the Acheson method is used, and is polished parallel to the (0001) plane. After that, (1120) or (110
The substrate (0001) surface 1a in which the groove 11 is formed by cutting the surface in the 0) direction with a diamond needle.
Is formed. Then, a crystal is grown on the surface by a liquid phase epitaxial (LPE) method using a Si melt as a solvent. The growth method of LPE is performed as follows. First, silicon is housed in a graphite crucible and heated at high frequency.
A temperature difference is provided in the graphite crucible, and the SiC substrate is immersed in the low temperature portion. The growth temperature was 1650 ° C. and the growth atmosphere was Ar.
【００１０】図２に、基板１上に溝１１を形成し５μｍ
程度に薄く成長させた時の表面写真を模写して示す。溝
の縁から成長した結晶は表面が非常に平滑であり、さら
に膜厚を厚くすると表面に何の模様も見られなくなっ
た。また、図３には基板主面に設けられた凹凸部のう
ち、凸部（畝）２１が前記図２におけると同様に示され
ている。これは、従来技術の（０００１）よりずらした
面上に成長させた時に比較して非常に表面状態の改善が
はかられた結果である。また、この結晶を用いることに
より製品の歩留りが大幅に改善された。In FIG. 2, a groove 11 is formed on the substrate 1 to form a groove of 5 μm.
A photo of the surface when grown to a thin thickness is shown. The crystal grown from the edge of the groove had a very smooth surface, and when the film thickness was further increased, no pattern was seen on the surface. Further, in FIG. 3, among the concave and convex portions provided on the main surface of the substrate, the convex portion (ridge) 21 is shown in the same manner as in FIG. This is a result of the remarkable improvement of the surface state as compared with the case of growing on the surface shifted from (0001) in the conventional technique. In addition, the yield of products was significantly improved by using this crystal.
【００１１】本発明は上記実施例に限らない。本実施例
では（０００１）面上にダイアモンドの針を用いて溝を
形成したが、溝はエッチング法により形成することもで
きる。特にこの場合溝の幅や成長する方位の制御が容易
になり、膜の制御が容易になる。また、このとき、反応
性イオンエッチング（ＲＩＥ）等の気相エッチング法を
用いることにより容易に溝の形を制御することができ、
その結果成長する結晶の特性も良くなる。The present invention is not limited to the above embodiment. In this embodiment, the groove is formed on the (0001) plane by using a diamond needle, but the groove may be formed by an etching method. In this case, in particular, it becomes easy to control the width of the groove and the growing direction, and the film can be easily controlled. At this time, the shape of the groove can be easily controlled by using a vapor phase etching method such as reactive ion etching (RIE).
As a result, the characteristics of the growing crystal are improved.
【００１２】次に、前記本実施例では成長は液相法によ
って実施したが、昇華法のような気相法で成長した時も
単結晶化率の向上がはかられた。また、ＣＶＤ法に本発
明を用いた場合、結晶中の欠陥が大幅に低下することが
発明者等の研究により判明した。Next, although the growth was carried out by the liquid phase method in the present embodiment, the single crystallization rate could be improved even when the growth was carried out by the vapor phase method such as the sublimation method. Further, it has been found by the study of the inventors that when the present invention is used for the CVD method, the defects in the crystal are significantly reduced.
【００１３】また、溝の方向はどちらの方向に向いても
よいが、（１１２０）または（１１００）方向に刻んだ
ときが最もきれいな成長を行える。本発明は（０００
１）方向のＳｉ面、Ｃ面いずれの場合も同じ効果を有す
る。The groove may be oriented in either direction, but the finest growth can be obtained when the groove is carved in the (1120) or (1100) direction. The present invention is (000
The same effect can be obtained in both cases of Si plane and C plane in the 1) direction.
【００１４】さらに、本発明を使用して成長する結晶は
ＳｉＣだけではない。結晶形が同じ六方晶溝造を有し、
格子定数の近い結晶を成長する時にも有効である。特
に、ＡｌＮ、ＧａＮは格子常数が近く、非常に有利であ
る。図４に本発明を用いＳｉＣ上にＧａＮのＭＩＳ発光
ダイオードを成長形成したものを例示する。図中、１は
ＳｉＣ基板で、その主面は溝が形成された（０００１）
面１ａである。前記（０００１）面にはＧａＮエピ層２
が形成され、これに設けられた一方の電極４ａと、前記
ＧａＮエピ層２にＺｎドープＧａＮ層３を介して設けら
れた他方の電極４ｂが夫々形成されている。この実施例
によって従来の発光ダイオードに比し発光光度が２倍を
超える発光ダイオードが得られた。なお、図中の６は電
極を導出するボンディングワイヤである。Moreover, SiC is not the only crystal grown using the present invention. The crystal form has the same hexagonal groove structure,
It is also effective when growing a crystal having a close lattice constant. In particular, AlN and GaN have very close lattice constants and are very advantageous. FIG. 4 illustrates an example in which a GaN MIS light emitting diode is grown and formed on SiC using the present invention. In the figure, 1 is a SiC substrate, and a groove is formed on its main surface (0001)
It is the surface 1a. GaN epi layer 2 is formed on the (0001) plane.
Is formed, and one electrode 4a provided on this is formed, and the other electrode 4b provided on the GaN epi layer 2 via the Zn-doped GaN layer 3 is formed. According to this example, a light emitting diode having a luminous intensity more than double that of the conventional light emitting diode was obtained. In the figure, 6 is a bonding wire for leading out the electrode.
【００１５】その他、本発明はその主旨に反しない限り
種々変形して使用することができる。In addition, the present invention can be used by being variously modified without departing from the spirit of the invention.
【００１６】[0016]
【発明の効果】本発明によれば、ＳｉＣ単結晶をＳｉＣ
基板上に成長させた場合に表面状態が悪くなる欠点が解
消され、発光効率のすぐれた発光ダイオードが得られ
る。その結果製品の歩留まりが大幅に向上し、その結
果、製品の製造原価が大幅に低下する顕著な効果があ
る。According to the present invention, a SiC single crystal is formed into SiC.
A defect that the surface condition is deteriorated when grown on a substrate is solved, and a light emitting diode having excellent luminous efficiency can be obtained. As a result, the yield of the product is significantly improved, and as a result, the manufacturing cost of the product is significantly reduced, which is a remarkable effect.
【図１】本発明による基板の形状を説明するための断面
図。FIG. 1 is a sectional view for explaining the shape of a substrate according to the present invention.
【図２】溝上に５μｍ程度成長させた時の表面状態を示
す断面図。FIG. 2 is a cross-sectional view showing a surface state when grown on a groove by about 5 μm.
【図３】従来方法による成長の表面状態を示す図。FIG. 3 is a diagram showing a surface state of growth by a conventional method.
【図４】本発明によるＳｉＣ上を用いて形成されたＧａ
ＮのＭＩＳ発光ダイオードの断面図。FIG. 4 Ga formed using on SiC according to the present invention
Sectional drawing of N's MIS light emitting diode.
１ ＳｉＣ基板 １ａ 溝が形成された（０００１）面 ２ ＧａＮエピ層 ３ ＺｎドープＧａＮ層 ４ Ａｌ電極 ５ ボンディングワイヤ 1 SiC substrate 1a (0001) plane in which a groove is formed 2 GaN epi layer 3 Zn-doped GaN layer 4 Al electrode 5 Bonding wire
Claims (1)
板を用意する工程と、前記基板の主面に線状の凹凸部を
形成する工程と、前記主面に前記基板と同じ結晶構造の
半導体単結晶を成長形成する工程を含む六方晶半導体の
結晶成長方法。Claim: What is claimed is: 1. A step of preparing a hexagonal semiconductor substrate having a (0001) plane, a step of forming linear irregularities on the main surface of the substrate, and the substrate on the main surface. A method for growing a hexagonal semiconductor including the step of growing and forming a semiconductor single crystal having the same crystal structure as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03189108A JP3142312B2 (en) | 1991-07-30 | 1991-07-30 | Crystal growth method for hexagonal semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03189108A JP3142312B2 (en) | 1991-07-30 | 1991-07-30 | Crystal growth method for hexagonal semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0536602A true JPH0536602A (en) | 1993-02-12 |
| JP3142312B2 JP3142312B2 (en) | 2001-03-07 |
Family
ID=16235507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03189108A Expired - Lifetime JP3142312B2 (en) | 1991-07-30 | 1991-07-30 | Crystal growth method for hexagonal semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3142312B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6617182B2 (en) | 1998-09-14 | 2003-09-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and semiconductor substrate, and method for fabricating the same |
| US6620238B2 (en) | 1998-07-31 | 2003-09-16 | Sharp Kabushiki Kaisha | Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device |
| JP2007180556A (en) * | 1997-10-07 | 2007-07-12 | Cree Inc | Nitride photonic device of group iii on silicon carbide substrate having conductive buffer intermediate layer structure |
| US8664687B2 (en) * | 2004-03-31 | 2014-03-04 | Samsung Electronics Co., Ltd. | Nitride semiconductor light-emitting device and process for producing the same |
| JP2014231463A (en) * | 2013-05-29 | 2014-12-11 | トヨタ自動車株式会社 | MANUFACTURING METHOD OF SiC SINGLE CRYSTAL |
-
1991
- 1991-07-30 JP JP03189108A patent/JP3142312B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007180556A (en) * | 1997-10-07 | 2007-07-12 | Cree Inc | Nitride photonic device of group iii on silicon carbide substrate having conductive buffer intermediate layer structure |
| US6620238B2 (en) | 1998-07-31 | 2003-09-16 | Sharp Kabushiki Kaisha | Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device |
| US6617182B2 (en) | 1998-09-14 | 2003-09-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and semiconductor substrate, and method for fabricating the same |
| US6815726B2 (en) | 1998-09-14 | 2004-11-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and semiconductor substrate, and method of fabricating the same |
| US8664687B2 (en) * | 2004-03-31 | 2014-03-04 | Samsung Electronics Co., Ltd. | Nitride semiconductor light-emitting device and process for producing the same |
| JP2014231463A (en) * | 2013-05-29 | 2014-12-11 | トヨタ自動車株式会社 | MANUFACTURING METHOD OF SiC SINGLE CRYSTAL |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3142312B2 (en) | 2001-03-07 |
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