JPH0536343A - Circuit breaking switch and manufacture thereof - Google Patents

Circuit breaking switch and manufacture thereof

Info

Publication number
JPH0536343A
JPH0536343A JP19032691A JP19032691A JPH0536343A JP H0536343 A JPH0536343 A JP H0536343A JP 19032691 A JP19032691 A JP 19032691A JP 19032691 A JP19032691 A JP 19032691A JP H0536343 A JPH0536343 A JP H0536343A
Authority
JP
Japan
Prior art keywords
trench
layer
shape memory
memory alloy
alloy layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19032691A
Other languages
Japanese (ja)
Inventor
Toshihiko Fukushima
稔彦 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP19032691A priority Critical patent/JPH0536343A/en
Publication of JPH0536343A publication Critical patent/JPH0536343A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Thermally Actuated Switches (AREA)
  • Fuses (AREA)

Abstract

PURPOSE:To miniaturize a circuit breaking switch and make it safe by providing a trench formed with a metal wire, and eccentrically providing a specific shape memory alloy layer in the trench. CONSTITUTION:A resist layer is pattern-formed to mask the left half of the upper face of a deposition layer 3A, and the right half of the deposition layer 3A is removed by anisotropic etching. A shape memory alloy layer 3 is residually formed on the left side face of a trench 2, and a SiN protective film 4 is formed on the whole face of the metal layer 3 except for the adjacent semiconductor board region. Annealing is performed for a preset period at the temperature of the transformation starting point or above of the memory alloy 3 in the inert gas to perform the shape memory treatment of the memory alloy 3. It is then oxidation-treated at the temperature of the transformation starting point or below, the trench 2 grown with a thick oxidation layer 5 is formed, and it is bent and displaced so that the upper section of the alloy layer 3 is closed at the opening section. The oxidation layer 5 is removed to form a metal wiring pattern, then a small and safe switch is provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、回路遮断スイッチ及
びその製造方法に関する。さらに詳しくは、各種半導体
集積回路における感熱式の回路遮断スイッチ及びその製
造法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit breaker switch and a method for manufacturing the same. More specifically, the present invention relates to a thermal circuit breaker switch for various semiconductor integrated circuits and a method for manufacturing the same.

【0002】[0002]

【従来の技術】各種半導体記憶素子、CPUチップ、イ
ンターフェイス素子等を構成する半導体集積回路は、極
めて微細で複雑な回路からなり、外的衝撃や内部の物理
的故障等によりしばしば破損を生じやすい。そして、こ
のように半導体集積回路中の一部に破損が生じた場合
に、負荷のバランスがくずれて部分的に過電流が流れ加
熱を生じ、それにより、他の隣接素子の動作に悪影響を
及ぼしたり、場合によっては、発火事故を引き起こすと
いう問題があった。
2. Description of the Related Art A semiconductor integrated circuit, which constitutes various semiconductor memory devices, CPU chips, interface devices, etc., is composed of extremely fine and complicated circuits, and is often liable to be damaged due to external impact or internal physical failure. When a part of the semiconductor integrated circuit is damaged as described above, the load is unbalanced and a partial overcurrent flows to cause heating, which adversely affects the operation of other adjacent elements. In some cases, there was a problem of causing an ignition accident.

【0003】そこで、従来から、これらの半導体集積回
路を使用するに際し、過電流を防止するための電流供給
遮断装置(リレー回路等)を組合わせることが行われて
いる。
Therefore, conventionally, when these semiconductor integrated circuits are used, a current supply / interruption device (relay circuit or the like) for preventing overcurrent has been combined.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
電流供給遮断装置は、組合せる半導体集積回路本体の数
倍以上の専有面積を必要とするものであり、これらの組
合せた半導体素子製品の小型化の支障となるものであっ
た。この発明はかかる状況下なされたものであり、こと
に半導体製品の小型化を可能とすべく、半導体回路を構
成する半導体基板上に構成できる微細な感熱式スイッチ
素子を提供しようとするものである。
However, the conventional current supply / interruption device requires an occupation area which is several times or more that of the semiconductor integrated circuit body to be combined, and miniaturization of these semiconductor device products. Was a hindrance to. The present invention has been made under such circumstances, and in particular, it is an object of the present invention to provide a fine thermal switch element that can be formed on a semiconductor substrate that constitutes a semiconductor circuit in order to enable miniaturization of semiconductor products. ..

【0005】[0005]

【課題を解決するための手段】かくしてこの発明によれ
ば、上部が屈曲変位された形状記憶合金層が、半導体基
板に穿設されたトレンチの一側面側に沿って、かつ上記
屈曲部位が該トレンチの開口部を閉鎖するように、偏位
内設されてなり、このトレンチ形成領域を含む半導体基
板上に金属配線が形成されてなる回路遮断スイッチが提
供される。
Thus, according to the present invention, the shape memory alloy layer whose upper portion is bent and displaced is provided along one side surface side of the trench formed in the semiconductor substrate, and the bent portion is There is provided a circuit breaker switch which is provided in a biased manner so as to close an opening of a trench and in which a metal wiring is formed on a semiconductor substrate including the trench formation region.

【0006】この発明は前記目的を達成すべく、金属配
線が形成されるべき半導体基板領域にトレンチを形設
し、このトレンチ内に特定の形状記憶合金層を偏位内設
して機械的感熱スイッチを構成するという手段を講じた
ものである。この発明の回路遮断スイッチは、例えば、
シリコン半導体基板にトレンチを形設し、このトレンチ
内に形状記憶合金を埋設した後、このトレンチの一側面
側の埋設層を縦方向にエッチング除去して、当該トレン
チの他側面側に形状記憶合金層を残存形成し、この形状
記憶合金層の形状を記憶させた後、当該形状記憶合金層
に隣接する領域を選択的に酸化処理して厚い酸化膜を成
長させることにより該形状記憶合金層の上部を屈曲変位
させ、次いで上記厚い酸化膜を除去した後、このトレン
チ形成領域を含む半導体基板上に金属配線の形成処理を
行うことにより、製造することができる。
In order to achieve the above-mentioned object, the present invention forms a trench in a semiconductor substrate region in which a metal wiring is to be formed, and a specific shape memory alloy layer is deviated in the trench to provide a mechanical thermal sensitivity. This means that a switch is constructed. The circuit break switch of the present invention is, for example,
After forming a trench in a silicon semiconductor substrate and burying a shape memory alloy in the trench, the buried layer on one side surface of the trench is vertically removed by etching, and the shape memory alloy is formed on the other side surface of the trench. After the layer is left and the shape of the shape memory alloy layer is memorized, a region adjacent to the shape memory alloy layer is selectively oxidized to grow a thick oxide film to form a shape memory alloy layer. It can be manufactured by bending and displacing the upper part, then removing the thick oxide film, and then performing a process for forming a metal wiring on the semiconductor substrate including the trench formation region.

【0007】上記トレンチの形成は、いわゆるトレンチ
キャパシタ等を形成する方法に準じて行うことができ
る。また、選択的な基板の酸化処理は、いわゆるLOC
OS法に準じて、SiN系保護膜をマスクとして行うこ
とができる。
The trench can be formed according to a method of forming a so-called trench capacitor or the like. In addition, the selective oxidation of the substrate is performed by the so-called LOC.
According to the OS method, the SiN-based protective film can be used as a mask.

【0008】[0008]

【作用】金属配線に過電流が流れて基板が過熱し、形状
記憶合金の変態温度以上になると、形状記憶合金層の上
部が変位前の状態に戻るため、この上面に形成されてい
る金属配線に亀裂が生じてラインが切断され、電流が遮
断されて過熱が防止されることとなる。
When the substrate is overheated due to the overcurrent flowing through the metal wiring and the temperature exceeds the transformation temperature of the shape memory alloy, the upper portion of the shape memory alloy layer returns to the state before displacement. Therefore, the metal wiring formed on this upper surface A crack will occur in the wire and the line will be cut off, and the current will be cut off to prevent overheating.

【0009】[0009]

【実施例】以下、添付の図面を参照して、この発明の一
実施例の回路遮断スイッチの製造工程について説明す
る。まず、図1に示すように、シリコン半導体基板1の
電源回路領域に公知のフォトリソグラフィによって口径
約3μm、深さ約5μmのトレンチ2を形成した後、全
面に形状記憶合金材料を堆積しエッチバックすることに
より、トレンチ2内に形状記憶合金の埋設層3Aを形成
した。この形状記憶材料としては、例えば、Ti−Ni
系合金、Ti−W合金等が挙げられ、例えば、CVD法
で堆積成長することができる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A process for manufacturing a circuit breaker switch according to an embodiment of the present invention will be described below with reference to the accompanying drawings. First, as shown in FIG. 1, a trench 2 having a diameter of about 3 μm and a depth of about 5 μm is formed in a power supply circuit region of a silicon semiconductor substrate 1 by known photolithography, and then a shape memory alloy material is deposited on the entire surface and etched back. By doing so, the buried layer 3A of the shape memory alloy was formed in the trench 2. As this shape memory material, for example, Ti-Ni is used.
Examples thereof include a system alloy and a Ti-W alloy, and for example, they can be deposited and grown by the CVD method.

【0010】次いで上記堆積層3Aの上面の左半分がマ
スクされるようにレジスト層をパターン形成した後、異
方性エッチングによって堆積層3Aの右半分を除去する
ことにより、図2に示す如く、トレンチ2の左側面側
に、形状記憶合金層3を残存形成させた。次いで、図3
に示すように、形状記憶合金層3の隣接する半導体基板
表面領域を除く全面に、CVD法及びリソグラフィによ
ってSiN系保護膜4を形成した後、不活性ガス(Ar
ガス)中で形状記憶合金の変態開始点(この実施例では
約720℃)以上の温度(この実施例では約800℃)
で1時間アニーリングを行うことにより、形状記憶合金
層3の当該形状の記憶処理を行った。
Next, after patterning a resist layer so that the left half of the upper surface of the deposited layer 3A is masked, the right half of the deposited layer 3A is removed by anisotropic etching, as shown in FIG. The shape memory alloy layer 3 was left on the left side surface of the trench 2. Then, FIG.
As shown in FIG. 3, after the SiN-based protective film 4 is formed on the entire surface of the shape memory alloy layer 3 except the surface region of the adjacent semiconductor substrate by the CVD method and the lithography, an inert gas (Ar
In a gas) at a temperature above the transformation start point of the shape memory alloy (about 720 ° C. in this example) (about 800 ° C. in this example)
The shape memory alloy layer 3 was memorized for the shape by annealing for 1 hour.

【0011】この後、上記変態開始点以下の温度(70
0℃)で酸化処理することにより、図4に示すごとき厚
い酸化層5(2μm)を成長させることにより、トレン
チ内の形状記憶合金層3の上部を当該トレンチの開口部
が閉鎖するように屈曲変位させた。この後、酸化層5を
エッチング除去し、配線(例えば、Al、Al−Si
等)用の金属配線パターン6の形成を行って、図5に示
すこの発明の回路遮断スイッチを得た。
Thereafter, the temperature (70
By oxidizing at 0 ° C.) to grow a thick oxide layer 5 (2 μm) as shown in FIG. 4, the upper portion of the shape memory alloy layer 3 in the trench is bent so that the opening of the trench is closed. It was displaced. After that, the oxide layer 5 is removed by etching, and the wiring (for example, Al, Al-Si
And the like) was formed to obtain the circuit breaker switch of the present invention shown in FIG.

【0012】かかる回路遮断スイッチは、過電流等によ
って前記変態開始点以上の温度になると、形状記憶合金
層3の上部が元の形状に復元するため、図6に示すよう
にトレンチ開口部上の金属配線パターン6が破断して断
線状態となり、それにより、電流が遮断されて過熱が自
動的に防止されう超小型スイッチとして機能するもので
あった。
In such a circuit breaker switch, when the temperature rises above the transformation start point due to overcurrent or the like, the upper portion of the shape memory alloy layer 3 restores to its original shape, and as shown in FIG. The metal wiring pattern 6 breaks and becomes a broken state, whereby the current is interrupted and overheat is automatically prevented, thereby functioning as a micro switch.

【0013】なお、上記実施例では、半導体集積回路を
構成する同一の半導体基板上に回路遮断スイッチを構成
した例を示したが、別の基板に構成した独立したスイッ
チ素子として、集積回路基板とボンディングワイヤー等
で接続して構成してもよい。
In the above embodiment, the circuit breaker switch is formed on the same semiconductor substrate that constitutes the semiconductor integrated circuit. However, as an independent switch element formed on another substrate, an integrated circuit substrate and an integrated circuit substrate are used. It may be configured by connecting with a bonding wire or the like.

【0014】[0014]

【発明の効果】この発明によれば、微小なトレンチと形
状記憶合金層との組合せによる超小型の感熱式回路遮断
スイッチが提供されることとなる。従って各種半導体集
積回路に付設することにより、装置の大型化を招くこと
なく、安全な集積回路素子を提供することが可能とな
る。
According to the present invention, it is possible to provide a microminiature thermal circuit breaker switch by combining a minute trench and a shape memory alloy layer. Therefore, by attaching to various semiconductor integrated circuits, it is possible to provide a safe integrated circuit element without increasing the size of the device.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の回路遮断スイッチの製造工程の一工
程を示す構成説明図である。
FIG. 1 is a structural explanatory view showing one step of a manufacturing process of a circuit breaker switch of the present invention.

【図2】同じく図1の次工程を示す説明図である。FIG. 2 is an explanatory view showing the next step similarly to FIG.

【図3】同じく図2の次工程を示す説明図である。FIG. 3 is an explanatory view showing the next step similarly to FIG.

【図4】同じく図3の次工程を示す説明図である。FIG. 4 is an explanatory view showing the next step similarly to FIG.

【図5】この発明の回路遮断スイッチの一実施例を示す
構成説明図である。
FIG. 5 is a structural explanatory view showing an embodiment of the circuit breaker switch of the present invention.

【図6】同じく動作を示す説明図である。FIG. 6 is an explanatory diagram showing the same operation.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 トレンチ 3 形状記憶合金層 3A 埋設層 4 SiN系保護膜 5 酸化層 6 金属配線パターン 1 Silicon Substrate 2 Trench 3 Shape Memory Alloy Layer 3A Buried Layer 4 SiN System Protective Film 5 Oxide Layer 6 Metal Wiring Pattern

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 上部が屈曲変位された形状記憶合金層
が、半導体基板に穿設されたトレンチの一側面側に沿っ
て、かつ上記屈曲部位が該トレンチの開口部を閉鎖する
ように、偏位内設されてなり、このトレンチ形成領域を
含む半導体基板上に金属配線が形成されてなる回路遮断
スイッチ。
1. A shape memory alloy layer whose upper portion is bent and displaced is provided along a side surface of a trench formed in a semiconductor substrate, and the bent portion closes an opening of the trench. A circuit breaker switch, which is provided in a column and has metal wiring formed on a semiconductor substrate including the trench formation region.
【請求項2】 半導体基板にトレンチを形設し、このト
レンチ内に形状記憶合金を埋設した後、このトレンチの
一側面側の埋設層を縦方向にエッチング除去して当該ト
レンチの他側面側に形状記憶合金層を残存形成し、この
形状記憶金層の形状を記憶させた後、当該形状記憶合金
層に隣接する領域を選択的に酸化処理して厚い酸化膜を
成長させることにより該形状記憶合金層の上部を屈曲変
位させ、次いで上記厚い酸化膜を除去した後、このトレ
ンチ形成領域を含む半導体基板上に金属配線の形成処理
を行うことからなる回路遮断スイッチの製造法。
2. A trench is formed in a semiconductor substrate, a shape memory alloy is buried in the trench, and a buried layer on one side surface of the trench is vertically removed by etching to the other side surface of the trench. After the shape memory alloy layer is formed and the shape of the shape memory gold layer is memorized, a region adjacent to the shape memory alloy layer is selectively oxidized to grow a thick oxide film. A method for manufacturing a circuit breaker switch, which comprises bendingly displacing an upper portion of an alloy layer, then removing the thick oxide film, and then performing a forming process of a metal wiring on a semiconductor substrate including the trench forming region.
JP19032691A 1991-07-30 1991-07-30 Circuit breaking switch and manufacture thereof Pending JPH0536343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19032691A JPH0536343A (en) 1991-07-30 1991-07-30 Circuit breaking switch and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19032691A JPH0536343A (en) 1991-07-30 1991-07-30 Circuit breaking switch and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0536343A true JPH0536343A (en) 1993-02-12

Family

ID=16256324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19032691A Pending JPH0536343A (en) 1991-07-30 1991-07-30 Circuit breaking switch and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0536343A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5813005A (en) * 1993-11-16 1998-09-22 Hitachi, Ltd. Method and system of database divisional management for parallel database system
US6101495A (en) * 1994-11-16 2000-08-08 Hitachi, Ltd. Method of executing partition operations in a parallel database system
US6510428B2 (en) 1993-11-16 2003-01-21 Hitachi, Ltd. Method and system of database divisional management for parallel database system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5813005A (en) * 1993-11-16 1998-09-22 Hitachi, Ltd. Method and system of database divisional management for parallel database system
US6192359B1 (en) 1993-11-16 2001-02-20 Hitachi, Ltd. Method and system of database divisional management for parallel database system
US6510428B2 (en) 1993-11-16 2003-01-21 Hitachi, Ltd. Method and system of database divisional management for parallel database system
US7599910B1 (en) 1993-11-16 2009-10-06 Hitachi, Ltd. Method and system of database divisional management for parallel database system
US6101495A (en) * 1994-11-16 2000-08-08 Hitachi, Ltd. Method of executing partition operations in a parallel database system

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