JPH05347640A - Pi/4 shift dqpsk modulator - Google Patents

Abstract

PURPOSE:To obtain a pi/4 shift DQPSK modulator whose circuit configuration is simplified. CONSTITUTION:A differential coder whose differential coding output (Ik, Qk) is a binary value is adopted for a differential coder 2 and a carrier generating section 6 generates 8 kinds of carriers having phases different by pi/4 each. Furthermore, the pi/4 shift DQPSK system is realized by shifting the phases of the carriers injected in a modulator 5 synchronously with a timing of transmission of a symbol by pi/4 each and waveform shaping LPFs 3, 4 for band limit are made up of only adders and subtractors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a π / 4 shift DQPS.
The present invention relates to a K modulator, and particularly to a π / 4 shift DQPSK modulator suitable for use as a modulator in a digital car telephone system or a digital cordless telephone system.

[0002]

2. Description of the Related Art It has been decided that a modulation system called a .pi. / 4 shift DQPSK system will be adopted in digital car telephone systems and digital cordless telephone systems being advanced in the United States and Japan. This π /
The 4-shift DQPSK method has the same occupied bandwidth as the normally used DQPSK method, but has a feature that the envelope of the modulated wave is small. Therefore, a non-linear operation power amplifier is used. It has been reported that bit error rate characteristics are not significantly deteriorated even when used.

By the way, when demodulating a phase-modulated wave on the receiving side, it is necessary to reproduce a carrier for synchronous detection. It is impossible to reproduce a carrier whose absolute phase is synchronized with the carrier on the transmitting side. A differential phase modulation method that does not require simple phase synchronization is generally used. In Figure 6,
The configuration of a DQPSK system, which is a type of differential phase modulation system, is shown. In FIG. 6, serial data is converted into parallel data X _k , Y _k by a serial / parallel converter 61, and then supplied to a differential encoder 62. This serial / parallel converter 61
FIG. 7 shows an operation outline of the above.

Next, in the differential encoder 62, the input data (X _k , Y _k ) is encoded into a binary differential encoded output (I _n , Q _n ). This differential encoder 62
The operation concept of the above is shown in a table format in FIG. The differential code (I _n , Q _n ) is a low-pass filter (LP) for waveform shaping.
F) After being band-limited by 63 and 64, they are input to the modulator 65. Thus, the differential code (I _n ,
By band limiting Q _n ), data transmission can be performed using the minimum necessary frequency resources. FIG. 9 shows a time waveform and a frequency spectrum of the signal (a) when the band is not limited and the signal (b) when the band is limited.

The arrangement of signal points in the DQPSK system thus transmitted is shown in FIG. Above, DQ
The basic operation of the modulator in the PSK system has been described. Of these functional blocks, the parts that are most frequently used for signal processing are the low-pass filters 63 and 64 for waveform shaping which are necessary for band limitation. This waveform shaping low-pass filter is usually an FIR (finite impulse) as shown in FIG.
response) is realized by a filter. In FIG. 11, D _{1 to} D _n are delay elements, and C _{1 to} C _n are filter coefficients. The above is the outline of the DQPSK method.

Next, a basic description will be given of the π / 4 shift DQPSK system based on the above description. The overall block configuration itself is exactly the same as that of FIG. 6, and the operation of the serial / parallel converter 61 shown in FIG. On the other hand, the operation of the differential encoder 62 is
This is quite different from the case of the PSK system, and its table format is shown in FIG. It is exactly the same that the output of the differential encoder 62 is passed through the waveform shaping low-pass filters 63 and 64 for band limitation, and the transfer characteristics required for the low-pass filters 63 and 64 are the same as those of the DQPSK system. Exactly the same as the case.

[0007]

However, the above-mentioned π / 4 shift DQPSK system has a smaller envelope of the modulated wave than the DQPSK system, and therefore the bit error rate characteristic of the non-linear power amplifier is reduced. On the other hand, it has the advantage of less deterioration, but has the drawback that the signal processing on the modulator side becomes complicated and a complicated circuit is required. That is, the output from the differential encoder 62 is as shown in FIG.
As shown in the equation (1), a multiplier that complicates the circuit configuration is indispensable to configure the waveform shaping low-pass filters 63 and 64 for band limitation.

[Equation 1] Therefore, the present invention makes it possible to simplify the circuit configuration by π /
It is an object to provide a 4-shift DQPSK modulator.

[0008]

A π / 4 shift DQPSK modulator according to the present invention comprises a differential encoder for deriving parallel input data as a binary differential encoded output, and the binary differential code. The band limiting filter that limits the digitized output while inputting it to the modulator, and the eight types of carriers that have different phases by π / 4 are generated, and the modulator is synchronized with the symbol transmission timing. The carrier generating means is provided for shifting the phase of injected carriers by π / 4.

[0009]

In the differential encoder, the binary differential encoded output is derived, while the differential encoder outputs 8 having a phase difference of π / 4.
Π / 4 shift DQ
Implements PSK modulation. As a result, since the DQPSK differential encoder can be used as the differential encoder, the differential encoded output takes a binary value. It can be configured with only.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, after serial data which is a modulated input is converted into parallel data X _k and Y _k by a serial / parallel converter 1, a differential encoder 2 outputs differentially encoded outputs (I _k , Q _k). ), Is further band-limited by the waveform shaping low-pass filters 3 and 4, and is input to the modulator 5, which is exactly the same as that of the DQPSK modulator shown in FIG. In this embodiment, in this DQPSK modulator configuration, there are 8
The type of carrier is generated by the carrier generation unit 6, and the modulator 6 is synchronized with the timing of transmitting a symbol.
A π / 4 DQPSK modulator is realized by rotating (shifting) the phase of the carrier injected into the counterclockwise by π / 4.

Next, a specific structure of the carrier generating section 6 will be described. First, the symbol clock generator 7 generates a symbol clock by dividing the bit clock for taking in serial data by 1/2. Therefore, the symbol clock is synchronized with the input data. This symbol clock is counted by the 3-bit counter 8, and the count output becomes the select signal of the selector 9. Further, a carrier having a predetermined frequency is generated from the carrier generator 10, and this carrier becomes a serial input of the 8-stage shift register 11 and is supplied to the 8-times multiplier 12. Then, the shift control of the 8-stage shift register 11 is performed by the output of the 8-times multiplier 12, whereby eight types of carriers having different phases by π / 4 can be obtained. The eight types of carriers are sequentially selected by the selector 9 according to the count output of the 3-bit counter 8 and injected into the modulator 5.

By the way, the modulated wave at time t = kT (T: symbol duration) is

[Equation 2] And can be represented in complex form. Where ΔΦ is X
_The phase change amount is determined by _k and Y _k, and has the relationship shown in Table 1.

[Table 1]

In the π / 4 shift DQPSK system which receives the signal processing as described above, the signal points are arranged as shown in FIG. For example, the time t = (k−
1) If it is located at P ₁ at time T, the transition is as follows. 1. _{(X k = 0, Y k} = 0) , then the transition to the P ₁ ⇒P _{2 2.} If (X _k = 1 and Y _k = 0), transit to P ₁ ⇒ P ₈ . If (X _k = 1 and Y _k = 1), transit to P ₁ ⇒ P ₆ . If (X _k = 0, Y _k = 1), transition to P ₁ ⇒ P ₄ If it is assumed that (X = 0, Y = 0) at time t = kT, the process proceeds to P ₂ .

Next, at time t = (k + 1) T, the following is performed. 1. If (X _{k + 1} = 0, Y _{k + 1} = 0), then P ₂ → P ₃ 2. If (X _{k + 1} = 1 and Y _{k + 1} = 0), then P ₂ → P ₁ 3. If (X _{k + 1} = 1 and Y _{k + 1} = 1), then P ₂ → P ₇ 4. If (X _{k + 1} = 0, Y _{k + 1} = 1), P ₂ ⇒P ₅ and the same operation transitions are repeated. Therefore, this modulation method can be regarded as a DQPSK method in which the reference phase axis of the carrier is rotated counterclockwise by π / 4 in synchronization with the timing of transmitting the symbol.

As described above, the π / 4 shift DQPSK system is realized by rotating the phase of the carrier injected into the modulator 6 counterclockwise by π / 4 in synchronization with the timing of transmitting the symbol. As a result, the differential encoder 2 for DQPSK can be used as it is, and the differential encoded output becomes binary (+1, −1). Therefore, the waveform shaping low-pass filter 3 for band limitation is used. , 4 can be configured only by the adder / subtractor without using the multiplier as shown in FIG. In FIG. 3, D _{1 to} D _n are delay elements, and C _{1 to} C _n are filter coefficients.

Further, in the above embodiment, the low-pass filters 3 and 4 for waveform shaping are constituted by using the adder / subtractor, but in order to improve the frequency utilization efficiency, a filter having a small roll-off factor, that is, a sharp cutoff characteristic is used. Since the load on the hardware becomes heavy when it is realized, a so-called ROM table method in which the output waveforms of the low-pass filters 3 and 4 for waveform shaping are calculated in advance and written in the ROM can be adopted. A conceptual diagram of this ROM table method is shown in FIG. In FIG. 4A, the output of the waveform shaping low-pass filters 3 and 4 at a certain time is the sum of that time and the impulse responses before and after that time. Therefore, if the patterns before and after are known, the waveform at a certain time can be known as shown in FIG. This waveform data may be stored in the ROM in advance.

By the way, since the waveform shaping low-pass filters 3 and 4 deal with the influence of the transient response generated by band limiting the rectangular wave, the transient response of the level to be considered is ± 4 symbols. Consider an example that spans the interval. In this case, when the pattern over a total of 8 symbols is determined, the time waveform to be output is uniquely determined.

Therefore, the differential encoded output (I _k ,
When Q _k ) is binary, the input pattern is (+
Therefore, a ROM pattern corresponding to 2 ⁹ is required. The relationship between successive time slots and the input pattern is shown in FIG. On the other hand, in the case where the differentially encoded output (I _k , Q _k ) has a 5-valued value, there are cases in which the input pattern is (+1, −1) and a case of Equation 3, so that 2 ⁵ · A ROM pattern equivalent to 3 ⁵ is required. The relationship between successive time slots and the input pattern is shown in FIG.

[Equation 3]

That is, as shown in the above embodiment, the present invention uses a differential encoder having a binary differential output (I _k , Q _k ) as the differential encoder 2. The π / 4 shift DSPSK modulator requires a significantly smaller storage amount in the ROM table than the conventional π / 4 shift DSPSK modulator using the 5-value differential encoder. The configuration of the control circuit can be simplified.

[0020]

As described above, according to the present invention,
While a differential encoder having a binary differential output is used as the differential encoder, eight types of carriers having different phases by π / 4 are generated, and in synchronization with the timing of sending symbols. Since the phase of the carrier injected into the modulator is shifted by π / 4, the differentially encoded output takes a binary value, so that the band limiting filter can be configured only with the adder / subtractor. Shift DQPS
The K modulator can be realized with a simple circuit configuration.

Further, since the ROM table is used for the band limiting filter, the differential encoded output (I _k , Q _k ) is obtained.
The storage amount of the ROM table is significantly smaller than that when a 5-valued differential encoder is used, and the configuration of the address control circuit can be simplified accordingly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an arrangement diagram of signal points in the π / 4 shift DQPSK system.

FIG. 3 is a block diagram showing a configuration of a waveform shaping low-pass filter.

FIG. 4 is a conceptual diagram of a ROM table system.

FIG. 5 is a diagram showing a relationship between consecutive time slots and an input pattern, where (a) is a case where a differential encoder having a binary differential output is used, and (b) is a differential code. Output 5
The case where the differential encoder of the value is used is shown respectively.

FIG. 6 is a block diagram showing an example of a configuration of a DQPSK modulator.

FIG. 7 is a waveform diagram for explaining an operation concept of the serial / parallel converter.

FIG. 8 is a conceptual diagram of differential encoding in the DQPSK system.

FIG. 9 is a time waveform and frequency spectrum diagram, (a)
Shows a signal when the band is not limited, and (b) shows a signal when the band is limited.

FIG. 10 is an arrangement diagram of signal points in the DQPSK system.

FIG. 11 is a block diagram showing a basic configuration of a waveform shaping low-pass filter.

FIG. 12 is a conceptual diagram of differential encoding in the π / 4 shift DQPSK system.

[Description of Codes] 1 serial / parallel converter 2 differential encoder 3, 4 waveform shaping low-pass filter 5 modulator 6 carrier generation unit

Claims (4)

[Claims] 1. A differential encoder for deriving parallel input data as a binary differential encoded output, and a band for inputting to a modulator while band limiting the binary differential encoded output. A limiting filter and a carrier generating means for generating eight types of carriers having phases that differ by π / 4 and shifting the phase of the carriers injected into the modulator by π / 4 in synchronization with the timing of transmitting a symbol. And a π / 4 shift DQPSK modulator. 2. The carrier generating means includes a symbol clock generator that generates a symbol clock synchronized with the parallel input data, and sequentially selects the eight types of carriers in synchronization with the symbol clock to cause the modulator. The π / 4 shift DQP according to claim 1, further comprising a selector for injecting.
SK modulator. 3. The carrier generating means obtains a carrier generator that generates a carrier of a predetermined frequency, and eight types of carriers having phases that differ by π / 4 based on the carrier output from the carrier generator. Means, a 3-bit counter for counting the symbol clock, and the 8-bit counter based on the count output of the 3-bit counter.
3. The .pi. / 4 shift DQPSK modulator according to claim 2, further comprising a selector for sequentially selecting types of carriers. 4. The π / 4 shift DQPSK modulator according to claim 1, wherein a ROM table is used for the band limiting filter.