JPH05347523A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

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Publication number
JPH05347523A
JPH05347523A JP31878191A JP31878191A JPH05347523A JP H05347523 A JPH05347523 A JP H05347523A JP 31878191 A JP31878191 A JP 31878191A JP 31878191 A JP31878191 A JP 31878191A JP H05347523 A JPH05347523 A JP H05347523A
Authority
JP
Japan
Prior art keywords
circuit
gain
level
signal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP31878191A
Other languages
Japanese (ja)
Inventor
Toshiharu Yasuki
壽晴 安木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31878191A priority Critical patent/JPH05347523A/en
Publication of JPH05347523A publication Critical patent/JPH05347523A/en
Withdrawn legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To prevent generation of a transient excessive output level by detecting a continuous maximum gain state of a variable gain circuit, and setting forcibly this circuit to the minimum gain state in response thereto. CONSTITUTION:An output level S2 of a gain variable circuit 1 for executing variable gain amplification of an input signal S1 such as a high frequency signal, etc., is subjected to level detection by a level detecting circuit 2, and its detected level S3 is compared with a reference level R1 by a comparing circuit 3. A detecting circuit 4 detects a fact that a control output level S4 of the comparing circuit 3 controls the gain of the gain variable circuit 1 to the maximum value, and generates the maximum value signal S5. A control circuit 5 sets forcibly a level of a control signal S6 applied to the control end of the gain variable circuit 1 to the minimum value set by a reference level R3 from the original output level S4 of the comparing circuit 3 in accordance with the maximum value signal S5. In such a way, even at the time of applying an input signal from an input signal disconnected state, it does not occur that an excessive output level is sent out of the variable gain circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高周波信号等の受信装置
で広く使用されている自動利得制御回路(以下AGC回
路と略す)の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an automatic gain control circuit (hereinafter abbreviated as AGC circuit) which is widely used in receivers for high frequency signals.

【0002】[0002]

【従来の技術】各種通信システムでは、伝送路や送信装
置などに係る要因のために受信装置に入力される高周波
信号等の信号レベルが変化する。このような信号入力レ
ベル変化に対し受信装置の信号出力レベルを安定化する
ために、受信装置ではAGC回路が広く用いられてい
る。
2. Description of the Related Art In various communication systems, the signal level of a high frequency signal or the like input to a receiving device changes due to factors related to a transmission line, a transmitting device and the like. In order to stabilize the signal output level of the receiving device against such a change in the signal input level, the AGC circuit is widely used in the receiving device.

【0003】図2に従来のAGC回路のブロック図を示
す。高周波信号等の入力信号S1を可変利得増幅する利
得可変回路1の出力レベルS2はレベル検出回路2にて
レベル検出され、その検出レベルS3は比較回路3にて
基準レベルR1と比較される。比較回路3はこれらのレ
ベルS3とR1が一致すべく利得可変回路1の利得を制
御信号S6により制御している。レベル検出回路2で
は、出力信号レベルS2の全振幅を検出する方法やAG
C用に設けられた入力信号S1に設けたパイロット信号
を抽出し、パイロット信号レベルを検出する方法などが
一般に用いられている。
FIG. 2 shows a block diagram of a conventional AGC circuit. The output level S2 of the gain variable circuit 1 that performs variable gain amplification of the input signal S1 such as a high frequency signal is level-detected by the level detection circuit 2, and the detection level S3 is compared with the reference level R1 by the comparison circuit 3. The comparator circuit 3 controls the gain of the gain variable circuit 1 by the control signal S6 so that these levels S3 and R1 match. In the level detection circuit 2, a method for detecting the total amplitude of the output signal level S2 or AG
A method of extracting the pilot signal provided in the input signal S1 provided for C and detecting the pilot signal level is generally used.

【0004】上記AGC回路では、入力信号S1が断の
場合、回路動作として利得可変回路1の利得が最大値に
設定される。この設定状態で入力信号S1が印加される
と、その時点で過大な信号出力レベルS2が送出され、
その後時間経過と共にAGC回路が機能し、所定の出力
レベルへ収束する動作を行う。この様子の概要を図3の
出力信号レベルの時間応答概要を示す図の実線で示して
いる。
In the above AGC circuit, when the input signal S1 is cut off, the gain of the variable gain circuit 1 is set to the maximum value as the circuit operation. When the input signal S1 is applied in this setting state, an excessive signal output level S2 is sent at that time,
After that, the AGC circuit functions with the lapse of time to perform an operation of converging to a predetermined output level. The outline of this situation is shown by the solid line in the figure showing the outline of the time response of the output signal level in FIG.

【0005】[0005]

【発明が解決しようとする課題】上述した従来のAGC
回路では、入力信号が断状態から急に印加された場合、
例えば送信装置の電源投入時などの場合には、AGC回
路の動作応答時間に応じたしばらくの間過大な信号出力
レベルが送出されることとなり、後段に接続される機器
の動作に支障を与えるという問題があった。
DISCLOSURE OF THE INVENTION The above-mentioned conventional AGC
In the circuit, if the input signal is suddenly applied from the disconnection state,
For example, when the power of the transmitter is turned on, an excessive signal output level is transmitted for a while according to the operation response time of the AGC circuit, which hinders the operation of the device connected in the subsequent stage. There was a problem.

【0006】従って本発明の目的は、従来のAGC回路
の欠点であった過渡的な過大出力レベルの発生を防ぐA
GC回路を提供することにある。
Therefore, an object of the present invention is to prevent the generation of a transient excessive output level, which is a drawback of the conventional AGC circuit.
It is to provide a GC circuit.

【0007】[0007]

【課題を解決するための手段】本発明のAGC回路は、
入力信号断時の利得可変回路の利得を最小値に制御する
手段を設けている。
The AGC circuit of the present invention comprises:
Means is provided for controlling the gain of the variable gain circuit when the input signal is cut off to the minimum value.

【0008】即ち、本発明のAGC回路は、入力信号の
入力端,出力信号の出力端および入力信号の変化に対し
ても出力信号レベルを一定値に制御する制御信号を入力
する制御端を備え前記制御信号により増幅利得を制御す
る利得可変手段と、前記出力端から前記出力信号のレベ
ルを検出する第一の検出手段と、この第一の検出手段の
出力レベルと第一の基準レベルに対応して前記制御信号
を生じる第一の比較手段とを備える自動利得制御回路に
おいて、前記自動利得制御回路が、さらに、前記第一の
比較手段の出力する前記制御信号を監視しこの制御信号
のレベルが前記利得可変手段の利得を最大値とするレベ
ルである場合には最大値信号を生ずる第二の検出手段
と、前記最大値信号に応答して前記制御信号を前記利得
可変手段の増幅利得を最小値に設定する制御信号に変え
て前記制御端に供給する制御手段とを備えている。
That is, the AGC circuit of the present invention comprises an input terminal for an input signal, an output terminal for an output signal, and a control terminal for inputting a control signal for controlling the output signal level to a constant value even when the input signal changes. Gain control means for controlling the amplification gain by the control signal, first detection means for detecting the level of the output signal from the output end, and output levels of the first detection means and a first reference level. And a first comparing means for generating the control signal, the automatic gain control circuit further monitoring the control signal output from the first comparing means, and controlling the level of the control signal. Is a level that maximizes the gain of the gain varying means, a second detecting means for producing a maximum value signal, and the control signal in response to the maximum value signal, the amplification gain of the gain varying means. And a control means for supplying to said control terminal in place of the control signal for setting a minimum value.

【0009】[0009]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0010】図1は本発明によるAGC回路の一実施例
のブロック図である。図1のAGC回路は、図2の従来
のAGC回路に加えて、比較回路3の出力端に接続され
た検出回路4と、上記比較回路3の出力端と上記利得可
変回路1の制御端との間に接続された制御回路5とを備
えている。
FIG. 1 is a block diagram of an embodiment of an AGC circuit according to the present invention. In addition to the conventional AGC circuit of FIG. 2, the AGC circuit of FIG. 1 includes a detection circuit 4 connected to the output end of the comparison circuit 3, an output end of the comparison circuit 3 and a control end of the gain variable circuit 1. And a control circuit 5 connected between the two.

【0011】上記検出回路4は比較回路3の制御出力レ
ベルS4が利得可変回路1の利得を最大値に制御してい
ることを検出し最大値信号S5を生ずる。制御回路5は
この検出回路4の出力した前記最大値信号S5に応じて
利得可変回路1の制御端に加えられる制御信号S6のレ
ベルを上記回路1の利得を最小値にすべく設定する。
The detection circuit 4 detects that the control output level S4 of the comparison circuit 3 controls the gain of the variable gain circuit 1 to the maximum value and generates the maximum value signal S5. The control circuit 5 sets the level of the control signal S6 applied to the control end of the variable gain circuit 1 in accordance with the maximum value signal S5 output from the detection circuit 4 so that the gain of the circuit 1 is minimized.

【0012】上記利得可変回路1への入力信号S1が断
の場合、比較回路3の出力レベルS4は、利得可変回路
1の利得を最大とするレベルとなる。各レベル(S3,
S4,S5およびS6)の大、小の方向性や極性の関係
は、本発明の原理に関係しないが、ここでは説明の便宜
上、比較回路3の出力レベルS4の最大値に対し利得可
変回路1に最大利得が、出力レベルS4の最小値に対し
回路1に最小利得が得られるものとすると、上記比較回
路3の出力レベルS4は上記状態では最大値となる。そ
して、検出回路4では、比較回路3の出力レベルS4を
内蔵する比較回路7にて第二の記述レベルR2と比較す
ることにより、比較回路3の出力レベルS4が最大値に
なっていることを検出する。なお、比較回路3と7の間
に接続された積分回路6は、入力信号S1が断でない場
合において生じ得る比較回路3の出力レベルS4の最大
値、例えば入力信号レベルS1の大から小への急激な変
化に対応して生じる過渡的な最大値に対して比較回路7
が検出動作を行うことがないように設けられた保護回路
である。
When the input signal S1 to the variable gain circuit 1 is disconnected, the output level S4 of the comparison circuit 3 becomes a level that maximizes the gain of the variable gain circuit 1. Each level (S3,
The relationship between the large and small directions and polarities of (S4, S5, and S6) is not related to the principle of the present invention, but here, for convenience of description, the variable gain circuit 1 has a maximum value of the output level S4 of the comparison circuit 3. Assuming that the maximum gain is obtained in the circuit 1 with respect to the minimum value of the output level S4, the output level S4 of the comparison circuit 3 becomes the maximum value in the above state. Then, in the detection circuit 4, by comparing the output level S4 of the comparison circuit 3 with the second description level R2 in the built-in comparison circuit 7, it is confirmed that the output level S4 of the comparison circuit 3 becomes the maximum value. To detect. The integrating circuit 6 connected between the comparing circuits 3 and 7 can generate the maximum value of the output level S4 of the comparing circuit 3 which can occur when the input signal S1 is not broken, for example, the input signal level S1 from large to small. The comparison circuit 7 compares the transient maximum value that occurs in response to a sudden change.
Is a protection circuit provided so as not to perform the detection operation.

【0013】前述したように検出回路4は、過渡的でな
い最大利得状態を比較回路3の最大出力レベルS4より
検出し、制御回路5を制御して増幅利得可変回路1の利
得を最小とすべく制御信号S6のレベルをもとの比較回
路3の出力レベルS4から強制的に第三の基準レベルR
3で設定される最小値に設定する。
As described above, the detection circuit 4 detects the maximum non-transient gain state from the maximum output level S4 of the comparison circuit 3 and controls the control circuit 5 to minimize the gain of the amplification gain variable circuit 1. Based on the level of the control signal S6, the output level S4 of the comparison circuit 3 is forcibly changed to the third reference level R.
Set to the minimum value set in 3.

【0014】このように、このAGC回路は、利得最大
状態が積分回路6の設定値に対応した時間を経過すると
強制的に利得最小状態に設定する機能を有し、入力信号
S1の断の状態から入力信号S1が印加された場合、図
3の破線のカーブに示すように出力信号S2のレベルは
低いレベルから徐々に所定のレベルへ収束する動作を行
い、本発明の目的を達成することができる。
As described above, this AGC circuit has a function of forcibly setting the gain minimum state to the minimum gain state after the time corresponding to the set value of the integrating circuit 6 has passed in the maximum gain state, and the state of disconnection of the input signal S1. When the input signal S1 is applied to the output signal S1 from the above, the operation of gradually converging the level of the output signal S2 from a low level to a predetermined level as shown by the curve of the broken line in FIG. 3 can be achieved. it can.

【0015】[0015]

【発明の効果】以上説明したように本発明は、可変利得
回路の継続的な最大利得状態を検出し、これに応答して
強制的に上記回路を最小利得状態とすることにより、入
力信号断状態からの入力信号印加においても上記可変利
得回路から過大出力レベルを送出することがない効果を
有する。
As described above, the present invention detects the continuous maximum gain state of the variable gain circuit and, in response thereto, forcibly sets the circuit to the minimum gain state, thereby eliminating the input signal interruption. Even when the input signal is applied from the state, the variable gain circuit does not send an excessive output level.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】従来のAGC回路のブロック図である。FIG. 2 is a block diagram of a conventional AGC circuit.

【図3】従来及び本発明によるAGC回路の出力信号レ
ベルの時間応答の概要を示す図である。
FIG. 3 is a diagram showing an outline of a time response of an output signal level of an AGC circuit according to the related art and the present invention.

【符号の説明】[Explanation of symbols]

1 利得可変回路 2 レベル検出回路 3 比較回路 4 検出回路 5 制御回路 6 積分回路 7 比較回路 1 gain variable circuit 2 level detection circuit 3 comparison circuit 4 detection circuit 5 control circuit 6 integration circuit 7 comparison circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 入力信号の入力端,出力信号の出力端お
よび入力信号の変化に対しても出力信号レベルを一定値
に制御する制御信号を入力する制御端を備え前記制御信
号により増幅利得を制御する利得可変手段と、前記出力
端から前記出力信号のレベルを検出する第一の検出手段
と、この第一の検出手段の出力レベルと第一の基準レベ
ルに対応して前記制御信号を生じる第一の比較手段とを
備える自動利得制御回路において、前記自動利得制御回
路が、さらに、前記第一の比較手段の出力する前記制御
信号を監視しこの制御信号のレベルが前記利得可変手段
の利得を最大値とするレベルである場合には最大値信号
を生ずる第二の検出手段と、前記最大値信号に応答して
前記制御信号を前記利得可変手段の増幅利得を最小値に
設定する制御信号に変えて前記制御端に供給する制御手
段とを備えることを特徴とする自動利得制御回路。
1. An input signal input terminal, an output signal output terminal, and a control terminal for inputting a control signal for controlling the output signal level to a constant value with respect to changes in the input signal are provided, and the amplification gain is controlled by the control signal. Gain control means for controlling, first detecting means for detecting the level of the output signal from the output end, and the control signal is generated corresponding to the output level of the first detecting means and the first reference level. In the automatic gain control circuit including a first comparing means, the automatic gain control circuit further monitors the control signal output from the first comparing means, and the level of the control signal is the gain of the gain varying means. And a control signal for setting the amplification gain of the gain varying means to the minimum value, in response to the maximum value signal, the second detection means generating a maximum value signal. To An automatic gain control circuit, further comprising: a control unit that supplies the control end to the control end.
【請求項2】 前記第二の検出手段が、前記第一の比較
手段からの前記制御信号のレベルと前記利得可変手段の
利得を最大値とする前記制御信号のレベルにほぼ等しい
第二の基準レベルとを比較し、前記制御信号のレベルが
前記第二の基準レベル以上である場合には前記最大値信
号を生ずるものであることを特徴とする請求項1記載の
自動利得制御回路。
2. The second reference means is substantially equal to the level of the control signal from the first comparing means and the level of the control signal that maximizes the gain of the gain varying means. 2. The automatic gain control circuit according to claim 1, wherein the maximum value signal is generated when the level of the control signal is higher than or equal to the second reference level by comparing with the level.
【請求項3】 前記制御手段が、前記第一の比較手段の
出力端と前記利得可変手段の制御端との間に配置されて
いることを特徴とする請求項1記載の自動利得制御回
路。
3. The automatic gain control circuit according to claim 1, wherein the control means is arranged between an output end of the first comparing means and a control end of the gain varying means.
JP31878191A 1991-12-03 1991-12-03 Automatic gain control circuit Withdrawn JPH05347523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31878191A JPH05347523A (en) 1991-12-03 1991-12-03 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31878191A JPH05347523A (en) 1991-12-03 1991-12-03 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPH05347523A true JPH05347523A (en) 1993-12-27

Family

ID=18102876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31878191A Withdrawn JPH05347523A (en) 1991-12-03 1991-12-03 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH05347523A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016152553A (en) * 2015-02-18 2016-08-22 日本アンテナ株式会社 Automatic gain control circuit
JP6049824B1 (en) * 2015-08-17 2016-12-21 株式会社東芝 Amplifier circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016152553A (en) * 2015-02-18 2016-08-22 日本アンテナ株式会社 Automatic gain control circuit
JP6049824B1 (en) * 2015-08-17 2016-12-21 株式会社東芝 Amplifier circuit

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Effective date: 19990311