JPH0534698B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a central processing unit in an information processing system, and in particular has multiple execution levels to run multiple processing programs under the management of an operating system. The present invention relates to an exception detection device within a central processing unit in an information processing system that executes.

[Conventional technology]

In a central processing unit having n types of execution levels from level 0 to level n-1, for example, an operating system is assigned with level 0 as a privilege level, and a user's processing program is executed at level n-1. Since each execution level has a stack pointer and its own stack area, even if the stack area is insufficient for a processing program at level n-1, there is no problem in executing the operating system at level 0. Additionally, in general, the smaller the execution level numerically, the stronger the privilege. The stronger the privilege, the more extensive operations can be performed on the central processing unit and peripheral devices. An operating system at level 0 allows all operations on the central processing unit and peripheral devices, and a user's processing program at level n-1 allows only the minimum amount of operations for program execution. Careless operations are prevented by requesting the operating system for operations that are not permitted by the user's processing program. In an information processing apparatus that executes a plurality of user processing programs, the operating system becomes complex, and even finer classification of execution levels is required. For example, execution of user processing programs, language processors that process the source programs of user processing programs, general-purpose operating system service routines such as sorting and merging, operating system file management, and scheduling of multiple user processing programs. It is organized into a hierarchy such as the schedule of the operating system that performs the operations. By giving different execution levels to each layer, the higher-privileged higher-level layers can be prevented from being influenced by the lower-level layers, and operations on the central processing unit and peripheral devices can also be subdivided. When a program at a certain execution level l1 requests processing to a program at a higher execution level l2, an execution level change instruction is used. The execution level change command has a parameter P that specifies the value of the called level l2 and the requested process.
has as an operand. When this execution level change instruction is executed, the program returns to level l1 after processing is completed and the execution level l of the caller is placed on the stack corresponding to level l2 of the call destination.
1, information indicating the state of condition flags, etc., and the value of parameter P indicating the type of processing are accumulated, and the execution level change command processing program of level 12 is activated. The execution level change command processing program performs processing according to the parameter P on the stack.

[Problem that the invention seeks to solve]

The above-mentioned conventional central processing unit requires a processing program for change instructions that corresponds to many execution levels and requests execution level processing to level lx for each execution level lx. That is, even if a certain execution level is not used, there is a possibility that an instruction to change the execution level to that level may be issued due to a program error. Therefore, it has the disadvantage that it requires a stack area and a processing program even for execution levels that are not used. In addition, in order to limit the execution levels that can be used for each user's processing program, the execution level change command of each execution level The processing program checks the caller's execution level on the stack, and then the processing program of the user that requested the process. It is necessary to check whether the request is reasonable. If this check determines that the execution level change command is invalid,
Branch to the operating system's exception handling program. This method has the disadvantage that the processing speed is greatly reduced because the check is performed every time at the beginning of the execution level change command processing program.

In contrast to the above-mentioned conventional central processing unit, the present invention prepares permissible execution level data indicating usable execution levels for each user processing program. The difference is that by holding the execution level, when the execution level is changed, the validity of the new execution level is checked by hardware.

[Means for solving problems]

The feature of the present invention is that from level 0 to level n-1
(where n is an integer), the level 0 is assigned to the operating system and the level n-1 is assigned to the user processing program, and when an exception notification occurs, the execution level is executed under the control of the operating system. In an execution level exception detection device for an information processing system that starts an exception handling program according to the type of exception, an execution level register that holds the execution level of the user processing program set by an execution level change instruction; When the execution level register is set to the level 0 by the exception notification, the n types of usable permissible execution levels prepared for each user processing program are set, and the permissible execution level that maintains this permissible execution level is set. a register, and when the execution level is changed, a value indicating the bit position of the permissible execution level held in the permissible execution level register and a value of the execution level held in the execution level register are input, respectively. and an execution level determination circuit including a combinational circuit formed by a logical sum of ANDs, and generates the exception notification based on a match signal of the combinational circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.
In the following explanation, a case will be described in which there are four execution levels from level 0 to level 3.

FIG. 1 is a block diagram showing an embodiment of a central processing unit using the execution level exception detection device of the present invention. 1 is a main memory control circuit, 2 is an instruction decoder, 3 is a register group, 4 is an arithmetic circuit, 5 is a control circuit, 6 is a register that holds an execution level, 7 is a permissible execution level register, 8 is an execution level determination circuit, 101 is an execution level exception notification signal, 102 is an exception notification signal such as reset or interrupt, and 50 is an execution level exception detection device of the present invention.

The main memory control circuit 1 reads instructions and reads and writes data in response to requests from the control circuit 5. The instruction decoder 102 decodes the instruction and passes decoded instruction information to the control circuit 5. Control circuit 5
In addition to executing instructions by controlling the general-purpose register 3, arithmetic circuit 4, and main memory control circuit 1 based on information from the instruction decoder 2, the controller also controls the execution level exception notification signal 101 and the exception notification signal 102. Therefore, when the occurrence of an exception is notified, the execution level register 6 is set to level 0 and an exception handling program corresponding to the type of exception is activated. The permissible execution level register 7 is a register that can be set only at level 0,
In addition to setting by executing a setting command, when the operating system switches the user processing program, the values in the new user processing program are set together with general-purpose registers and the like.

In the execution of the execution level change instruction in this embodiment, first, a new execution level is set in the execution level register 6, and the return destination program counter value, old execution level, etc. are stacked on the stack corresponding to the new execution level. The execution level change command processing program corresponding to the new level is activated. When a new execution level is set in the execution level register 6 during this execution process, the execution level determination circuit 8 sets the bit position (10
4) is checked and the value of the corresponding bit is 0, the execution level exception notification signal 101 becomes "1" and the control circuit 5 is notified of the occurrence of the exception.
That is, only the execution level corresponding to the bit position where the value of the bit in the permissible execution level register 7 is "1" is the execution level permitted for the user processing program. For example, in this embodiment, if the bit values at bit positions 3, 1, and 0 of the permissible execution level register are "1" and the bit value at bit position 2 is "0", the permissible execution levels are 3, 1, and 0. becomes.

FIG. 2 is a block diagram showing the execution level determination circuit 8 in detail. 81 is a decoder, and one of the outputs L0 to L3 corresponding to the execution level 103 becomes "1". FIG. 3 shows the truth table of the decoder 81. 82 to 85 are NAND
It is a gate, and when the bit value of the tolerance level 104 corresponding to the execution level 103 is "0", the output becomes "1". Does not support execution level 103
In the NAND gate, the output of the decoder 81 is “0”
Therefore, “1” is output. In other words, when the bit value of the tolerance level 104 corresponding to the execution level 103 is "0", all of 82 to 85 are
The output of the NAND gate becomes “1”. At that moment
The output of the AND gate 86 becomes "1", and the occurrence of the exception is notified to the control circuit 5 as the execution level exception notification signal 101.

In this embodiment, a dedicated register is assigned to the permissible execution level register 7, but some fields of other registers that are switched in accordance with the user processing program may also be used to hold the permissible execution level.

FIG. 4 is a block diagram showing a second embodiment of the present invention, in which the execution level determination circuit according to the present invention is used as a program debug circuit in the same central office equipment as the first embodiment. 103
is an execution level, 7-1 is a read permissible execution level register, 7-2 is a write permissible execution level register, 8-1 and 8-2 are the same execution level judgment circuits as in FIG. 2, and 105 is the data to the main memory.・Read access signal 106 is also a write access signal, and 101 is an exception notification signal to the control circuit 5 of the central processing unit as in the first embodiment. 87, 88
is an AND gate, and 89 is an OR gate.

The operation of the program debug circuit shown in FIG. 4 is similar to the execution level exception notification shown in FIG. 1, but in contrast to the circuit shown in FIG. After changing the execution level, when the corresponding bits of the read/write permissible execution level registers 7-1 and 7-2 corresponding to the new execution level are "0" and a data read/write occurs, the exception notification signal 101 becomes "0". 1”. For example, if the execution level 103 is level 2, the read permission execution level register 7-1
When the bit value at bit position 2 is "0", the output of the execution level determination circuit 8-1 becomes "1". At this time, when the program performs an operand read, the operand read access signal 105 becomes "1", the output of the AND gate 87 becomes "1", and the OR
The output of gate 89 becomes "1". When the control circuit 5 is notified of the occurrence of an exception by the exception notification signal 101, the control circuit 5 starts an exception handling program for program debugging.

Conventional information processing devices use a method in which an address to be debugged is set in advance, and an exception for debugging is generated when the address output from the central processing unit matches the set value. Additionally, in this conventional method, in addition to setting the address to be debugged, there is also a method in which the type of access to be debugged (read, write, etc.) is set, and a debugging exception is generated when the address and access type match. It is used. In the second embodiment shown in FIG. 4, by using the address and access coincidence detection signal of the conventional method instead of the operand read/write signals 105 and 106, access at a specific execution level can be performed in addition to the conventional method. can be detected. In this case as well, by setting the values of the read/write permissible execution level registers 7-1 and 7-2 to all “0”, the output of the execution level judgment circuits 8-1 and 8-2 becomes “1”. It can also be used as a conventional debug exception.

〔Effect of the invention〕

As explained above, the central processing unit using the present invention has a structure with many execution levels in order to support various user processing programs depending on various uses, and the overall operation of the central processing unit is Under the control of the operating system that operates with the highest priority, processing proceeds while using multiple execution levels as required for each user processing program. At the start of execution of each of these user processing programs, the operating system sets an execution level in the permissible execution level register of the present invention so that execution is permitted only at the execution level that the user processing program can take during normal operation. . Further, when an execution level change to an incorrect execution level occurs due to a malfunction of a user processing program, the execution level exception detection device of the present invention can directly notify the operating system of the exception at high speed.

Therefore, by using the present invention, it is possible to specify permissible execution levels in detail, and to detect unauthorized execution levels at high speed with simple hardware. This has the effect of reducing the head count and improving the debugging effect regarding execution level exceptions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a central processing unit using the first embodiment of the execution level exception detection device of the present invention, and FIG. 2 is a block diagram of the execution level determination circuit 8 shown in FIG.
3 is a diagram showing a truth table of the decoder 81 of the execution level determination circuit shown in FIG. 2, and FIG. 4 is a block diagram showing a second embodiment of the present invention. 1 is a main memory control circuit, 2 is an instruction decoder, 3 is a register group, 4 is an arithmetic circuit, 5 is a control circuit, 6 is an execution level register, 7, 7-1, 7-2 are tolerance level registers, 8, 8 -1 and 8-2 are execution level determination circuits.

Claims (1)

[Claims] 1 It has n types of execution levels from level 0 to level n-1 (n is an integer), and the level 0 is assigned to the operating system and the level n-1 is assigned to the user processing program, and when an exception notification occurs, In an execution level exception detection device for an information processing system that starts an exception handling program according to the type of exception under the management of the operating system, the execution level of the user processing program set by the execution level change instruction is When the execution level register to be held and this execution level register are set to the level 0 by the exception notification, the n types of usable allowable execution levels prepared for each user processing program are set, and this allowable execution level is set. a permissible execution level register that holds an execution level; a value indicating the bit position of the permissible execution level held in the permissible execution level register when the execution level is changed; and a value indicating the bit position of the permissible execution level held in the execution level register; and an execution level determination circuit including a combinational circuit formed by a logical sum of n logical products each inputting a value, and generating the exception notification based on a match signal of the combinational circuit. Exception detection device.