JPH05346852A - Pipeline processing data processor - Google Patents

Abstract

PURPOSE:To improve the performance of a computer by bypassing data at much earlier timing when immediately using cache read data for following instructions in the case of pipeline processing provided with the cache memory of direct mapping. CONSTITUTION:A bypass processing condition in the case of generating cache hit is shown and this device is provided with an instruction register 10, general- purpose register 11, arithmetic circuit 12 and cache memory 13. Respective stages are expressed by D, E, C1, C2 and W, the time point of bypassing data is shown by an arrow, and the hit of the cache memory is shown by an arrow with a white circle. In this case, data appear at the end of the stage C1 and at this time point, the relevant data are controlled so as to be bypassed to the following arithmetic instructions. Namely, when cache data can be read, data are immediately bypassed. Thus, processing is more speedily completed in comparison with the system of bypassing data on the stage C2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processing data processing device having a direct mapping operand cache memory (hereinafter referred to as a cache memory) to efficiently execute pipeline processing.

[0002]

2. Description of the Related Art A cache memory is used in order to increase the speed of processing in a data processing device, particularly to increase the average speed of memory access. Less than,
The cache memory may be simplified to be abbreviated as cache.

WAY is one of the options for configuring the cache
There are numbers. This is the number of entries in the cache memory that may hold (cache) the data of any address. Generally 2way-set-as
sociative, 4way-set-associative, full-set-assoceat
ive, direct-mapping, etc. are often adopted.

It is generally known that if the cache memory has the same capacity, increasing the number of ways increases the hit rate and the performance. However, when the number of WAYs becomes large, the target data must be selected from a larger number of elements that can be held when the cache is read, resulting in an increase in hardware and an increase in delay time.

Here, one configuration and processing when the cache is adopted will be described with reference to FIG. In the cache, there is a data memory 1 for holding data, a tag memory 2 used for hit judgment, a hit judgment circuit (decision of WAY to select) 3 for hit judgment, and data depending on the result of the hit judgment. And a circuit 4 for selecting (WAY select). If there is target data in any of the WAYs, the cached data is read out together with the hit signal.

The structure of FIG. 8 is used as it is for the FULL-assoc.
When the iative configuration is adopted, it can be predicted that the output from the data memory 1 or the tag memory 2 will be very large. Therefore, generally, the associative memory is used when the number of ways is large like full-associative.

As can be seen from FIG. 8, in general, the path requiring the longest propagation time in the cache memory is indexed from the address holding circuit to the tag memory and hit (WA).
Y) This is a path from judgment to WAY selection to data output.

Direct mapping (1 WAY) is shown in FIG.
A configuration example in the case of is shown. Since there is only one entry in the cache memory where data may enter, there is no need for a circuit for selecting the output of the data memory as WAY. The reference numerals in FIG. 9 correspond to those in FIG.

FIG. 10 is a conceptual diagram of a pipeline processing configuration including a cache memory. In the figure, reference numeral 10 is an instruction register, 11 is a general-purpose register (GR), 12 is an arithmetic circuit (ALU), 13 is a cache memory, and 11 'is a general-purpose register. The D stage is an operand read stage, the E stage is an address operation stage, the C stage is a cache read stage, and the W stage is a write stage.

In FIG. 10, two GRs (general purpose registers) are shown, but the actual number is one. GR11,1
1'is used for reading the source operand in the D stage, and used for writing the result in the W stage.
In FIG. 10, the processing of the cache memory shown in FIGS. 8 and 9 is performed in one stage.

The time required for each stage of D, E, C and W in FIG. 10 is not necessarily the same. The most time consuming stage determines the cycle time of this pipeline. Conventionally, the C stage requires a large amount of time, and determines the pipeline cycle time. Further, in recent years, since the speed of the logic circuit portion has been increased, the C stage may be divided into two to reduce the cycle time of the pipeline.

FIG. 11 shows the processing of the cache memory shown in FIG. 10 divided into two stages. The reference numerals in the figure correspond to those in FIG. 1 and FIG. Memory reference is performed in the C1 stage, and hit determination and WAY selection are performed in the C2 stage.

FIG. 12 shows the processing of the direct mapping cache memory shown in FIG. 2 divided into two stages. It should be noted in FIG. 12 that the hit determination is only performed in the C2 stage, and the data read from the data memory is not processed. The reference numerals in FIG. 12 correspond to those in FIG.

[0014]

FIG. 13 shows how read data from the cache memory is bypassed by a subsequent operation instruction. If the WAY selection processing is performed in the C2 stage as in the case of FIG. 11, the C2 stage is effectively used, but in the case of the configuration shown in FIG. It is not being used effectively. If the cache is hit, the data is not prepared until the end of the C2 stage even though the data is prepared at the end of the C1 stage. Therefore, if a subsequent instruction uses this data, the data is not read until the end of the C2 stage. It locks up and reduces performance.

As described above, in the conventional configuration, although the data is obtained, the data cannot be used to proceed the processing, so that the interlock is performed more than necessary and the performance is lowered.

According to the present invention, in a pipeline having a cache memory of direct mapping in which the cache memory read stage and the cache hit determination stage are independent of each other, the cache read data can be immediately used by a subsequent instruction immediately. The purpose is to improve performance by bypassing the data in.

[0017]

FIG. 1 is an explanatory diagram of the principle of the present invention, showing a mode of bypass processing when a cache hit occurs. In the figure, reference numeral 10 is an instruction register, 11 is a general-purpose register, 12 is an arithmetic circuit, and 13 is a cache memory. Also, those with a dash "'", "''", or "'''" are the same as those without a dash. Further, D, E, C1, C2 and W respectively represent stages. The arrow indicates the time when the data is bypassed, and the white circle on the arrow indicates that the cache is hit.

In the case of the present invention, data appears at the end of the C1 stage, and at this time, the data is controlled so as to be bypassed to the subsequent arithmetic instruction.

[0019]

This can be achieved by bypassing as soon as the cache data can be read as shown in FIG. C
It can be seen that the processing ends 1τ earlier than the method of bypassing in two stages. But 2 at the same time on the W stage
It can be seen that one instruction is executed. GR for this
The most obvious way is to increase the write port of. However, this method involves a large increase in hardware. There is also a method of using a register write buffer to solve this problem without increasing the number of write ports of GR, but the present invention does not take any measures for that purpose. It should be resolved.

[0020]

FIG. 2 shows a block diagram of an embodiment of the present invention.
Reference numerals 1, 2, 3, 11, 12, and 13 in FIG.
Corresponds to 0. Reference numerals 14, 15 and 16 are selectors, 17 is a load data bypass detection circuit for determining whether or not the bypass as shown in FIG. 1 is performed, and 18 is a C1 stage write register ID (C1-
A WR-REG-ID) holding unit 19 is a general-purpose register read interlock detection circuit that detects whether or not the register is in an interlock-needed state due to a busy register or the like during the bypass process. 20 is a C1 stage load instruction (C1-LD-O
P) Holding unit, 21 is a pipeline stage control circuit that generates a control signal corresponding to each stage of the pipeline.

The various signals in the figure represent the following signals. D-RD-REG-ID-0: This signal indicates that the register ID # 0 is read in the D stage.

D-RD-REG-ID-1: This signal indicates that the register ID # 1 is read from the D stage. C1-VALID: A signal indicating that the C1 stage is processing.

E-WR-REG-ID: This signal is for instructing the register to be written in the E stage. D-RD-REG-0-USED: This signal is obtained by decoding an instruction at the D stage and is a signal indicating whether or not to use the register # 0.

D-RD-REG-1-USED: This is a signal obtained by decoding an instruction in the D stage, and is a signal instructing whether or not to use the register # 1. E-VALID: A signal indicating that the E stage is processing.

E-LD-OP: This signal indicates that the load instruction is being processed at the E stage. BRANCH-INTERLOCK: A signal indicating that the branch is interlocked.

GR-READ-INTERLOCK:
It is a signal indicating that an interlock occurs when reading a general-purpose register. D-STAGE-RELEASE: This signal represents the end of the D stage.

E-STAGE-RELEASE: This signal represents the end of the E stage. In FIG. 2, as briefly described in the processing mode with reference to FIG. 1, the operand is read from the general-purpose register 11 at the D stage and is supplied to the arithmetic circuit 12 via the selector 15 at the stage to supply the address. Is calculated. C
In the first stage, the data memory 1 and the tag memory 2 are accessed, and in the C2 stage, the hit determination circuit 3 determines whether or not there is a hit.

The illustrated load data bypass detection circuit 17
Determines whether to perform bypass as shown in FIG.
When performing the bypass, the data read from the data memory 1 is supplied to the arithmetic circuit 12 by the selectors 15 and 16.

The general-purpose register read interlock detection circuit 19 shown in the figure should perform the interlock when the register used in the D stage and the register used in the W stage are the same, as will be described later. To detect.

The illustrated pipeline stage control circuit generates a control signal for pipeline processing, that is, a signal instructing during processing or release to control the pipeline processing. FIG. 3 shows a bypass processing mode in the case of a cache hit in the case of the present invention. The symbols in the figure correspond to those in Fig. 1, the arrow indicates the time when the data is bypassed, the white circle on the arrow indicates that the cache has been hit, and the cross on the arrow indicates the cache is a miss. It shows that it did.

In FIG. 3, the missed data is written into the missed cache memory from the main storage device without any software intervention and written into the cache memory, and the written contents are read again by executing the C1 and C2 stages. By controlling in this way, it is possible to control even if there is a mis-hit with a control close to that when a hit occurs.

In the case of a miss hit, there is a method of writing to the cache memory once and then reading again to write to the GR or bypass, while there is a method of writing to the GR11 or bypass while writing to the cache memory. There is also a method of causing an interrupt to update the cache memory by software. However, we will not consider them in detail here. Because the hit rate of cache memory is generally 9
This is because it is 0% or more, and even if the configuration is such that the performance is improved with respect to the remaining 10%, it may not be so advantageous. At least a mishit may be processed in the conventional manner. In the worst case, do not bypass and write to GR once, then the subsequent instruction is GR
May be controlled to read.

In the case of FIG. 3, the data for bypass is passed in the C1 stage, and the result of the hit determination is notified in the C2 stage. The C1 stage and C2 stage are repeated several times, and the fact that the data bypassed in the C1 stage at the right end of the figure is hit in the C2 stage is notified, and the one calculated in that stage is used as the correct one for the next calculation. It

Below, for example, it is described in VHDL which is defined as a hardware description language in IEEE. Incorporating the signal next-e-alu-op1 into the signal e-alu-op1 in the E stage, and also the signal next-e-al
It is described that u-op2 is taken into the signal e-alu-op1 in the E stage, but the description can be considered to represent the hardware configuration as shown in FIG. Note that in FIG. 4, the rising edge of the clock (clock = '1' and cloc
k'event), the signals next-e-alu-op1 and next-e-alu-op2 input to the respective flip-flops are set in the respective flip-flops, and the signal e-alu-op
1 and the signal e-alu-op2 are represented in the form of hardware. In the above description, the description “<=” means “taken in” (the same applies hereinafter). (A) Consider the D stage end signal.

The signal D-STAGE-REL shown in FIG.
EASE is set to '1' in the following cases. D-STAGE-RELEASE <= '1' when D-VALID = '1' and not (E-VALID = '1' and E-STAGE-RELEASE = '0') and BRANCH-INTERLOCK = '0' and GR- READ-INTERLOCK = '0' else '0'; This expression shows the end condition of the D stage. The first term indicates that the D stage processing is being performed. The second term indicates that the D stage does not end and the D stage interlocks when the next E stage is processing and the E stage does not end. The third term indicates that when a branch instruction is executed, it waits in the D stage until the branch destination instruction is fetched. Section 4 interlocks in the D stage until the write is complete (or bypass is possible) when the GR reading the operand in the D stage is modified by an instruction that preceded and has not finished. It is shown that. This GR-REA
The D-INTERLOCK signal is hereinafter referred to as a GR read interlock signal.

According to the present invention, it is possible to bypass the data at an early timing by changing the GR read interlock signal or the like. (B) Next, consider the GR read interlock.

In the conventional case shown in FIG.
As can be seen from 3, the register number (E-WR-REG-ID, C1 respectively) in which the result of the LD instruction held in the E or C1 stage of the preceding LD (load) instruction is written.
-WR-REG-ID) is the read register number of the D stage of the subsequent instruction (there are two in the figure;
D-REG-ID0, D-RD-REG-ID1), the subsequent instruction may be interlocked at the D stage.

Here, the processing in the case of a mishit will be described. When processing missed data by interrupt processing, stop the execution of its own instruction and the following instruction,
After the cache memory replacement processing is performed by the interrupt program, the interrupted LD instruction may be executed.

GR-READ-INTERLOCK <= '1' when (E-VALID = '1' and E-LD-OP = '1' and ((E-WR-REG-ID = D-RD-REG-ID0 and D-RD-REG-0-USED) or (E-WR-REG-ID = D-RD-REG-ID1 and D-RD-REG-1-USED))) (C1-VALID = '1' and C1-LD-OP = '1' and ((C1-WR-REG-ID = D-RD-REG-ID0 and D-RD-REG-0-USED) or (C1-WR-REG-ID = D- RD-REG-ID1 and D-RD-REG-1-USED))) else '0'; In the above, E-VALID and C1-VALID are signals indicating that the E and C1 stages are valid, respectively. E-LD-OP and C1-LD-OP are E and C1, respectively.
It is a signal indicating that the LD instruction is processed in the stage, and is D-RD-REG-0-USED, D-RD-R.
EG-1-USED is a signal obtained by decoding an instruction in the D stage, and is a signal indicating whether or not to use each of two source register operands.

In the case of FIG. 13, the GR read interlock signal is given in the above-described manner, but in the case of the present invention in FIG. 1, it is necessary to apply the interlock at the C1 stage. From this, the GR read interlock signal follows the following logic.

GR-READ-INTERLOCK <= '1' when (E-VALID = '1' and E-LD-OP = '1' and ((E-WR-REG-ID = D-RD-REG-ID0 and D-RD-REG-0-USED) or (E-WR-REG-ID = D-RD-REG-ID1 and D-RD-REG-1-USED))) else '0'; For the operation when the
It may be considered in the same manner as in the case of 3. (C) Next, consider the operand selection control.

By using the control signals as described above, the operation of the pipeline stage can be performed as desired. However, in the case of the present invention, the control on the flow of data as an operand must be changed.

First, the conventional case will be described, and then the case of the present invention will be described. Although the ALU is shown as an example of an arithmetic unit such as a normal addition, the shifter and the like may be similarly considered.

Process (clock, reset)-(register process) begin if reset = 1 then-(reset process) e-alu-op1 <= x "00000000"; e-alu-op2 <= x " 00000000 "; elsif (clock = '1' and clock'event) then-(clock rising e-alu-op1 <= next-e-alu-op1; time processing) e-alu-op2 <= next-e -alu-op2; end if; end process; This process represents an edge-triggered flip-flop.

Process (clock, reset) indicates that the flip-flop can change its output only when the clock, reset input changes. if reset = 1 then from elsi
Up to f, it shows the operation when reset = 1, that is, when reset is input. Here, it is shown that two signals e-alu-op1 and e-alu-op2 representing the output signals of the flip-flops are initialized to 0.

Elsif (clock ＝ '1' and clock'event) the
The process from the n to the end if represents the rising edge of the clock. A clock'event is true when the clock signal changes, and clock = '1' is true when the clock signal is '1'.

Therefore (clock = '1' and clock'event)
The rising edge of the clock is detected at. At the rising edge of the clock, flip-flops are connected to the inputs of each flip-flop next-e-alu-op1, next-e
-Two signals that capture the alu-op2 signal and represent the output signal e-
It shows that alu-op1 and e-alu-op2 change. Note that
next indicates that it is an input.

(A) When moving from the D stage to the E stage, the operand is updated. Above next-e-alu
-op1 etc. are given as follows. NEXT-E-ALU-OP1 <= D-ALU-OP1 when D-STAGE-REL = '1' else E-ALU-OP1; NEXT-E-ALU-OP2 <= D-ALU-OP2 when D-STAGE- REL = '1' else E-ALU-OP2; (b) In the D stage operand generation, the first operand can be GR only D-ALU-OP1 <= D-GR-DATA-1; The second operand is GR Or it can be immediate. Then, the instruction is decoded and selected by d-op2-sel.

D-ALU-OP2 <= D-GR-DATA-2 when D-OP2-SEL = REG-SEL else x "0000"& D-OPCODE (16 to 31); (c) where d-gr -data-1 and d-gr-data-2 are bypassed data by the conventional method when the result of the E stage of the preceding instruction should be bypassed.

D-gr-data-1 <= e-result when d-op1-bypass-from-e = '1' else gr (d-gr-rd-adr-1); d-gr-data-2 <= e-result when d-op2-bypass-from-e = '1' else gr (d-gr-rd-adr-2); d-op1-bypass-from-e <= '1' when e- valid = '1' and e-write = '1' and e-wr-gr-adr = d-gr-rd-adr-1 else '0'; d-op2-bypass-from-e <= '1' when e-valid = '1' and e-write = '1' and e-wr-gr-adr = d-gr-rd-adr-2 else '0'; where gr (i) is the general register i The second register value, d-gr-rd-adr-1, d-gr-rd-adr-2, is obtained by decoding the instruction with the register numbers of the first and second source register operands, respectively.

E-write is a signal indicating that writing to the register will be performed in the next W stage. Also e-wr-gr-adr
Indicates which register is written in the W stage.

E-result is the result calculated by the ALU. In the case of the present invention, the following functions are added to the above conventional case (see FIG. 1). That is, when the preceding LD instruction is the C1 stage and the write register number is equal to the read register number, the preceding LD instruction
Bypass the cache read data of the instruction as if it were used as GR read data. This logic is very similar to that from the arithmetic unit and can be inferred.

D-OP1-BYPASS-FROM-C1 <= '1' when C1-VALID = '1' and C1-LD-OP = '1' and C1-WR-GR-ADR = D-GR-RD- ADR-1 else '0'; D-OP2-BYPASS-FROM-C1 <= '1' when C1-VALID = '1' and C1-LD-OP = '1' and C1-WR-GR-ADR = D -GR-RD-ADR-2 else '0'; D-GR-DATA-1 <= E-RESULT when D-OP1-BYPASS-FROM-E = '1' else C1-CACHE-DATA when D-OP1- BYPASS-FROM-C1 = '1' else GR (D-GR-RD-ADR-1); D-GR-DATA-2 <= E-RESULT when D-OP2-BYPASS-FROM-E = '1' else C1-CACHE-DATA when D-OP2-BYPASS-FROM-C1 = '1' else GR (D-GR-RD-ADR-2); Due to the above changes, processing is performed by interrupt processing and instruction re-execution at a miss hit. The speed-up of the cache memory of the done method has been completed.

Next, as shown in FIG. 3, a circuit configuration is shown in which cache data missed by hardware is read and the data is bypassed by a subsequent instruction. In the update control of the operand register described so far, the update is performed only when the end signal D-STAGE-REL of the D stage is asserted, and in other cases, the previous value is held. In FIG. 3, the data bypassed from the preceding instruction even though D-STAGE-REL is not asserted must be fetched into the operand register. The control for that is shown below.

When moving from the D stage to the E stage, the operand is updated. NEXT-E-ALU-OP1 <= D-ALU-OP1 when D-STAGE-REL = '1' else C1-CACHE-DATA when E-OP1-BYPASS-FROM-C1 = '1' else E-ALU-OP1 ; NEXT-E-ALU-OP2 <= D-ALU-OP2 when D-STAGE-REL = '1' else C1-CACHE-DATA when E-OP2-BYPASS-FROM-C1 = '1' else E-ALU- OP2; E-OP1-BYPASS-FROM-C1 <= '1' when C1-VALID = '1' and C1-LD-OP = '1' and C1-WR-GR-ADR = E-GR-RD-ADR -1 else '0'; E-OP2-BYPASS-FROM-C1 <= '1' when C1-VALID = '1' and C1-LD-OP = '1' and C1-WR-GR-ADR = E- GR-RD-ADR-2 else '0'; In addition to the method shown in Fig. 3, many other methods are conceivable, such as when data to be written in the cache is prepared and bypassing is possible. As indicated by the logic, control may be performed so as to detect the coincidence of the register numbers and the timing at which the LOADed data arrives and capture the same in the operand register. (D) Next, consider the modification (I) of pipeline control.

In the above description, the sum of two register operands or 1 is set in the addressing mode of the LOAD instruction.
The sum of two register operands and an immediate value (immediate) is used, but consider the case where only one register operand can be specified (that is, only register indirect addressing, and it is not necessary to calculate an address by addition).

FIGS. 6 and 7 show the operation of the pipeline in the conventional example and the present invention in that case. Reference numerals in the figure are those in FIG.
3 and FIG. 1. In this case, the interlock control by the LOAD instruction is not necessary as shown in FIG. The operand control circuit may remain conventional control. (E) Further, consider the modification (II) of pipeline control.

In the case of the above description, the pipeline is interlocked to solve the data dependency between instructions. However, in general, in addition to the method of interlocking, there is a method of inputting an invalid instruction into the pipeline after the E stage and causing the original instruction to flow into the pipeline after the E stage when the waiting condition disappears. This state is shown in FIG. Most instructions are equivalent to invalid instructions without a write to GR. In the case of FIG. 5, "NOP" is made to flow corresponding to the "ADD" command. GR
The following is an example of invalidating the instruction by invalidating the write control signal.

(A) Common process (clock, reset) begin if (clock = '1' and clock'event) or reset = '1' then if reset = 1 then-(Process at reset) E-WRITE < = '0'; else-(Process at clock rising) E-WRITE <= NEXT-E-WRITE; end if; end if; end process; (b) Interlock method NEXT-E-WRITE <= D- WRITE when D-STAGE RELEASE = '1' else E-WRITE; (c) Invalidation method NEXT-E-WRITE <= D-WRITE when D-STAGE-RELEASE = '1' else E-WRITE when E-STAGE- RELEASE = '0' and E-VAL = '1' else '0'; When the instruction cannot be invalidated only by the GR write control signal, at least an appropriate E stage signal may be invalidated. For example, FR (floating point) write signal,
An exception detection signal, a system register update signal, etc. correspond to this. (F) Next, an example of pipeline processing according to the present invention will be described.

Now, an example very often used for transferring data of a fixed size and substituting records / character strings will be given. Here, one element is 4 bytes. Such loop processing is expanded to the following processing.

[0061] It is the loop that has the greatest effect on the processing time in this instruction sequence. Below is the pipeline when executing this loop. FIG. 14 shows a conventional case,
FIG. 15 shows the case of the present invention. As shown in FIG.
In this example, the invention improves performance by up to 11%.

[0062]

As described above, according to the present invention, in a pipeline process having a cache memory of direct mapping in which a cache memory read stage and a cache hit determination stage are independent, cache read data is succeeded. The performance of the computer can be improved by bypassing the data at an earlier timing when the instruction is used immediately.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 shows a block diagram of an embodiment of the present invention.

FIG. 3 shows a bypass processing mode in the case of a cache miss.

FIG. 4 shows a circuit equivalent to the description of VHDL.

FIG. 5 shows a case of pipeline control by an invalid instruction.

FIG. 6 shows a conventional processing mode when address calculation is not required.

FIG. 7 shows a processing mode of the present invention when address calculation is not required.

FIG. 8 shows a basic configuration of a cache memory.

FIG. 9 shows a basic configuration in the case of direct mapping.

FIG. 10 shows a pipeline (when one stage is spent in cache).

FIG. 11 shows a pipeline (when two stages are spent in cache).

FIG. 12 shows a pipeline (2-stage-direct mapping).

FIG. 13 shows a mode of bypass processing in a conventional case.

FIG. 14 shows a processing example of a conventional case.

FIG. 15 shows a processing example in the case of the present invention.

[Explanation of symbols]

 1 data memory 2 tag memory 3 hit determination circuit 4 data selection circuit 10 instruction register 11 general purpose register 12 arithmetic circuit 13 cache memory 14 selector 15 selector 16 selector 17 load data bypass detection circuit 18 C1 stage write register ID holding unit 19 general purpose register Read interlock detection circuit 20 C1 stage load instruction holding unit 21 Pipeline stage control circuit

Claims (4)

[Claims] 1. A read stage (C1) comprising a direct mapping operand cache memory (13) for reading the operand cache memory (13).
And a hit determination stage (C2) for performing a hit determination by the operand cache memory (13) independently, in a pipelined data processing device, an instruction for a write register for data being read from the operand cache memory The “write register identification signal” (WR-REG-ID) and the “read register identification signal” (RD-REG-ID) indicating the register to be read as the operand are input, and the “write register identification signal” ( WR-RE
G-ID) and the "readout register identification signal" (RD
-REG-ID) has a load data bypass detection circuit (17) for detecting whether writing and reading are performed on the same register, and the load data bypass detection circuit (17) is the same register as described above. When it is detected that the data is written to or read from the operand cache memory (13), the data read from the operand cache memory (13) is bypassed for the operation by the subsequent instruction without waiting for the hit determination in the operand cache memory (13). Then, the pipeline processing data processing device is configured to start the execution stage (E) of the subsequent instruction. 2. The register read stage (D) of the subsequent instruction when the preceding load instruction has not reached the read stage (C1) when reading the register in the register read stage (D) of the subsequent instruction.
Alternatively, interlocking is performed in the operation stage (E), and at the time of a mishit in the operand cache memory (13), the preceding load instruction is interrupted, and the necessary data from the main memory device to the operand cache memory (13). 2. After the move-in is performed, the load instruction is re-executed.
The pipeline processing data processing device described. 3. The register read stage (D) of the subsequent instruction when the preceding load instruction has not reached the read stage (C1) when reading the register in the register read stage (D) of the subsequent instruction.
Alternatively, interlocking is performed in the arithmetic stage (E), and when a miss hit occurs in the operand cache memory (13), the interlocking state occurs, and necessary data is moved in from the main memory device to the operand cache memory (13). The pipeline processing data processing apparatus according to claim 1, wherein the interlock is released and the execution is continued after that. 4. The register read stage (D) of the subsequent instruction when the preceding load instruction has not reached the read stage (C1) when reading the register in the register read stage (D) of the subsequent instruction.
The pipeline processing data processing device according to claim 1, wherein an invalid instruction is passed in the subsequent stages.