JPH05344371A - Protective circuit for preventing crt burning - Google Patents

Abstract

PURPOSE:To prevent beforehand the burning of CRT phosphor due to the projection of the same high-contrast still picture for a long time brought about by forgetting turning off the power. CONSTITUTION:An A/D conversion circuit 3 digitizes a luminance signal 21 for every one field and a subtraction circuit 5 subtracts one field data and the field data which had been digitized. If the subtraction circuit output is zero, the both signals are judged to be coincident. The comparison is performed for the prescribed time which is required for a counter 7 to count a vertical synchronizing signal at most and decided by the number of bits of the counter. When the subtraction circuit output remains zero during the prescribed time, the video is not changed. That is, it is discriminated as the still picture and a comparator 8 outputs a signal 24 to drop the contrast. When it becomes animation, the counter 7 is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the same still image having a high contrast for a long time when the color television receiver is used for a video game such as a NES, due to forgetting to turn off the power or leaving it for a long time. The present invention relates to a protection circuit for preventing the CRT phosphor from being burned in due to the projection of the above.

[0002]

2. Description of the Related Art In recent years, color television receivers are increasingly used as display devices for video games such as NES. Television broadcasts, VTRs, etc. are usually moving images, whereas video signals of such a video game continue to display a still image, that is, the same image, unless a key input is operated. Therefore, when the video signal has a high contrast and is left for a long time, the phosphor in the high-luminance portion is burnt, and the luminance efficiency of the portion is reduced, which causes problems such as uneven brightness and uneven color in the subsequent projection. ..
In a personal computer or the like that is always integrated with a keyboard, a measure to prevent the image sticking is taken by lowering the contrast by detecting the presence / absence of a key input. It is not possible to detect the presence or absence of key input.

[0003]

Therefore, when a normal color television receiver is connected to a Famicom or the like and a high-contrast still image is continuously projected for a long time, it is possible to prevent the burn-in of the CRT. It was difficult. The present invention is
In order to solve such a problem, the presence or absence of a change in the image state is monitored, and when it is determined that the image is the same image within a predetermined range of time and there is no image change, the contrast is automatically lowered to prevent the CRT from being burned. It is an object to provide a protection circuit designed to prevent the above.

[0004]

According to the present invention, whether a luminance signal is an interlace type signal, a non-interlace type signal, or a random interlace type signal is determined by a synchronizing signal separated from an input luminance signal. According to the field discriminating circuit for discriminating which is the field discriminating circuit and the discriminating signal from the field discriminating circuit, in the case of the interlace system, one of the luminance signals defined as the even field or the odd field is used as the non-interlace system or the random interlace In the case of the system, an A / D conversion circuit for converting the luminance signal of every other field from an analog signal into a digital signal, and pixel data composed of upper 4 bits of the digital signal output from the A / D conversion circuit are provided. A field memory for storing each field and the A / A subtracting circuit that outputs a level difference between both the converter output and the field memory output by subtracting,
A counter for counting the vertical synchronizing signal separated from the synchronizing signal and a level difference from the subtracting circuit are monitored for each required time until the maximum count number of the counter is reached, and there is no level difference between the required times. The present invention provides a CRT burn-in protection circuit composed of a comparator that outputs a signal to lower the contrast sometimes and a signal that resets the counter when a level difference is recognized during the required time. ..

[0005]

The brightness signal is converted into a digital signal every other field, and one field data is compared with the field data converted into a digital signal before that. This comparison is performed by the subtraction circuit using only the high-order bits representing the large amplitude portions of both data. Therefore, if the subtraction circuit output is zero, both signals can be judged to be the same. This comparison of the sameness is performed for a predetermined time. The predetermined time is a time required for the counter to count the vertical synchronization signal to the maximum, and is determined by the number of bits of the counter. When the output of the subtraction circuit continues to be zero for the required time (predetermined time), it is determined that the image has not changed, that is, a still image, and the comparator outputs a signal to reduce the contrast. Whenever the output of the subtraction circuit is not zero, the counter is reset each time, and in that state, no signal is output to reduce the contrast.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A CRT image sticking protection circuit according to the present invention will be described below with reference to the drawings. FIG. 1 shows a CR according to the present invention.
FIG. 3 is a block diagram of a main part showing an embodiment of a T-burn-in prevention / protection circuit. In the figure, 1 is a sync separation circuit for separating a sync signal from a brightness signal (Y signal) 21, and 2 is an input brightness signal.
A field discrimination circuit 3 for discriminating whether 21 is an interlace type signal, a non-interlace type signal or a random interlace type signal from the synchronizing signal, and 3 is a field discriminating circuit 2 for the analog luminance signal 21. A / D converter circuit 4 for converting into a digital signal every other field according to the discrimination signal 22 from the above, 4 uses the upper 4 bits from the digital signal output of the A / D converter circuit 3 as one pixel data, and this is used for every one field Field memory for sequentially storing and outputting to 5
Is a subtraction circuit that determines whether or not both signals are the same by subtracting the output of the A / D conversion circuit 3 and the output of the field memory 4, and 6 is a vertical synchronization signal from the synchronization output from the synchronization separation circuit 1. Integrating circuit for taking out only, 7 is a counter (V counter) for counting the vertical synchronizing signal, 8 is a comparator for monitoring the output of the subtracting circuit based on the count time of the counter 7, TR1 is under the control of the comparator 8,
A transistor for switching which is turned on when lowering the contrast, and 9 is a video signal processing circuit including contrast control.

Next, the operation of the present invention will be described. Scanning methods include interlace methods, non-interlace methods, and random interlace methods, but these methods differ in the arrangement of synchronization signals. That is,
In the interlace system, the even-numbered field and odd-numbered field differ in the arrangement relationship between the horizontal synchronizing signal in the vertical scanning period and the synchronizing signal (equivalent pulse, vertical synchronization, horizontal synchronization) in the vertical blanking period. Further, in the case of the non-interlace system, the synchronization signal array of each field (which may be called a frame in this case) is the same. Therefore, from the sync signal from the sync separation circuit 1, the phase of the horizontal sync signal after a fixed time from the rising of the vertical sync signal is detected, or the vertical sync signal is present after a fixed time from the horizontal sync signal of the 262th scanning line. Which method is used to determine which method is used. If none of the above, it is determined to be random interlace.

The A / D conversion of the A / D conversion circuit 3 is unified in either an even field or an odd field for interlaced signals. This unification is predetermined. In each of the non-interlaced and random methods, every other field is used. As a result, in every method, every other field is used. This is done to shorten the time required to determine whether or not the images are the same and to save the memory capacity of the field memory 4. In the present embodiment, the digital output of the A / D conversion circuit 3 has an 8-bit configuration for one pixel. The upper (MSB) 4 bits are used as the pixel data. This is to save the memory capacity of the field memory 4. However, since the high contrast component (large amplitude component) almost appears in these upper 4 bits,
It is considered that the video contents can be sufficiently grasped by monitoring this. The upper 4-bit pixel data is stored in the field memory 4 in units of one field, and is also sequentially input to the subtraction circuit 5. The data sequentially output from the field memory 4 is input to the subtraction circuit 5. The data from the field memory 4 is the data of the field immediately preceding the above data from the A / D conversion circuit 3. The subtraction circuit 5 subtracts both of them. By subtracting, if the result is zero, the images in the compared fields have the same content, and if the result is other than zero, the image content is different.

The subtracted data (level difference) of the subtraction circuit 5 is input to the comparator 8. The count data 23 from the counter 7 is further input to the comparator 8. Here, the counter 7 will be described. The role of the counter 7 is time management. The vertical synchronizing signal separated by the integrating circuit 6 is input to the counter 7. The counter 7 counts this vertical synchronizing signal, and the upper limit that can be counted is determined by the number of bits of the counter, and the time required to reach the upper limit is the product of the upper limit and the period of the vertical synchronizing signal. For example, in the case of the interlace system (NTSC system), the vertical cycle is 1/60 (seconds), and thus the required time Tm when counting this with a 16-bit or 18-bit counter is as follows. 16 bits → Tm = (1/60) × 65536 ≈ 18 (minutes) 18 bits → Tm = (1/60) × 262144 ≈ 72 (minutes) The above count data is sequentially input to the comparator 8 and in parallel with this. Data from the subtraction circuit 5 is monitored. Then, when the subtraction data continues to be zero within the range of Tm, it is determined that the image has not changed during the Tm, that is, in the still image state. However, this is an ideal case, and in practice, the subtraction data may be affected by noise or the like. Therefore, a constant K is given to the comparator 8 as the motion sensitivity, and when the subtraction data is a certain value or less, It is supposed to be zero (still image). Thus, when the still image state has passed for the time Tm, the comparator 8 outputs the contrast control signal 24. In this embodiment, a "high (H)" level signal is output. With this H signal
TR1 turns on and the contrast control terminal of the video processing circuit 9
The voltage of 10 is lowered and the contrast level of the video output signal 11 is lowered. The control terminal 10 is also a terminal to which a voltage based on the user's contrast adjustment (for example, a DAC DAC output) is applied.

The comparator 8 continues to output the H level during a still image, and resets the counter 7 with a reset signal 25 when a moving image is detected (subtraction data ≠ 0). By this reset, the H level becomes the "low (L)" level, and as a result, TR1 is turned off and the normal state is restored. on the other hand,
When the subtracted data in the comparator 8 is not zero before the time Tm elapses and is changing, it means that the image is a moving image. In this case, the counter 7 is reset by the reset signal 25 every time the motion is detected. Therefore, in this state, the H level is not output, and in the L state,
Continue to turn off TR1.

[0011]

As described above, according to the present invention, when a color television receiver is connected to a Famicom or the like and used for a video game or the like, when a high-contrast still image continues for a certain period of time, it is automatically Since the contrast is lowered, the phosphor burn-in of the CRT that occurs when left in the above state for a long time is prevented, which contributes to maintaining the quality performance of the color television receiver.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a burn-in protection circuit for a CRT according to the present invention.

[Explanation of symbols]

 1 sync separation circuit 2 field discrimination circuit 3 A / D conversion circuit 4 field memory 5 subtraction circuit 6 integration circuit 7 counter 8 comparator TR1 transistor 9 video signal processing circuit 21 brightness signal 22 discrimination signal 23 count data 24 contrast control signal 25 reset signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H04N 5/57 // G09G 1/16 F 8121-5G M 8121-5G

Claims (1)

[Claims] 1. A color television receiver provided with a video processing circuit capable of adjusting contrast by DC control, wherein the luminance signal is an interlace type signal or a non-interlaced signal according to a synchronizing signal separated from an inputted luminance signal. According to a field discriminating circuit for discriminating whether the signal is an interlace type signal or a random interlace type signal, and a discriminating signal from the field discriminating circuit, either an even field or an odd field in the case of the interlace method. In the case of the non-interlaced method or the random interlaced method, one of the determined luminance signals is an A / D conversion circuit for converting the luminance signal of every other field from an analog signal to a digital signal, and the output of the A / D conversion circuit. 4 of the digital signals of A field memory that stores pixel data consisting of bits for each field, a subtraction circuit that subtracts the output of the A / D conversion circuit and the output of the field memory and outputs a level difference between the two, vertical synchronization separated from the synchronization signal. A counter that counts signals and a level difference from the subtraction circuit are monitored for each time required to reach the maximum count of the counter, and a signal is output to reduce the contrast when there is no level difference during the time required. On the other hand, it is configured with a comparator that outputs a signal that resets the counter when a level difference is recognized during the required time, and the contrast is lowered when there is no change in the video signal within a fixed time. Characteristic CRT seizure prevention protection circuit.