JPH05344113A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To miniaturize the circuit and to reduce energy consumption by comparing the output bits of parallel/serial(P/S) converters for synchronizing patterns and received data with respectively correspondent converters and judging whether synchronizing patterns are detected or not corresponding to the number of coincident/noncoincident bits. CONSTITUTION:After performing S/P-conversion of received data by an S/P conversion circuit 31, the data are n-divided and respectively inputted to the (n) pieces of P/A converters 34-1-34-n for received data. On the other hand, the output synchronizing pattern of a synchronizing pattern designating register 32 is n-divided and respectively inputted to the (n) pieces of P/S converters 33-1-33-n for synchronizing pattern. A plural-bit comparator 35 compares the output bits of the converters 35-1-35-n and 34-1-34-n with the corresponding converters simultaneously for every (n) bits. Corresponding to the number of coincident/noncoincident bits as the compared results, a synchronizing pattern detection circuit 36 judges whether the synchronizing patterns are detected or not. Thus, since the comparison is performed simultaneously for every (n) bits, the frequency of an internal operating clock can be reduced into 1/n in comparison with the conventional frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit used in communication equipment using frame synchronization such as TDMA.

In general communication equipment using frame synchronization, or in electronic equipment having a communication function using frame synchronization, high functionality, miniaturization, and low power consumption are general problems, and therefore, frame It is necessary to reduce the size and power consumption of the synchronous circuit.

[0003]

2. Description of the Related Art FIG. 9 shows a conventional example of a frame synchronization circuit. Here, the received data is a serial burst signal having a frame structure. This frame includes a unique word UW (synchronization word) as a frame synchronization pattern, and the unique word UW1 to UW1.
There are A types of UWA.

Reference numeral 6 is a serial-parallel converter (hereinafter referred to as an S / P converter) for converting received data serially input into 1
Every time a bit is input, it is serial-parallel converted into N-bit parallel data and output. The N-bit parallel received data are input in parallel to the A match detection circuits 8-1 to 8-A. The coincidence detection circuits 8-1 to 8-A are provided corresponding to the A unique words UW1 to UWA, respectively.
It has a function of detecting the corresponding unique word UW.

The coincidence detection circuit 8 includes a unique word (UW) designation register 10, a parallel / serial converter (hereinafter, P /
81 and 82, a comparator circuit 83, an allowable error number setting register 12, an error counting circuit 13, a window width designation register 14, a window control circuit 15, and the like.

FIG. 10 shows the detailed structure around the comparison circuit of the coincidence detection circuit 8. The parallel reception data from the S / P converter 6 is the P / S converter 8 including a shift register.
1 and is serial-parallel converted by the internal processing clock CLK _IN , and its serial output bit is serially input to one input terminal of the comparison circuit 83 including an XOR circuit.

The UW designation register 10 stores the N-bit UW pattern of the unique word UW,
This UW pattern is input in parallel to the P / S converter 82 composed of a shift register every time 1 bit of received data is input, and serial-parallel converted by the internal processing clock CLK _IN , and its serial output bit is compared by the comparison circuit 83. Is serially input to the other input terminal of.

Here, as shown in FIG. 11A, the internal processing clock CLK _IN is the reception clock CLK _R.
N times the frequency. Therefore, the P / S converters 81 and 82 convert all the N-bit data input in parallel into serial data and output the same at a cycle in which one bit of received data is input to the S / P converter 6.

The comparison circuit 83 compares the output bits serially output from the P / S converters 81 and 82 for matching / mismatching bit by bit, and outputs a mismatching bit of "1" when they do not match. The number of unmatched bits is accumulated by the accumulator including the adder 131 and the flip-flop 132. Therefore, the total value is the number of unmatched bits obtained by comparing the parallel received data output from the S / P converter 6 and the unique word UW stored in the UW designation register in correspondence with each bit.

The determination circuit 135 determines the number of mismatched bits a.
Is compared with the allowable error number b as the unique word detection condition set in the allowable error number setting register 12, and if this allowable error number b or less, it is determined that the currently input received data is the unique word UW. , Outputs a match detection signal.

The output coincidence detection signal is shown in FIG.
Is input to the window control circuit 15 shown in FIG. The window control circuit 15 includes a window width designation register 14
Window width data is input from. The window control circuit 15 is adapted to generate a window having the window width at the predicted arrival position of the unique word and determine whether or not the coincidence detection signal is within the window, thereby making it similar to the unique word UW. The match detection signal outside the search range based on the received data is masked, and only the correct match detection signal is output to the synchronization determination protection circuit 3 through the protection stage number counting circuit 2.

The protection stage number counting circuit 2, the synchronization determination protection circuit 3, the counter 4, the decoder 5 and the like are circuits for performing synchronization protection, and since these are general circuits from the past, detailed description will be given. Omit it.

Frame synchronization is performed by combining the circuits that perform the above basic operations by the number of unique words UW to be used (A circuits are combined in this conventional example) and operating these circuits in parallel. It constitutes a circuit.

On the other hand, although the above-mentioned circuit requires a large amount of hardware, in order to reduce the hardware, one coincidence detection circuit may be used for a plurality of unique words UW in a time division manner. As an example of this, the case of detecting two unique words UW1 and UW2 is shown in FIG. 11B.
Shown in. That is, the frequency of the internal processing clock CLK _IN is set to 2N times the reception clock CLK _R , the unique word UW1 is searched in the first half of the 1-bit period of the received data, and the unique word UW2 is searched in the second half.

Generally speaking, the internal operation clock CLK when there is only one unique word UW to be detected.
_{Assuming that} the frequency of _IN is f ₁ , when the number of unique words UW to be detected is A, the frequency f _A of the internal operation clock CLK _IN is f _A = f ₁ × A.

[0016]

As described above, when there are a plurality of unique words UW to be detected, they are detected by operating separate coincidence detecting circuits in parallel as in the circuit of FIG. If the circuit is configured in this manner, the amount of hardware will increase.

Therefore, as described in the example of FIG. 11B, if one coincidence detection circuit is used to detect a plurality of unique words UW in a time division manner, the frequency of the internal operation clock thereof. Becomes higher, which increases current consumption and power consumption.

Even when only one unique word UW is detected, the internal operation clock CLK _IN is considerably faster than the reception clock CLK _R , and therefore the current consumption is large. It is necessary to lower the voltage as much as possible to achieve low power consumption.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the size and power consumption of a frame synchronization circuit.

[0020]

FIG. 1 is an explanatory view of the principle of the present invention. As a first form, the frame synchronization circuit of the present invention includes a serial-parallel conversion circuit 31 that serial-parallel converts received data, a synchronization pattern designation register 32 that stores a synchronization pattern, and a synchronization pattern output from the synchronization pattern designation register 32. n parallel pattern serial-to-serial converters 33-1 to 3n, to which the divided sync patterns divided by n are respectively input
33-n, n parallel parallel converters for reception data 34-1 to 34-n to which parallel parallel reception data obtained by dividing the parallel output of the serial-parallel converter 31 by n are respectively input, and n parallel patterns for synchronization pattern A serial-pattern converter for synchronization pattern and a received data for which the output bits of the serial converters 33-1 to 33-n and the output bits of the n parallel data serial converters 34-1 to 34-n respectively correspond The parallel-serial converter is provided with a plurality of bit comparison circuits 35 for comparison, and a synchronization pattern detection circuit 36 for determining the presence / absence of synchronization pattern detection based on the number of coincidence / disagreement bits of the comparison result of the plurality of bit comparison circuits 35 It is a thing.

The above-mentioned synchronization pattern detection circuit is an error counting circuit for counting the number of coincidence / non-coincidence bits of the comparison result of the bit comparison circuit, an error tolerance number setting register for storing the error tolerance number as a synchronization pattern detection condition, and It can be configured by a determination circuit that compares the error allowable number of the error allowable number setting register with the count value of the counting circuit and determines whether or not the synchronization pattern detection condition is satisfied.

As a second form of the frame synchronization circuit of the present invention, in the frame synchronization circuit described above, there are a plurality of types of synchronization patterns, one of which is sequentially selected by the selection means and n synchronization patterns are selected. Configured to input to a parallel-to-serial converter.

As a third mode, the frame synchronization circuit of the present invention is the same as the second frame synchronization circuit described above.
There are a plurality of allowable error numbers as detection conditions according to the plurality of types of synchronization patterns, and an error allowable number corresponding to the synchronization pattern selected by the selecting means is selected by the second selecting means and input to the determination circuit. Configured to do.

As a fourth form of the frame synchronizing circuit of the present invention, the frame synchronizing circuit of the first form and the frame synchronizing circuit of the second form are combined to form a serial / parallel conversion circuit in each frame synchronizing circuit. It is configured to be commonly used.

[0025]

In the frame synchronization circuit of the first embodiment, the serial-parallel conversion circuit 31 serial-parallel converts the received data, the serial-parallel converted parallel received data is divided into n, and each divided parallel received data is divided into n pieces. Received data parallel-to-serial converter 34-1 ~
Input to 34-n. On the other hand, the synchronization pattern designation register 3
The synchronization pattern output from the No. 2 is divided into n, and the divided synchronization patterns are input to n synchronization pattern parallel-serial converters 33-1 to 33-n, respectively.

In the multi-bit comparison circuit 35, the output bits of the n synchronization pattern parallel / serial converters 33-1 to 33-n and the n received data parallel / serial converters 34-1 to 34-n are output. The bits are compared with each other at the same time by n bits at a time between the parallel serial converter for synchronization pattern and the parallel serial converter for received data. The sync pattern detection circuit 36 determines the presence or absence of sync pattern detection based on the number of coincidence / non-coincidence bits of the comparison result of the multiple bit comparison circuit 35.

As described above, in the multi-bit comparison circuit 35, the bit matching / mismatching between the received data and the sync pattern is determined by n.
Since it is performed bit by bit at the same time, the frequency of the internal operation clock can be made 1 / n of the conventional frequency.

In the frame synchronization circuit of the second form,
When there are a plurality of types of synchronization patterns to be detected, one of them is sequentially selected by the selection means and input to the n synchronization pattern parallel-serial converters. As a result, it becomes possible to detect a plurality of synchronization patterns with a small circuit and with a low internal operation clock.

In the frame synchronizing circuit of the third form,
A plurality of error allowable numbers as detection conditions are provided in accordance with the plurality of types of synchronization patterns, and the error allowable number corresponding to the synchronization pattern selected by the selecting unit is selected by the second selecting unit from the determination circuit. input. Thereby, the detection condition of the synchronization pattern can be changed according to the type of the synchronization pattern.

In the frame synchronizing circuit of the fourth mode,
By combining the frame synchronization circuit of the first form and the frame synchronization circuit of the second form described above, for example, a plurality of synchronization patterns having the same detection condition and another synchronization pattern having a different detection condition can be searched. Can be done at the same time.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. A frame synchronization circuit as an embodiment of the present invention is shown in FIG. This frame synchronization circuit detects A unique words UW1 to UWA as unique words UW, and the bit number B of each unique word UW is 6n bits (where n is 2 or more and less than B). integer).

The serial reception data is input to the coincidence detection circuit 1 via the S / P converter 6. Match detection circuit 1
Are A UW specification registers 10-1 to 10-A, a plural-bit simultaneous comparison circuit 11, and A error allowable number setting registers 1
2-1 to 12-A, error counting circuit 13, A number of window width designation registers 14-1 to 14-A, window control circuit 15
Etc.

Here, the UW designation registers 10-1 to 10-A
Stores the bit patterns (6n bits) of the unique words UW1 to UWA, respectively. Further, each unique word U is stored in the allowable error count setting registers 12-1 to 12-A.
Each unique word UW1 corresponding to W1-UWA
Stored is the allowable error bit number b as a detection condition of UWA. Window width specification registers 14-1 to 14-A
The window width of each unique word UW1 to UWA is stored in the corresponding to each unique word UW1 to UWA.

From the coincidence detection circuit 1, each unique word U
Match detection signals are output corresponding to W1 to UWA, respectively, and these are input to the synchronization determination protection circuit 3 via the synchronization stage number counting circuits 2-1 to 2-A, respectively.

FIG. 3 shows a detailed configuration example around the multi-bit simultaneous comparison circuit 11, and FIG. 4 shows a detailed configuration example around the error counting circuit 13.

In FIG. 3, n UW P / S converters 112-1 to 112-n, which are shift registers, are provided as circuits for parallel-serial conversion of the unique word UW of the UW designation register for bit comparison. .. Further, n pieces of reception data P / S converters 11 each composed of a shift register as a circuit for performing parallel / serial conversion for bit comparison of reception data.
3-1 to 113-n are provided. These P / S converters 11
2-1 to 112-n and 113-1 to 113-n are each for inputting 6-bit parallel data and converting it into serial data.

The outputs of the UW specification registers 10-1 to 10-A are input to the selector 111, and the selector 11
One of them is selected by 1 and output. Here, the UW pattern of the output of the UW designation register 10 is 6n.
Although it is a bit, on the output side of the selector 111, this U
The W pattern is divided into n of 6 bits, each of which is n
It is distributed and input to the U / W P / S converters 112-1 to 112-n. That is, the 6n bits of the UW pattern are B (1)
~ B (6n), 6 bits of B (1) to B (6) are UW
6 bits of B (7) to B (12) are supplied to the U / W P / S converter 112-2, ... B (6n-5) to B
The 6 bits of (6n) are input to the UW P / S converter 112-n.

Similarly, 6 output from the S / P converter 6
The n-bit parallel reception data is also divided into n, and n pieces of reception data P / S converters 113-1 are provided as in the unique word side.
~ 113-n are distributed and input. That is, if the 6n bits of the parallel reception data are B (1) to B (6n), B (1) to B (6n)
6 bits of (6) is the P / S converter 113-1 for received data
6 bits of B (7) to B (12) are received by the P / S converter 113-2 for received data, and 6 bits of B (6n-5) to B (6n) are received by the P / S converter 113-2. It is input to the / S converter 113-n.

The comparison circuit 114 includes n XOR circuits 114.
-1 to 114-n, UW P / S converter 11
2-1 to 112-n and P / S converter for received data 113-1 to
The output bits of 113-n correspond to UW P / P so that corresponding bits can be compared for bit match / mismatch.
S converter 112-1 and received data P / S converter 113-1
Output bits of XOR circuits 114-1 to XOR circuits 114-1 ...
Input to 4-n respectively. Accordingly, the comparison circuit 114
Allows simultaneous comparison of n bits.

In FIG. 4, the error counting circuit 13 includes an adder circuit 131, a flip-flop 132 and a selector 13.
4, an error number comparison circuit 135 and the like are included. The adder circuit 131 and the flip-flop 132 have an accumulator configuration, and the adder circuit 131 is a comparator circuit 114.
The n non-matching bit signals from are input and added to the previous integrated value. The unmatched bit number a of the addition result is transferred to the error number comparison circuit 1 via the flip-flop 132.
35 is input.

The selector 134 selects the error allowable number setting register corresponding to the unique word UW selected by the selector 111 from the error allowable number setting registers 12-1 to 12-A and sets the error allowable number b to an error. Number comparison circuit 135
To enter. The error number comparison circuit 135 outputs a match detection signal when the number of mismatch bits a is equal to or less than the error allowable number b (that is, a ≦ b).

The operation of this embodiment circuit will be described below with reference to the time chart of FIG. In FIG. 3, every time 1 bit of the received data is input, the S / P converter 6 serial-parallel converts it into 6n-bit parallel data, and the parallel received data is divided into n by 6 bits for each received data. It is input to the P / S converters 113-1 to 113-n.

Further, the selector 111 first selects the UW designation register 10-1, and the pattern of the unique word UW1 is divided into n and each P / S converter 112 for UW.
-1 to 112-n.

These parallel input data are sent to the UW P / S converters 112-1 to 112-n and the received data P / S.
One bit is serially read from each of the converters 113-1 to 113-n, and a match / mismatch between the corresponding bit of the unique word UW and the corresponding bit of the received data indicates the XOR circuits 114-1 to 114 of the comparison circuit 114. -n is compared. That is, the comparison circuit 114 simultaneously compares the received data and the unique word UW1 for bit coincidence / non-coincidence n bits at a time. The number of unmatched bits is shown in FIG.
Are sequentially accumulated in the adder circuit 131 of the error counting circuit 13.

Therefore, with respect to the unique word UW1, it is possible to calculate the number of mismatching bits a between the received data and the pattern of the unique word UW1 stored in the UW designation register 10-1 when the internal operation clock CLK _IN is 6 clocks. it can.

The mismatch bit number a as the result of this calculation is input to the error number comparison circuit 135 in FIG.
Compared with the allowable error number b of the unique word UW1 selected in step 1, if the detection condition that the number of unmatched bits a is less than the allowable error number b is satisfied, the match detection signal of the unique word UW1 is output.

When the search for the unique word UW1 is completed, the search for the unique word UW2 is performed by the next 6 bits of the internal operation clock CLK _IN , and the search is performed for the A-th unique word UWA in the same manner. Therefore, the internal clock is 6 × A clock for one clock of the reception clock.

In the window control circuit 15 at the subsequent stage in FIG. 2, the counter 4, the decoder 5, and the window width designation register 14 are used for the detection signals of the unique words UW1 to UWA based on the window reference timing signal.
-1 to 14-A is used to individually determine the window for each of the A unique words UW1 to UWA (the match detection signal of each unique word UW1 to UWA corresponds to each unique word UW1 to UWA. By determining whether it is in the window)
Correct detection is performed by masking the match detection signal outside the search range by the received data similar to the unique word UW,
The operation of outputting the coincidence detection signal to the synchronization determination protection circuit 3 can be performed for each unique word.

According to this embodiment, the frequency f _n of the internal operation clock CL _IN is f _n = f ₁ × A / n. However, f ₁ is the unique word U as described above.
The frequency of the internal operation clock of the conventional circuit when W is one, and A is the number of unique words UW when there are a plurality of unique words UW.

At this time, received data (bit rate is C
The time required to receive 1 bit is 1 / C
And within this time A unique words UW1-U
In order to perform the WA coincidence detection operation, when the frequency of the internal operation clock is DHz, the number of multiple simultaneous comparisons (that is, the number of divisions of parallel reception data) is n, and the number of bits of the unique word UW is B, It is sufficient that the condition C ≧ (A × B) / (D × n) is satisfied, whereby the all unique words UW
It is possible to compare bits 1 to UWA.

6 and 7 show another embodiment of the present invention. In this embodiment, the unique words UW to be detected are two kinds of 20-bit unique words UW.
1, UW2 and one unique word U of 32 bits
This is a case where the total of three types, W3, is used. In the figure, the same reference numerals are attached to circuit components having the same functions as those of the above-described embodiment.

In FIG. 6, UW designation registers 10-1 and 10-2 are registers for storing 20-bit data, and UW patterns of unique words UW1 and UW2 are stored therein, respectively. The UW designation register 10-3 is a register for storing 32-bit data, and the unique word UW3
UW pattern is stored.

The selector 111 is the UW designation register 10-1.
And the circuit that selects one of 10-2, the selected UW
The pattern output is divided into two parts of 10 bits each, and P for UW
It is input to the / S converters 112-1 and 112-2, respectively.
The UW3 pattern output of the UW specification register 10-3 is 1
The PW / S converter 116 for UW is divided into 6 bits each.
-1, 116-2 is input.

The serial reception data is converted into 32-bit parallel reception data by the S / P converter 6, and the 32-bit parallel reception data is converted into 16 bits at a time from the MSB side and the LSB.
The two divided data are input to the received data P / S converters 115-1 and 115-2, and 10 bits from the LSB side of the 32-bit parallel received data are received data P / S converters. 113-1 to the next 11 bits ~
20 bits are input to the received data P / S converter 113-2. Depending on the timing relationship between the 20-bit UW and the 32-bit UW, each of the received data P / S converters 113-1 and 113-2 may be divided into 10 bits from the MSB side.
It is also possible to input into the configuration.

The output bits of the UW P / S converters 112-1 and 112-2 and the received data P / S converters 113-1 and 113-2 are respectively output by XOR circuits 114-1 and 114-2. The comparison is performed, and the comparison result is input to the adding circuit 118.
The output bits of the UW P / S converters 116-1 and 116-2 and the received data P / S converters 115-1 and 115-2 are compared by XOR circuits 117-1 and 117-2, respectively. ,
The comparison result is input to the adder circuit 119.

The error counting circuit at the subsequent stage is the same as that of the above-mentioned embodiment, and as shown in FIG.
The error counting circuits on the W1 and UW2 sides include an adder circuit 131, a flip-flop 132, and an allowable error number setting register 12-1.
The allowable error number setting register 12-1 stores the allowable error number as a detection condition common to the unique words UW1 and UW2. on the other hand,
The error counting circuit on the side of the unique word UW3 is the addition circuit 1
36, a flip-flop 137, an allowable error number setting register 12-3 and an error number comparing circuit 138. The allowable error number setting register 12-3 stores the allowable error number as a detection condition of the unique word UW3.

Further, the window control circuit and the protection stage number counting circuit in the subsequent stage are the same as those in the above-mentioned embodiment except that there are two systems of circuits for the unique words UW1 and UW2 and the unique word UW3. Detailed explanation is omitted.

The operation of the circuit of this embodiment will be described below with reference to FIG. The search operation for the unique words UW1 and UW2 is the same as that in the above-described embodiment, and the received data 1
Set the internal operation clock CLK _IN to 1 in the first half of the bit period.
The unique word UW1 is searched using 0 clock, and subsequently the unique word UW2 is searched using 10 clocks of the internal operation clock CLK _IN . Each unique word UW1 in the multiple bit simultaneous comparison circuit
And UW2 are searched by simultaneous 2-bit comparison.

The search for the unique word UW3 is performed in parallel with the search for the unique word words UW1 and UW2. That is, the unique word UW3 is searched using the internal operation clock CLK _IN for 16 clocks in the first half of the 1-bit period of the received data. The search for the unique word UW3 in the plural-bit simultaneous comparison circuit is also performed by the two-bit simultaneous comparison.

The operation of the circuit in the subsequent stage is the same as that of the above-mentioned embodiment. That is, in the error counting circuit, the comparison results are added, and the result is compared with the allowable number of errors to make a match detection determination. After the window control circuit determines whether or not a match is detected in the window, the protection stage number counting circuit counts the number of protection stages, and finally performs the synchronization determination.

[0061]

As described above, according to the present invention, the frequency of the internal operation clock can be suppressed to a low level and the increase in the circuit scale can be suppressed. Therefore, the frame synchronizing circuit can be downsized and the power consumption can be reduced. Can be planned.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a frame synchronization circuit as one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a multiple-bit simultaneous comparison circuit in the embodiment circuit.

FIG. 4 is a diagram showing a configuration example of an error number counting circuit in the embodiment circuit.

FIG. 5 is a time chart of an example circuit.

FIG. 6 is a diagram showing a configuration example of a multi-bit simultaneous comparison circuit of a frame synchronization circuit as another embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of an error counting circuit, a window control circuit, a protection stage number counting circuit, etc. of a frame synchronization circuit as another embodiment of the present invention.

FIG. 8 is a time chart of another embodiment circuit.

FIG. 9 is a diagram showing a conventional example of a frame synchronization circuit.

FIG. 10 is a diagram showing a configuration example of a match detection circuit portion of a conventional example circuit.

FIG. 11 is a time chart of a conventional circuit.

[Explanation of symbols]

1 coincidence detection circuit 2-1 to 2-A protection stage number counting circuit 3 synchronization determination protection circuit 4 counter 5 decoder 6 S / P converter 10-1 to 10-A UW designation register 11 multiple bit simultaneous comparison circuit 12-1 to 12-A error allowable number setting register 13 error counting circuit 14-1 to 14-A window width designation register 15 window control circuit 111, 134 selector 112-1 to 112-n, 116-1, 116-2 UW P /
S converters 113-1 to 113-n, 115-1 and 115-2 P / S converter for received data 114 Comparison circuit 114-1 to 114-n XOR circuit (exclusive OR circuit) 131, 118, 119 136 adder circuit 132 137 flip-flop 135 error number comparison circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Koji Chiba 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. A serial-parallel conversion circuit (31) for serial-parallel conversion of received data, and a synchronization pattern designation register (3) for storing a synchronization pattern.
2), n sync pattern parallel-to-serial converters (33-1 to 33-) to which the divided sync patterns obtained by dividing the sync pattern output from the sync pattern designation register into n are respectively input
n), n parallel / serial converters for reception data (34-1 to 34-n) to which the divided parallel reception data obtained by dividing the parallel output of the serial / parallel converter by n are respectively input, and the n synchronization patterns Bit comparison for comparing the output bits of the parallel-to-serial converter for reception and the output bits of the parallel-to-serial converter for reception data of the n-pieces between the corresponding serial-to-serial converter for synchronization pattern and the parallel-to-serial converter for reception data Circuit (3
5), and a frame synchronization circuit including a synchronization pattern detection circuit (36) for determining the presence or absence of synchronization pattern detection based on the number of coincidence / non-coincidence bits of the comparison result of the multiple bit comparison circuit. 2. The synchronization pattern detection circuit is an error counting circuit for counting the number of coincidence / disagreement bits of the comparison result of the bit comparison circuit, and an error tolerance number setting register for storing an error tolerance number as a synchronization pattern detection condition. 2. The frame synchronization circuit according to claim 1, further comprising: a determination circuit that determines whether or not a synchronization pattern detection condition is satisfied by comparing the error tolerance number of the error tolerance number setting register with the count value of the counting circuit. 3. The synchronization pattern has a plurality of types, and one of the synchronization patterns is sequentially selected by a selection means and input to the n synchronization pattern parallel-serial converters.
Alternatively, the frame synchronization circuit described in 2. 4. The allowable number of errors as the detection condition is plural according to the plurality of kinds of synchronization patterns, and the allowable number of errors corresponding to the synchronization pattern selected by the selecting means is selected from the second by the second selecting means. The frame synchronization circuit according to claim 3, wherein the frame synchronization circuit is configured to be input to the determination circuit. 5. A frame synchronization circuit configured such that the frame synchronization circuit according to claim 1 and the frame synchronization circuit according to claim 3 are combined and a serial-parallel conversion circuit in each frame synchronization circuit is commonly used.