JPH0533535B2 - - Google Patents
Info
- Publication number
- JPH0533535B2 JPH0533535B2 JP18090185A JP18090185A JPH0533535B2 JP H0533535 B2 JPH0533535 B2 JP H0533535B2 JP 18090185 A JP18090185 A JP 18090185A JP 18090185 A JP18090185 A JP 18090185A JP H0533535 B2 JPH0533535 B2 JP H0533535B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- pin
- heat sink
- wiring
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920006015 heat resistant resin Polymers 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000004033 plastic Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、ピングリツドアレイに関する。[Detailed description of the invention] (Industrial application field) The present invention relates to pin grid arrays.
（従来の技術）
従来、半導体装置のパツケージとして、デユア
ルインラインパツケージ（以下、DIPという。）
が大部分を占めていたが、最近のLSIチツプの高
集積化や電子装置の小型化、高性能化に対する要
求の増大により装置のピン数が増大するようにな
り、DIPではピン数の増加に限界があるため、最
近では、セラミツク基板にピンを複数列立設した
ピングリツドアレイが開発され、実用に供されて
きている。(Prior art) Dual in-line packages (hereinafter referred to as DIPs) have traditionally been used as packages for semiconductor devices.
However, the number of pins in devices has increased due to the recent increase in the integration of LSI chips, the miniaturization of electronic devices, and the increasing demand for higher performance. Because of the limitations, pin grid arrays, in which multiple rows of pins are erected on a ceramic substrate, have recently been developed and put into practical use.
（発明が解決しようとする問題点）
しかしながら、従来のピングリツドアレイパツ
ケージは、セラミツク製基板を採用しているた
め、コストが高く、しかも基板を大きくすると共
に、回路を微細化することは困難であるという問
題がある。このため、プリント配線基板技術を応
用した比較的安価なプラスチツク製のピングリツ
ドアレイが開発されているが、製造工程での管理
を厳しくしなければ高精度のものが得られず、ま
た熱伝導を高めるため金属製放熱板を組み込む
と、接合工程や接合部の封止工程など製造工程が
増加するなどの問題があつた。(Problems to be solved by the invention) However, the conventional pin grid array package uses a ceramic substrate, which is expensive, and it is difficult to increase the size of the substrate and miniaturize the circuit. There is a problem that. For this reason, relatively inexpensive plastic pin grid arrays have been developed using printed wiring board technology, but high precision cannot be obtained without strict control during the manufacturing process, and thermal conductivity Incorporating a metal heat sink to increase the heat dissipation caused problems, such as the need for additional manufacturing steps such as bonding and sealing of joints.
（問題点を解決するための手段）
本発明は、前記問題を解決する手段として、開
口部を有するプラスチツク製ベースフイルムの表
面に配線パターンを形成してなる配線基板と、該
配線基板に立設された前記配線パターンに接続さ
れた複数のピンと、前記配線基板の開口部を覆う
ように配線基板上に配置された金属製放熱板の周
縁部とを耐熱性樹脂で封止して一体化してなるこ
とを特徴とするピングリツドアレイを提供するも
のである。(Means for Solving the Problems) As a means for solving the above-mentioned problems, the present invention provides a wiring board in which a wiring pattern is formed on the surface of a plastic base film having an opening, and A plurality of pins connected to the wiring pattern and a peripheral edge of a metal heat sink disposed on the wiring board so as to cover the opening of the wiring board are sealed and integrated with a heat-resistant resin. This invention provides a pin grid array characterized by the following.
（作用）
本発明は、配線基板と、ピンと、放熱板とを封
入成形して一体化することによりピングリツドア
レイの信頼性を高めると同時に、製造工程の簡略
化を図り低コスト化を図るものであり、プラスチ
ツク製のベースフイルムからなる配線基板は半導
体装置の薄型化に寄与し、放熱板は放熱板として
機能し、配線基板の開口部から露出している放熱
板の表面に装着される半導体チツプからの放熱散
性を高め、また耐熱性樹脂は配線基板を放熱板及
びピンと共に一体に封止し、機械的強度、耐熱衝
撃性及び加工精度の向上、製造工程の簡略化に寄
与する。(Function) The present invention improves the reliability of the pin grid array by integrally molding the wiring board, pins, and heat sink, and at the same time, simplifies the manufacturing process and lowers costs. The wiring board made of a plastic base film contributes to the thinning of semiconductor devices, and the heat sink functions as a heat sink and is attached to the surface of the heat sink exposed through the opening of the wiring board. It improves heat dissipation from the semiconductor chip, and the heat-resistant resin seals the wiring board together with the heat sink and pins, contributing to improved mechanical strength, thermal shock resistance, processing accuracy, and simplification of the manufacturing process. .
（実施例）
以下、本発明の実施例について添付の図面を参
照して説明する。(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.
本発明に係るピングリツドアレイの一実施例を
示す図において、１はポリイミド樹脂、エポキシ
樹脂などのプラスチツク材料製ベースフイルムか
らなる配線基板、２は良導電性金属材料からなる
ピン、３は銅又はアルミニウムなど良熱伝導性金
属材料からなる放熱板、４は配線基板と、ピンと
放熱板とを一体に封じ込める封止部で、ポリフエ
ニレンサルフアイド、エポキシ樹脂などの耐熱性
樹脂から形成されている。 In the diagram showing an embodiment of the pin grid array according to the present invention, 1 is a wiring board made of a base film made of a plastic material such as polyimide resin or epoxy resin, 2 is a pin made of a highly conductive metal material, and 3 is copper. or a heat sink made of a metal material with good thermal conductivity such as aluminum; 4 is a sealing part that integrally seals the wiring board, the pins, and the heat sink, and is made of a heat-resistant resin such as polyphenylene sulfide or epoxy resin; There is.
配線基板１は、その中央部に開口部５を有し、
そのベースフイルムの表面に、第２図に示すよう
に、開口部５の近傍から放射状に伸張した配線パ
ターン６を形成したもので、ベースフイルム及び
配線パターン６を貫通して複数の貫通孔７が形成
されている。 The wiring board 1 has an opening 5 in its center,
As shown in FIG. 2, a wiring pattern 6 extending radially from the vicinity of the opening 5 is formed on the surface of the base film, and a plurality of through holes 7 are formed through the base film and the wiring pattern 6. It is formed.
本発明に係るピングリツドアレイは、配線基板
１が薄肉のプラスチツクフイルムで形成されてい
るため、配線基板と配線パターンとの接合強度が
低く、そのため配線パターンとピンをハンダ付け
してもその強度は向上せず、しかもハンダ付けに
よる面接合では、ハンダ付け加工が繁雑で、ハン
ダ付け加工後に洗浄工程が必要になることから、
ピン２の取り付けの容易化を図り、ピン２を確実
に固定するため、貫通孔７の周囲の配線パターン
６をリング状に形成する一方、貫通孔７に嵌入さ
れるピン２の頭部側近傍に大径の段部２ａを形成
し、頭部２ｂを配線基板１の貫通孔７に挿入した
後、ハンマーリング等によりかしめて、その頭部
２ｂと段部２ａとの間に配線基板１を挟持させる
ことによりピン２を配線基板１に固定すると共
に、配線パターン６に接続するようにしている。 In the pin grid array according to the present invention, since the wiring board 1 is formed of a thin plastic film, the bonding strength between the wiring board and the wiring pattern is low. Moreover, the soldering process is complicated and requires a cleaning process after the soldering process.
In order to facilitate the attachment of the pin 2 and securely fix the pin 2, the wiring pattern 6 around the through hole 7 is formed into a ring shape, and the wiring pattern 6 near the head side of the pin 2 inserted into the through hole 7 is formed in a ring shape. After forming a large-diameter stepped portion 2a on the top and inserting the head 2b into the through hole 7 of the wiring board 1, the wiring board 1 is crimped with a hammer ring or the like, and the wiring board 1 is inserted between the head 2b and the stepped portion 2a. By sandwiching the pins 2, the pins 2 are fixed to the wiring board 1 and connected to the wiring pattern 6.
放熱板３は配線基板１の開口部５に面する側に
該開口部５とほぼ同面積の凹所９が形成される一
方、周縁部３ａに突起１０が形成され、周縁部３
ａを配線基板１及びピン２と耐熱性樹脂で封入成
形することにより配線基板１及びピン２と一体化
されている。なお、１１はスタンドオフで、ピン
グリツドアレイをピンソケツトやマザー基板等に
装着した際、マザー基板等との間に一定の間隔を
あけるためのもので、ピングリツドアレイの任意
の位置にそれぞれ封止部４と一体成形されてい
る。また、封止部４にはピン２の頭部２ｂに達す
る穴１２が形成されているが、この穴１２は封入
成形時にピン２を押圧固定する可動ピン１９によ
り形成される。２０は防湿用保護皮膜で、エポキ
シ系あるいはポリイミド系樹脂をコーテイングす
ることにより形成されている。 The heat sink 3 has a recess 9 having approximately the same area as the opening 5 on the side facing the opening 5 of the wiring board 1, and a protrusion 10 on the peripheral edge 3a.
A is integrated with the wiring board 1 and the pins 2 by encapsulating and molding the wiring board 1 and the pins 2 with a heat-resistant resin. In addition, 11 is a standoff, which is used to leave a certain distance between the pin grid array and the mother board when it is attached to a pin socket, mother board, etc., and can be placed at any position on the pin grid array. It is integrally molded with the sealing part 4. Further, a hole 12 reaching the head 2b of the pin 2 is formed in the sealing portion 4, and this hole 12 is formed by a movable pin 19 that presses and fixes the pin 2 during encapsulation molding. Reference numeral 20 denotes a moisture-proof protective film, which is formed by coating with epoxy or polyimide resin.
前記構造のピングリツドアレイは次のようにし
て製造できる。即ち、予め用意した段付きのピン
２の頭部２ｂを配線基板１の貫通孔７に嵌入し、
ピン２の頭部２ｂに振動やハンマーリングにより
ピン２をかしめて、配線基板１にピン２を固定す
ると同時に配線パターンとピン２とを電気的に接
続する。この配線基板１は、第３図に示すよう
に、下型１５のキヤビテイ１７内に配置され、放
熱板３を配線基板１の開口部５を覆うようにセツ
トした後、上型１８を降下させて型閉めし、耐熱
性樹脂をキヤビテイ１７に射出して封入成形する
ことにより製造できる。 The pin grid array having the above structure can be manufactured as follows. That is, the head 2b of the stepped pin 2 prepared in advance is inserted into the through hole 7 of the wiring board 1,
The pin 2 is caulked to the head 2b of the pin 2 by vibration or hammering to fix the pin 2 to the wiring board 1 and at the same time electrically connect the wiring pattern and the pin 2. As shown in FIG. 3, this wiring board 1 is placed in the cavity 17 of the lower mold 15, and after the heat sink 3 is set to cover the opening 5 of the wiring board 1, the upper mold 18 is lowered. It can be manufactured by closing the mold, injecting heat-resistant resin into the cavity 17, and enclosing it.
なお、配線基板の製造は、まずベースフイルム
にスリツト加工を施し、脱脂、乾燥後、化学銅メ
ツキの付着を容易にするためベースフイルムの全
面に触媒ペーストを塗布、乾燥させた後、スタン
ピング加工し、配線パターン６を形成すべき部位
以外の部位にレジストインキをスクリーン印刷し
てマスクし、次いで化学銅メツキ法により銅メツ
キを施し、該銅メツキ上に電気銅メツキ、電気銀
メツキを積層して配線パターンを形成し、配線パ
ターン６の表面とレジストインキ層との間に凹凸
の無い平滑な配線基板とするのが好ましいが、公
知のフレキシブル印刷配線基板の製造方法と同様
にして製造することもできる。 In the manufacturing of wiring boards, the base film is first slit, then degreased and dried. Catalyst paste is applied to the entire surface of the base film to facilitate the adhesion of chemical copper plating. After drying, stamping is performed. , screen print resist ink on areas other than those where the wiring pattern 6 is to be formed to mask them, then apply copper plating using a chemical copper plating method, and layer electrolytic copper plating and electrolytic silver plating on the copper plating. Although it is preferable to form a wiring pattern and create a smooth wiring board with no unevenness between the surface of the wiring pattern 6 and the resist ink layer, it is also possible to manufacture it in the same manner as a known method for manufacturing a flexible printed wiring board. can.
本発明は、前記実施例に限定されるものではな
く、種々に変形することができる。例えば、前記
実施例では、段付きピン２として一端側に一重の
段を有するピンを採用しているが、これは第４図
に示すように、ピン２に段を二重にあるいは３重
以上設け、頭部２ｂ側の段部２ａと頭部２ｂとの
間で配線基板１をかしめる一方、その段部２ａと
その下側の段部２a′との間に形成される空間部２
ｃに耐熱性樹脂を廻り込ませてピン２の引抜力を
一段と向上させることもできる。 The present invention is not limited to the embodiments described above, and can be modified in various ways. For example, in the above embodiment, a pin having a single step on one end is used as the stepped pin 2, but as shown in FIG. The wiring board 1 is caulked between the step 2a on the side of the head 2b and the head 2b, while the space 2 formed between the step 2a and the step 2a' on the lower side is
It is also possible to further improve the pulling force of the pin 2 by wrapping a heat-resistant resin around c.
また、配線基板１の配線パターン６と反対側の
表面に貫通孔を包囲する金属リングを形成し、該
金属リングをもベースフイルム及び配線パターン
６と共に、ピン２の頭部と段部２ａとの間に挾持
させ、ピン２をより強固に取り付けることができ
るようにしても良い。 Further, a metal ring surrounding the through hole is formed on the surface of the wiring board 1 opposite to the wiring pattern 6, and the metal ring is also connected to the head of the pin 2 and the stepped portion 2a together with the base film and the wiring pattern 6. It is also possible to sandwich the pin 2 between them so that the pin 2 can be more firmly attached.
さらに、前記実施例では、配線基板１に一つの
開口部５を形成し、一つの半導体チツプを装着で
きるようにしているが、第５図に示すように、二
つの開口部５を設けるか、あるいはそれ以上の数
の開口部５を設け、各開口部５から露出している
放熱板３の表面に半導体チツプをそれぞれ搭載す
るようにすることもできる。 Further, in the above embodiment, one opening 5 is formed in the wiring board 1 so that one semiconductor chip can be mounted therein, but as shown in FIG. 5, two openings 5 may be provided. Alternatively, a larger number of openings 5 may be provided, and semiconductor chips may be mounted on the surface of the heat sink 3 exposed through each opening 5.
（発明の効果）
以上の説明から明らかなように、本発明によれ
ば、配線基板を使用し、金型を用いて配線基板を
ピン及び放熱板と一体に封入成形するようにした
ので、ピングリツドアレイの薄型化及び低コスト
化を図ることができ、しかも50μｍ程度の高寸法
精度で信頼性の高いピングリツドアレイを製造で
きる。また、封止部と放熱板が配線基板と一体化
されているため、曲げ強度、耐機械的衝撃性及び
耐熱衝撃性に優れ、しかも熱放散性に優れたピン
グリツドアレイを製造できるなど優れた効果が得
られる。(Effects of the Invention) As is clear from the above description, according to the present invention, a wiring board is used and the wiring board is integrally molded with the pins and the heat sink using a mold. It is possible to reduce the thickness and cost of a pin grid array, and to manufacture a highly reliable pin grid array with high dimensional accuracy of about 50 μm. In addition, since the sealing part and the heat sink are integrated with the wiring board, it is possible to manufacture pin grid arrays with excellent bending strength, mechanical shock resistance, and thermal shock resistance, as well as excellent heat dissipation properties. You can get the same effect.
第１図は本発明に係るピングリツドアレイの断
面図、第２図は本発明に係るピングリツドアレイ
の製造に使用する配線基板の平面図、第３図はそ
の製造過程における封入成形時の金型の断面説明
図、第４図は本発明の他の実施例を示すピングリ
ツドアレイの部分断面図、第５図は本発明の他の
実施例を示すピングリツドアレイの底面図であ
る。
１…配線基板、２…段付きピン、３…放熱板、
４…耐熱性樹脂、５…開口部、６…配線パター
ン、７…貫通孔、１０…突起。
FIG. 1 is a cross-sectional view of a pin grid array according to the present invention, FIG. 2 is a plan view of a wiring board used in manufacturing the pin grid array according to the present invention, and FIG. 3 is a view during encapsulation molding in the manufacturing process. FIG. 4 is a partial sectional view of a pingrid array showing another embodiment of the present invention, and FIG. 5 is a bottom view of a pingrid array showing another embodiment of the present invention. It is. 1... Wiring board, 2... Stepped pin, 3... Heat sink,
4...Heat-resistant resin, 5...Opening, 6...Wiring pattern, 7...Through hole, 10...Protrusion.
Claims (1)
ムの表面に配線パターンを形成してなる配線基板
と、該配線基板に立設され前記配線パターンに接
続された複数のピンと、前記配線基板の開口部を
覆うように配線基板上に配置された金属製放熱板
の周縁部とを耐熱性樹脂で封止して一体化してな
ることを特徴とするピングリツドアレイ。1. A wiring board formed by forming a wiring pattern on the surface of a plastic base film having an opening, a plurality of pins erected on the wiring board and connected to the wiring pattern, and a wiring board so as to cover the opening of the wiring board. A pin grid array is characterized in that the peripheral edge of a metal heat sink placed on a wiring board is sealed and integrated with a heat-resistant resin.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18090185A JPS6240749A (en) | 1985-08-16 | 1985-08-16 | Pin grid array |
| EP86108770A EP0218796B1 (en) | 1985-08-16 | 1986-06-27 | Semiconductor device comprising a plug-in-type package |
| DE8686108770T DE3675321D1 (en) | 1985-08-16 | 1986-06-27 | SEMICONDUCTOR ARRANGEMENT WITH PACK OF PIN PLUG TYPE. |
| US06/880,832 US4823234A (en) | 1985-08-16 | 1986-07-01 | Semiconductor device and its manufacture |
| KR1019860006161A KR870002647A (en) | 1985-08-16 | 1986-07-28 | Semiconductor device and manufacturing method |
| CN198686105249A CN86105249A (en) | 1985-08-16 | 1986-08-16 | Semiconductor device and manufacturing thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18090185A JPS6240749A (en) | 1985-08-16 | 1985-08-16 | Pin grid array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6240749A JPS6240749A (en) | 1987-02-21 |
| JPH0533535B2 true JPH0533535B2 (en) | 1993-05-19 |
Family
ID=16091288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18090185A Granted JPS6240749A (en) | 1985-08-16 | 1985-08-16 | Pin grid array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6240749A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62189743A (en) * | 1986-02-14 | 1987-08-19 | Matsushita Electric Works Ltd | Wiring circuit unit |
| JPS62189742A (en) * | 1986-02-14 | 1987-08-19 | Matsushita Electric Works Ltd | Pin grid array |
| JP2770947B2 (en) * | 1988-02-05 | 1998-07-02 | シチズン時計株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
-
1985
- 1985-08-16 JP JP18090185A patent/JPS6240749A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6240749A (en) | 1987-02-21 |
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