JPH05328353A - Descrambling device - Google Patents

Abstract

PURPOSE:To execute descrambling without generating malfunction even when the superposed position of a scrambling discrimination signal(SDS) or the like is changed in a descrambling device for descrambling a video signal obtained by compressing and scrambling a synchronizing signal. CONSTITUTION:A microprocessor 13 previously receives the superposing position information of a scrambling discrimination signal or the like from a CATV center and sets up the information in a vertical descrambling timing offset circuit 12. The circuit 12 applies the set data to the initial value of a counter in a vertical descrambling timing signal generating circuit 9 as offset data. Thereby even when the superposed position of the scrambling discrimination signal is changed, a scrambled video signal can be descrambled without generating malfunction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a descrambling device used for a terminal of a CATV system.

[0002]

2. Description of the Related Art In recent years, in general terrestrial television broadcasting, since the number of channels is limited by the width of the broadcasting band, it is difficult to meet the recent diversification of viewer needs. The number of viewers who subscribe to the CATV system is increasing.

The current CATV system is an urban CAT
The number of users is increasing mainly in the V system. In this urban CATV system, pay services are provided only to specific contractors. The paid service has confidentiality, so the video signal is scrambled. That is, the image information of the pay service is processed by a specific means so that the image cannot be reproduced only by the ordinary television receiver. To reproduce this scrambled signal, descramble processing is performed based on the key signal sent together with the scrambled signal.

First, an outline of scrambling and descrambling by band compression will be described. For example, in FIG.
Is a scramble signal and is compressed to a certain level for a certain period including the horizontal synchronization period. In this case, even if an attempt is made to reproduce the screen on the television receiver as it is, horizontal synchronization is not applied and a so-called horizontal screen is displayed. FIG. 3B shows a timing signal for descrambling the scrambled signal to return it to the original television signal. The scrambled signal shown in FIG. 3A is changed by a predetermined level only during this H level period. (C) is a signal in which this scrambled signal is descrambled based on the descramble timing signal. With this signal, it is possible to reproduce the screen on a normal television receiver.

Next, an example of a scramble signal and a descrambler by amplitude compression of the conventional horizontal and vertical synchronizing signals will be described with reference to FIGS. 4 and 5. FIG. 4 is a block diagram showing the configuration of a conventional descrambling device. In the figure, the scrambled video signal is supplied to a scramble identification signal extracting circuit 1. The scramble identification signal extracting circuit 1 is superimposed in the vertical blanking period.
The scramble identification signal f of (a) is identified and the signal is extracted. The scramble identification signal f is, for example, 2
It is assumed that the frequency of the sine wave in the video band of MHZ is superimposed on the scrambled signal of 20 mS, for example. The scramble identification signal extracting circuit 1 is composed of a bandpass filter and a waveform shaping circuit which pass this frequency. The output of the scramble identification signal extracting circuit 1 is given to the scramble identification signal detecting circuit 2. The scramble identification signal detection circuit 2 is composed of a counter or the like for determining the time width thereof in order to distinguish the extracted identification signal from noise.

The detection signal from the scramble identification signal detection circuit 2 is given to the sampling timing generation circuit 3. The sampling timing generation circuit 3 generates a synchronization pattern g shown by using this detection signal as a trigger, a synchronization pattern sampling timing signal i for sampling the key data h, and a timing signal j for sampling the key data. Etc. The timing signals i and j are given to the sync pattern extracting circuit 4 and the key data extracting circuit 5, respectively.
The synchronization pattern extracting circuit 4 and the key data extracting circuit 5 are connected to the input terminals and are composed of a gate circuit for extracting the input scramble signal based on the timing signals i and j. The sync pattern signal and the key data signal are supplied to the scramble signal determination circuit 6 and the key data decoding circuit 7. Here, the blocks from the scramble identification signal extraction circuit 1 to the key data extraction circuit 5 constitute a synchronization pattern / key data extraction means for extracting the synchronization pattern and the key data based on the scramble identification signal which is a trigger for descrambling start. There is.

The scramble signal judging circuit 6 checks the bit pattern of the extracted sync pattern signal to judge whether it is a regular scramble signal, and is composed of a shift register, a comparator and the like. This determination signal is given to the horizontal descrambling timing signal generating circuit 8 and the vertical descrambling timing signal generating circuit 9. The horizontal descramble timing signal generation circuit 8 generates a horizontal descramble timing signal by using the descramble start signal as a trigger, and is composed of a horizontal synchronization timing counter and the like.
Further, the vertical descramble timing signal generation circuit 9 uses the descramble start signal output from the scramble signal determination circuit 6 as a trigger, and uses the horizontal descramble timing signal output from the horizontal descramble timing signal generation circuit 8 as a clock for vertical descrambling. It generates a timing signal and is composed of a vertical synchronization timing counter or the like. The vertical synchronization timing counter starts counting from a predetermined value determined in advance according to the scramble identification signal, the synchronization pattern, and the superposition position of the key data.

On the other hand, the key data decoding circuit 7 decodes the key data extracted by the key data extracting circuit 5, and its output is given to the descramble level generating circuit 10. Descramble level generation circuit 10
Generates a scramble level of a scramble signal based on the decoded data, and is composed of a flip-flop circuit or the like. The outputs of the horizontal and vertical descramble timing signal generation circuits 8 and 9 and the descramble level generation circuit 10 are given to the descramble processing circuit 11. Descramble processing circuit 1
The descrambling signal 1 descrambles the scrambled signal according to the timing signal and the descramble level signal, and is composed of an amplifier circuit and the like.

Next, the operation of this conventional example will be described.
First, as shown in FIG. 5A, when the scrambled signal is input to the descrambler, the scrambled identification signal extracting circuit 1 first extracts the identification signal f and shapes the waveform. FIG. 5B shows a scramble identification signal extracting circuit 1
Shows the output of. When the scramble identification signal detection circuit 2 detects the scramble identification signal, the extraction timing generation circuit 3 outputs a synchronization pattern and a key data extraction timing signal as shown in FIG. 5C. Therefore, the synchronization pattern g and the key data h are shown in FIG.
As shown in (d) and (e), they are extracted respectively. Here, the synchronization pattern is, for example, a specific bit pattern of 8 bits (“10101001” in the example of FIG. 5). By checking this signal, it is confirmed whether or not it is a descramble signal, and shown in FIG. Start a counter to generate the descramble timing signal. In this way, the horizontal and vertical descramble timing signal generation circuits 8 and 9 are activated, and the timing signal is sent to the descramble processing circuit 11. Further, the key data is decoded based on the key data h shown in FIG. 5E, and the descramble level generation circuit 10 gives the descramble level to the descramble processing circuit 11. The scrambled signal is descrambled based on these signals and output from the output terminal.

[0010]

However, in such a conventional descrambler, a signal such as a character multiplex broadcast is superimposed at the same horizontal scanning line timing as that of the scramble identification signal of the scramble signal and the superimposing device of the synchronization pattern signal. If so, it is necessary to change the superposition position of the scramble identification signal and the synchronization pattern signal in order to avoid it. However, when the superposition position is changed, the initial value of the counter of the vertical descrambling timing circuit is deviated, so that the vertical descrambling timing signal deviates from the normal timing, and there is a drawback that normal descrambling processing cannot be performed.

The present invention has been made in view of the above conventional problems, and enables normal descrambling processing even when the superimposing positions of the scramble identification signal and the synchronization pattern signal are changed. This is a technical issue.

[0012]

SUMMARY OF THE INVENTION The present invention is a descrambling device for descrambling a scrambled CATV scrambled signal by compressing or level-shifting horizontal and vertical synchronizing signals with respect to a video signal. A synchronization pattern / key data extraction means for extracting a synchronization pattern and key data based on a scramble identification signal which is a trigger for descrambling start and which is superimposed in the period, and a desynchronization based on a bit pattern of the extracted synchronization pattern signal. A scramble signal determination circuit that generates a scramble start timing signal, a horizontal descramble timing signal generation circuit that generates a horizontal descramble timing signal that descrambles the horizontal synchronization signal based on the descramble start timing signal, and a horizontal descramble A vertical descramble timing signal generation circuit that counts the horizontal descramble timing signal obtained from the imming signal generation circuit and generates a vertical descramble timing signal that descrambles the vertical synchronization signal, and a descramble start timing signal from the scramble signal determination circuit. At the time of occurrence, the vertical descrambling timing offset circuit, which sets a preset offset value in the vertical descramble timing signal generating circuit, communicates with the CATV center to obtain the superimposed position information of the scramble identification signal and the synchronization pattern signal. A microprocessor for setting in the vertical descrambling timing offset circuit based on this, and a scramble signal by decoding the key data extracted by the synchronization pattern / key data extraction means. A descramble level generating means for generating a descramble level corresponding to the compression level, and a descramble processing circuit for descramble the scramble signal based on the horizontal and vertical descramble timing signals and the descramble level signal of the descramble level generating means. , Are provided.

[0013]

According to the present invention having such a feature, when the data signal of the character multiplex broadcasting or the like is superposed within the vertical blanking period, the microcomputer is previously set to CA.
The scramble identification signal and the sync pattern superposition position signal are received from the TV center and set in the vertical descrambling timing offset circuit. In this way, the vertical descramble timing signal generation circuit starts counting from this value each time the descramble start timing signal is applied, and generates the vertical descramble timing signal. Therefore, since the preset data changes in response to the change of the superposition position of the scramble identification signal and the synchronization pattern signal, the descrambling can be performed normally.

[0014]

1 is a block diagram showing the overall configuration of a descramble circuit according to an embodiment of the present invention. In this figure, the same parts as those in the conventional example described above are designated by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, a vertical descrambling timing offset circuit 12 is connected to the vertical descrambling timing signal generating circuit 9. The vertical descrambling timing offset circuit 12 sets a plurality of pieces of position information for the superposition position within the vertical blanking period, and when the descrambling start timing signal is generated, the counter corresponding to the superposition position of the scramble identification signal and the synchronization pattern is set. The preset value is set. The offset circuit 12 is composed of, for example, a flip-flop or a register that holds data of about 10 bits. The microprocessor 13 is also configured to perform data communication with the CATV center. On the CATV center side, when data such as character multiplex broadcasting is superimposed, the position is checked and the scramble identification signal f, the synchronization pattern signal g, and the key data h are superimposed so as not to be superimposed at the same position. At that time, the CATV center sends the superposition position information of the scramble identification signal f and the synchronization pattern signal g to the microprocessor 13. The microprocessor 13 receives this signal,
The offset data is set in the vertical descramble timing offset circuit 12.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. FIG. 2A shows a scrambled video signal in which vertical and horizontal synchronizing signals applied to the input terminal are band-compressed and level-shifted. In this figure, the scramble identification signal f, the synchronization pattern signal g, and the key data h are superimposed on the specific horizontal scanning line position in the vertical blanking period, and the character multiplex signal k is added.
Shows a state in which is superimposed. When this signal is applied to the input terminal, the scramble identification signal extracting circuit 1 extracts the scramble identification signal f, as described above, and generates a synchronization pattern and key data extraction timing signal. If it is determined that the signal is a scramble signal, horizontal and vertical descramble timing signals are generated. FIG. 2B shows this horizontal descramble timing signal, and the vertical descramble timing signal generation circuit 9 counts this signal.

When the character multiplex broadcast signal k is superposed during the vertical blanking period and the scramble identification signal or the like is superposed so as not to be superposed on this, the CATV center superimposes it on the microprocessor 13. Position data is obtained. In FIG. 2A, character multiplex broadcasting k
Is at the position of the count value “13” in FIG. 2E, and in order to avoid it, the scramble identification signal f and the synchronization pattern g
Is the count value "11" and the key data h is the count value "1"
2 "is superimposed. In this case, the microprocessor 13 receives the superposition position information "11" of the scramble identification signal f and the synchronization pattern signal g from the CATV center. However, the counter of the vertical descrambling timing signal generation circuit 9 is initialized after the scramble signal determination circuit 6 determines the scramble identification signal f and the synchronization pattern signal g, so that the microprocessor 13 is next to the superposition position information "11". The value “12” is set in the vertical descrambling timing offset circuit 12. In the offset circuit 12, the counter starts counting with this signal as an offset signal for each frame. Therefore, the vertical descramble timing signal generation circuit 12 is generated by the descrambling start signal output from the scramble signal determination circuit 6.
To initialize. Therefore, the counter after descrambling starts counting as shown in FIG. 2E, and the vertical descrambling timing signal as shown in FIG. 2C can be generated with a predetermined count value. The descramble processing circuit 11 performs the descramble processing on the basis of the horizontal and vertical descramble timing signals thus obtained and the descramble level of the descramble level generation circuit 10, whereby the descramble can be normally performed.

[0017]

As described in detail above, according to the present invention, a data signal of a character multiplex broadcast or the like is superimposed, and a superimposing position of a scramble identification signal or a sync pattern signal serving as a descramble key signal is avoided so as to avoid this. Changes.
Regardless of this position change, by offsetting the position information in the vertical descrambling timing offset circuit in advance, it is possible to perform the descrambling process without malfunction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a descrambling device according to an embodiment of the present invention.

FIG. 2 is a time chart showing a descrambling state during a vertical blanking period.

FIG. 3 is a timing diagram showing an operation of a descrambling process.

FIG. 4 is a block diagram showing an example of a conventional descramble circuit.

FIG. 5 is a time chart showing a scramble identification signal f, a synchronization pattern signal g, key data h and data extraction timings thereof, which are superimposed on a plurality of horizontal scanning lines during a vertical blanking period.

[Explanation of symbols]

 1 scramble identification signal sampling circuit 2 scramble identification signal detection circuit 3 sampling timing generation circuit 4 synchronization pattern sampling circuit 5 key data sampling circuit 6 scramble signal determination circuit 7 key data decoding circuit 8 horizontal descrambling timing signal generation circuit 9 vertical descrambling timing Signal generation circuit 10 Descramble level generation circuit 11 Descramble processing circuit 12 Vertical descrambling timing offset circuit 13 Microprocessor

Claims (1)

[Claims] 1. A descrambling device for descrambling a scrambled CATV scrambled signal by compressing or level shifting horizontal and vertical synchronizing signals with respect to a video signal, which is superimposed within a vertical blanking period. A sync pattern / key data extraction means for extracting a sync pattern and key data based on a scramble identification signal which is a trigger for descrambling start, and a descramble start timing signal based on a bit pattern of the extracted sync pattern signal. A scramble signal determining circuit, a horizontal descramble timing signal generating circuit for generating a horizontal descramble timing signal for descramble a horizontal synchronizing signal based on the descramble start timing signal, and the horizontal descramble timing A vertical descramble timing signal generating circuit that counts the horizontal descramble timing signal obtained from the signal generating circuit and generates a vertical descramble timing signal that descrambles the vertical synchronizing signal, and a descramble start timing signal from the scramble signal determining circuit. At the time of occurrence, communication is performed between the CATV center and the vertical descramble timing offset circuit that sets a preset offset value in the vertical descramble timing signal generation circuit, and the superposition position information of the scramble identification signal and the sync pattern signal is transmitted. A microprocessor for setting the vertical descrambling timing offset circuit based on the above, and a scrambler for decoding the key data extracted by the synchronization pattern / key data extraction means. Descramble level generating means for generating a descramble level corresponding to the compression level of the bull signal, and descrambles the scramble signal based on the horizontal and vertical descramble timing signals and the descramble level signal of the descramble level generating means. And a descramble processing circuit.