JPH05328292A - Image recorder - Google Patents

Abstract

PURPOSE:To facilitate consecutive recording and editing in the variable length coded recording. CONSTITUTION:Image information of M-frames is coded in variable length so as to be recorded on N tracks of a magnetic tape and the result is recorded on the magnetic tape. Control signals *a, *b representing the starting position of N tracks are recorded on an linear track of the magnetic tape. When frames #1b-#4b are consecutively recorded after a frame #3a, the control formation representing the effective final frame #3a in the N tracks is recorded the control signal *a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus for variable length coding image information and recording it on a recording medium.

[0002]

2. Description of the Related Art In recent years, a variable length coding system capable of achieving a high compression rate has been attracting attention as a compression system of image data. For example, since high-definition, which is one of the standards for the next-generation high-definition image signal, has five times as much information as the NTSC system, the variable-length coding system is more efficient for recording (or transmitting) the image information. Need to be compressed.

[0003]

However, the image information compressed by the variable length coding does not have a constant data amount per field (or frame). For example, when applied to a digital VTR that records image information on a magnetic tape by the helical scan method, it becomes difficult to record data of one screen in the same track. as a result,
There is a problem that it is difficult to realize joint shooting (recording), editing, special playback, etc.

It is an object of the present invention to present an image recording apparatus which eliminates such inconvenience.

[0005]

In the image recording apparatus according to the present invention, image information of an M (≧ 2) screen is transferred to N (≧≧ 2) of a recording medium.
2) It has a variable length coding means for performing variable length coding so that it can be recorded on a track, and records a control signal indicating the start of N tracks on the recording medium.

[0006]

By the above means, the encoded data of the image information is
It is guaranteed to be located at the beginning of the track in units of N tracks. Therefore, special reproduction and editing are facilitated. Further, since the recording in N-track units can be discriminated by the control signal, special reproduction and editing can be further facilitated, and the control information can be used for splicing and editing on any screen without breaking recording in N-track units. Will be able to do.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention. In this embodiment, M (M is an integer of 2 or more)
Image data of frame (or field) is N (N is 1
(N above integer) tracks are recorded, and joint shooting is performed in units of these N tracks. For editing and special reproduction, these N tracks are also set as an execution unit.

In FIG. 1, 10 is an input terminal for an image signal to be recorded, 12 is an A / D converter for converting the image signal from the input terminal 10 into a digital signal, and 14 is an A / D converter.
A variable-length coding circuit that performs variable-length coding of the M frame image data from the D converter 12 and compresses it into Am (Mbits) less than or equal to the recording capacity An (Mbits) of N tracks of the magnetic tape 28, which will be described later. Is a variable length coding circuit 1
An error correction code addition circuit for adding an error correction code to the output of 4, a synchronization / ID addition for forming an output of the error detection code addition circuit 16 into a synchronization block and adding a synchronization code Sync for synchronization detection and identification information ID Circuit. I
D includes an address of image information and a compression parameter (compression ratio etc.).

Reference numeral 20 is a modulation circuit for performing low-frequency suppression modulation such as 8-10 conversion or 8-14 conversion on the output of the Sync / ID addition circuit 18, 22 is a recording amplifier for amplifying the output of the modulation circuit 20, and 24 is recording. A switch connected to the a-contact in the mode and a b-contact in the reproduction mode, 26 is a recording / reproducing magnetic head, and 28 is a magnetic tape as a recording medium.

Reference numeral 30 is a reproduction amplifier, 32 is a demodulation circuit corresponding to the modulation circuit 20, 34 is a Sync / ID detection circuit circuit for detecting the synchronization code Sync and the identification information ID, and 36.
Is an error correction circuit for correcting the data portion supplied from the Sync / ID detection circuit 34 with an error correction code,
Reference numeral 38 denotes a variable length code decoding circuit which decodes the variable length coded image data error-corrected by the error correction circuit 36,
Reference numeral 40 denotes a frame memory having a storage capacity for M frames, which stores the image data restored by the variable-length code decoding circuit 38, and 42 converts the image data read from the frame memory 40 into an analog signal. The D / A converter 44 is an output terminal for outputting the analog reproduced image signal output from the D / A converter 42 to the outside.

Reference numeral 45 is an operating device for editing operation, 46 is a control circuit for controlling editing such as joint photographing according to a signal from the operating device 45, and 47 is a control circuit 46 which requires data (such as position data for joint photographing). Is a memory for storing. Details of the operation of the control circuit 46 will be described later.

FIG. 2 shows an example of the variable length coding circuit 14, which is a circuit block diagram of a combination of discrete cosine transform (DCT) and variable length coding.

In FIG. 2, reference numeral 50 denotes an input terminal to which the image data from the A / D converter 12 is input, and 52 denotes a block for dividing the raster scan image data from the input terminal 50 into a block of i × j pixels. A block circuit 54 is a DCT circuit for converting the output of the block circuit 52 of the block circuit 52 into the frequency domain by discrete cosine transform.

56a, 56b, 56c and 56d are DCTs
A delay circuit for delaying the output of the circuit 54 for M frame periods,
Reference numerals 58a, 58b, 58c, 58d and 58e denote outputs of the DCT circuit 54 and delay circuits 56a, 56b, 56c and 56.
A quantizing circuit for quantizing the output of each d, 60 is a quantizing matrix generating circuit for generating the element value Xij which is the basis of the quantizing coefficient of the quantizing circuits 58a, 58b, 58c, 58d and 58e. 66 is a quantization circuit 58a,
58b, 58c, 58d, 58e is an initial coefficient generation circuit for generating an initial value S0 of a parameter that determines the quantization characteristic.

68a is a quantization matrix generating circuit 60.
Is a multiplier that multiplies the output Xij of the above by the coefficient S0 output from the initial coefficient generation circuit 66, and the multiplication result is applied to the quantization circuit 58a. Reference numeral 70a denotes a variable length coding circuit that performs variable length coding on the output of the quantization circuit 58a and outputs the information amount Ba of the variable length code. Reference numeral 72a denotes an initial coefficient S0 from the initial coefficient generation circuit 66 and the variable length coding circuit 70a.
Is a coefficient calculation circuit that determines a coefficient S1 that provides a predetermined information amount after variable-length coding from the information amount Ba from

Thereafter, similarly, 68b, 68c, 68d,
68e is an output Xij of the quantization matrix generation circuit 60.
, Multipliers 70b, 70c, 70d for multiplying the coefficients S1, S2, S3, S4 output from the coefficient operation circuits 72a, 72b, 72c, 72d, and the quantization circuits 58b, 5
8c and 58d outputs are variable length coded, and the information amount B is
variable-length coding circuit for outputting b, Bc, bd, 70e
Is a variable length coding circuit for variable length coding the output of the quantizing circuit 58e and outputting a variable length code, 72b, 72c, 7
2d is a coefficient calculation circuit 72a, 72b, 72c, respectively.
From coefficients S1, S2 and S3, and the variable length coding circuit 70
Based on the information amounts Bb, Bc, Bd from b, 70c, 70d, the coefficients S2, S3, S4 such that a predetermined compression ratio or more is obtained.
Is a coefficient calculation circuit for calculating

Reference numeral 74 is a buffer for rate-adjusting the output of the variable length coding circuit 70e, and reference numeral 76 is a coefficient calculation circuit 72d.
Of the variable S and the variable length code from the buffer 74, and 78 is an output terminal connected to the error correction code addition circuit 16 of FIG.

The circuit shown in FIG. 2 outputs variable-length coded data having a minimum compression rate capable of recording M frame image data on N tracks. First, the operation of FIG. 2 will be described.

In the circuit shown in FIG. 2, the quantizer circuits 58a, 58b, which are connected in multiple stages, are arranged so that the data amount Am after compression of M frames is smaller than the recording capacity An of N tracks and is as close as possible to An. 58c, 58d, 58
Coefficients S0, S1, S2, S for controlling the quantization characteristic of e
3 and S4 are sequentially changed to output the variable length code having the lowest compression rate.

First, the operation of the circuit shown in FIG. 2 will be described.
The blocking circuit 52 includes an input terminal 50 (A / D converter 1
The raster scanning image data from 2) is converted into a block column of i × j pixels, and the DCT circuit 54 causes the blocking circuit 5
The blocked image data from 2 is converted into the frequency domain by the discrete cosine transform, and the transform coefficient is output. The initial coefficient setting circuit 66 generates an initial coefficient S0 corresponding to a general compression rate suitable for recording M frame compressed image data on N tracks, and outputs the initial coefficient S0 to the multiplier 68a and the coefficient calculation circuit 7.
2a.

The multiplication circuit 68a multiplies the quantized coefficient Xij generated by the quantized matrix generation circuit 60 by the initial coefficient S0, and the quantized circuit 58a has a quantized characteristic corresponding to Xij × S0, and outputs from the DCT circuit 54. Is quantized. If S0 is large, the amount of information after compression is small, and if S0 is small, the amount of information after compression is large, and vice versa. The variable length coding circuit 70a performs variable length coding on the output of the quantization circuit 58a, and outputs the information amount Ba after variable length coding to the coefficient calculation circuit 72a.

The coefficient calculation circuit 72a calculates the information amount B from the initial coefficient S0 from the initial coefficient generation circuit 66 and the information amount Ba.
If a is greater than the target value, coefficient S1 with a value greater than S0
Is generated, and conversely, if the information amount Ba is less than the target value,
A coefficient S1 having a value smaller than S0 is generated, and the multiplication circuit 68b is generated.
And the coefficient calculation circuit 72b.

The delay circuit 56a delays the output of the DCT circuit 54 for M frame periods and supplies it to the delay circuit 56b and the quantization circuit 58b. The delay time by the delay circuit 56a may be equal to or longer than the processing time in the quantization circuit 58a, the variable length coding circuit 70a, and the coefficient calculation circuit 72a.

The multiplication circuit 68b converts the quantization coefficient Xij generated by the quantization matrix generation circuit 60 into the coefficient calculation circuit 72.
The coefficient S1 from a is multiplied, and the quantization circuit 58b outputs Xi
The output of the delay circuit 56a (the output of the DCT circuit 54) is quantized with the quantization characteristic according to j × S1. Again, S
If 1 is large, the amount of information after compression is small, and if S1 is small, the amount of information after compression is large. The variable length coding circuit 70b performs variable length coding on the output of the quantization circuit 58b and outputs the coded information amount Bb to the coefficient calculation circuit 72b.

The coefficient calculation circuit 72b is a coefficient calculation circuit 72b.
From the coefficient S1 from a and the information amount Bb, if the information amount Bb is larger than the target value, a coefficient S2 having a value larger than S1 is generated, and conversely, if the information amount Bb is smaller than the target value, a value smaller than S1. The coefficient S2 is generated and supplied to the multiplication circuit 68c and the coefficient calculation circuit 72c.

In the same manner, the quantization and the variable length coding by the coefficients S2 and S3 are tried in the same manner, and finally, the coefficient calculation circuit 72d can compress the image data of M frames in N tracks. The quantization circuit 58e quantizes the transform coefficient of the DCT circuit 54 with the quantization table of Xij × S4, and the variable length coding circuit 70e outputs the variable length code to the output of the quantization circuit 58e. Turn into.

The code output of the variable length coding circuit 70e is supplied to the buffer 74. The buffer 74 performs rate adjustment with a predetermined recording rate, inserts dummy data in the empty data portion, and outputs it to the multiplexing circuit 76. The coefficient S4 output from the coefficient calculation circuit 72d is also applied to the multiplexing circuit 76, and the multiplexing circuit 76 multiplexes these and outputs them to the output terminal 78, that is, the error correction code adding circuit 16
(Fig. 1).

In this way, the variable length coding circuit 14
Performs high-efficiency encoding of the image data from the A / D converter 12 in units of M frames. The error correction code addition circuit 16 adds an error correction code based on, for example, a double-coded Reed-Solomon code to the output of the circuit 14. Sync
The ID adding circuit 18 synchronizes the output of the error correction code adding circuit 16 into a synchronization block, and outputs a synchronization code Sync for synchronization detection.
Also, the identification information ID including an address and a compression parameter is added and output to the modulation circuit 20. Modulation circuit 20
Outputs low-frequency suppression modulation of the circuit 18, and the output is applied to the magnetic head 26 via the recording amplifier 22 and the switch 24 and recorded on the magnetic tape 28.

FIG. 4 shows an example of the track pattern when M = 4 and N = 6. The magnetic tape 28 has a linear track extending in its longitudinal direction, and a mark * indicating the head position of every N tracks is simultaneously recorded on the linear track.

The compressed image data thus recorded on the magnetic tape 28 is reproduced by the magnetic head 26, and its output is applied to the demodulation circuit 32 through the switch 24 and the reproduction amplifier 30 and demodulated. The Sync / ID detection circuit 34 receives the synchronization code Sync from the output of the demodulation circuit 32.
The identification information ID, the variable length coded image data and its error correction code are detected by c, and the variable length coded image data and its error correction code are supplied to the error correction circuit 36. The error correction circuit 36 corrects the code error of the variable length coded image data according to the error correction code, and the variable length code decoding circuit 38 decodes the variable length coded image data and outputs the original digital image signal.

The digital image signal restored by the variable length code decoding circuit 38 is temporarily stored in the frame memory 40 for M frames, and if there is no unnecessary reproduced image to be described later, D / S read out in the writing order. It is supplied to the A converter 42. The D / A converter 42 converts the image data from the memory 40 into an analog signal. The reproduced image signal thus reproduced is output from the output terminal 44 to the outside.

Next, the joint photographing operation, which is a feature of this embodiment, will be described. FIG. 4 shows a recording track pattern before connection shot editing. The recording track pattern after assembly is shown. Before editing, the case where another image is connected after the frame # 3a in a state where the compressed image data of the frames # 1c to # 4c are recorded after the compressed image data of the frames # 1a to # 4a is described as an example. To do.

The magnetic tape shown in FIG. 4 is reproduced, and while the recorded image is displayed on the monitor, the frame 3a to be shot continuously is designated by the operating device 45, and the recording switch of the operating device 45 is instructed to start recording. The control circuit 46 is
The end frame # 3a of the joint shot specified by the user is stored, and the magnetic tape is rewound to the beginning position * a of the N track where the frame # 3a is recorded.
Control signal on the linear track by the additional circuit 18 *
After "a", the end frame # 3a information for joint shooting is recorded.

After that, the next N tracks are fast-forwarded to the head position * c, and thereafter, the image signals input to the input terminal 10 are sequentially recorded. The edited track pattern is shown in FIG. Image frames # 1b to # 4b are recorded instead of the image frames # 1c to # 4c. Image frame # 1
The control signal indicating the head position of the N track on which b to # 4b are recorded is also rewritten. When the control signal includes the ID, the contents are naturally image frames # 1b to # 4.
It has been rewritten to correspond to b.

A control signal indicating the beginning of N tracks,
The information of the end frame of the continuous shooting may be the front end or the end of each track instead of the above linear track. Further, the Sync ID adding circuit 18 and the S
Of course, recording and detection may be performed by a circuit other than the ync / ID detection circuit 34.

As described above, when reproducing the magnetic tape after the spliced shot editing, when the Sync / ID detection circuit 34 detects the information of the spliced shot end frame on the linear track, the information is transferred to the control circuit 46. To do. The control circuit 46 temporarily stores the information of the end frame for joint shooting in the memory 47, and monitors and controls the frame memory 40. That is, after the reproduced image data of the joint shooting end frame stored in the memory 47 is written in the frame memory 40, the reproduced image data up to the next control signal indicating the beginning of the N frame is written in the frame memory 40. Try not to. In FIG. 5, the reproduced image data of the frame # 4a is prevented from being written in the frame memory 40.

Of course, all the reproduced image data output from the variable-length code decoding circuit 38 is once written in the frame memory 40, and at the time of reading, it is jointly shot after the reproduced image data of the joint shot end frame. It goes without saying that the reproduction image data of the frame # 1b and subsequent frames may be controlled to be read out. In FIG. 5, when reading from the frame memory 40, frame # 4
The reproduced image data of a is skipped.

In the circuit shown in FIG. 2, the quantizing circuits 58a ...
58e and the variable length coding circuits 70a to 70e are arranged and connected in multiple stages. In this circuit configuration, it is necessary to compress the output code of the variable length coding circuit 70e to an information amount equal to or less than the target information amount, Depending on the coefficient calculation of the coefficient calculation circuits 72a to 72d, it is necessary to set a coefficient at the stage of the coefficient calculation circuit 72d so that the compression ratio is considerably high. To prevent this, the coefficient calculation circuits 72a to 72d
Instead of the loop calculation by the microcomputer, the operation may be repeatedly performed so as to obtain the optimum amount of information. In this case, an image memory for storing the image data of one screen is required, but the quantization circuit and the variable length coding circuit need only be one stage.

Further, the quantizing circuits 58a to 58e and the variable length coding circuits 70a to 70e are arranged in parallel, and the plurality of coefficients S0 to S4 corresponding to the target information amount are used for the simultaneous quantization and variable length coding. Alternatively, the compression code having the closest information amount that is less than or equal to the target information amount may be selected.

That is, FIG. 2 is an example, and various configurations can be adopted as the circuit configuration of the variable length coding circuit 14 for realizing the embodiment of the present invention shown in FIG. 1, and the circuit example of FIG. 2 is limited. Not done. The compression ratio may be feedback-controlled by the amount of data in the buffer 76 in the circuit of FIG.

In the present embodiment, since M frames are always completed in N tracks, it is possible to relatively easily realize joint shooting, editing and special reproduction. Also, by reproducing N tracks, the situation that the reproduction data forming one screen becomes insufficient does not occur, and the underflow or overflow of the reproduction image display does not occur.

Although the example in which the magnetic tape is used as the recording medium has been described, the case where other recording medium such as a magnetic disk, an optical disk, a magneto-optical disk, and a solid-state memory is used is also included in the scope of the present invention. There is no end.

[0044]

As can be easily understood from the above description, according to the present invention, image information is recorded in units of N tracks, which facilitates processing for joint shooting, editing, special reproduction, and the like. Further, it is possible to prevent overflow or underflow on the display screen.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a circuit example of a variable length coding circuit 14.

FIG. 3 is an example of a recording track pattern of the present embodiment.

FIG. 4 is a recording track pattern before joint shooting.

FIG. 5 is a recording track pattern after joint shooting.

[Explanation of symbols]

10: Image input terminal 12: A / D converter 14: Variable length coding circuit 16: Error correction code addition circuit 18: S
sync / ID addition circuit 20: Modulation circuit 22: Recording amplifier 24: Switch 26: Recording / reproducing magnetic head
28: magnetic tape 30: reproduction amplifier 32: demodulation circuit 34: Sync
ID detection circuit circuit 36: error correction circuit 38: variable length code decoding circuit 40: frame memory 42: D /
A converter 44: Reproduced image output terminal 45: Operating device
46: Control circuit 47: Memory 50: Input terminal 52: Blocking circuit 54: DCT circuit 56a, 56b, 56c, 56d: Delay circuit 58a,
58b, 58c, 58d, 58e: Quantization circuit 60:
Quantization matrix generation circuit 66: initial coefficient generation circuit
68a, 68b, 68c, 68d, 68e: multiplier 7
0a, 70b, 70c, 70d, 70e: Variable length coding circuit 72a, 72b, 72c, 72d: Coefficient operation circuit 74: Buffer 76: Multiplexing circuit 78: Output terminal

Claims (3)

[Claims] 1. A variable-length coding unit for variable-length coding image information of an M (≧ 2) screen so that it can be recorded on N (≧ 2) tracks of a recording medium, and indicates the start of N tracks. An image recording apparatus characterized by recording a control signal on the recording medium. 2. The image recording apparatus according to claim 1, wherein control information indicating an effective screen among M screens recorded on N tracks is recorded on the recording medium. 3. The image recording apparatus according to claim 1, wherein control information indicating an invalid screen among M screens recorded on N tracks is recorded on the recording medium.