JPH05327506A - Non-overlap signal generating circuit - Google Patents

Abstract

PURPOSE:To prepare a non-overlap signal whose non-overlap period can be adjusted as necessary, and to attain a high speed and high precise A/D conversion by preparing each control signal by each clock signal from a clock generator. CONSTITUTION:D flip flops 21-23 store the level of an input terminal D when the level of a clock input terminal C rises, and outputs the level as output signals Q1-Q3 from an output terminal Q. The flop 21 clears the stored level each time the level of an input terminal CLEAR rises, and outputs a lower level output signal Q1 to an AND circuit 24 regardless of the level of the input terminals C and D. Then, a control signal phi1 is outputted from the output terminal, and a control signal phi2 is outputted from an AND circuit 25 through a delay circuit 26. A control signal phi3 is outputted from the flop 3 through the two delay circuits 26. Each circuit 26 outputs an input signal by delaying it by a time tau. The time tau is adjusted, and the non-overlap period is changed, so that the high speed and high precise A/D conversion can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-overlap signal generation circuit, and more particularly to a non-overlap signal generation circuit suitable for a two-step parallel A / D converter using a chopper type comparator.

In recent years, a two-step parallel A / D converter has been developed which can reduce the circuit scale without decreasing the conversion speed. A chopper comparator is generally used in the two-step parallel A / D converter. Therefore, A / D converter A /
In order to improve the D conversion accuracy, it is required to improve the accuracy of the non-overlap signal which is a control signal used in the chopper type comparator.

[0003]

2. Description of the Related Art FIG. 4 is a circuit diagram showing the operating principle of a two-step parallel A / D converter taking a 4-bit A / D converter as an example.

The high-potential-side reference voltage VrH and the low-potential-side reference voltage VrL are divided by 16 resistors R connected in series, all of which have the same resistance value. The resistance R is 4 in 1
Each block B1 to B4 is connected to the minus input terminal of each of the upper comparators 41 to 43. That is, the upper comparators 41 to 4
Reference voltages V1 to V3 are applied to the respective negative input terminals of No.3.

Further, the three connection points between the four resistors R in each of the blocks B1 to B4 are connected to the negative input terminals of the lower comparators 44 to 46 via the three switches S1 to S4, respectively. There is. That is, the reference voltages Va to Vc are applied to the negative input terminals of the lower comparators 44 to 46, respectively.

The input analog signal Vin is input to the positive input terminals of the comparators 41 to 46. Therefore, the upper comparators 41 to 43 respectively compare the reference voltages V1 to V3 with the input analog signal Vin,
When the reference voltages V1 to V3 are higher than the input analog signal Vin, a low level output signal is output, and when the input analog signal Vin is higher than the reference voltages V1 to V3, a high level output signal is output.

Each output signal (thermometer code) of the upper comparators 41 to 43 is input to the upper 2-bit encoder 47. Then, the input signal Vin is supplied to the reference voltages VrH to V1, V by the high-order 2-bit encoder 47.
It is determined which level area (1 to V2, V2 to V3, V3 to VrL) is in (hereinafter referred to as a large level area), encoded into a binary code and converted into digital output D3 to D2 of upper 2 bits. .. In addition, the upper 2 bits
The encoder 47 turns on one of the switches S1 to S4 corresponding to the level region of the input signal Vin.

Therefore, the reference voltages Va to Vc obtained by dividing the large level region of the input signal Vin into quarters are applied to the negative input terminals of the lower comparators 44 to 46 via the switches S1 to S4 which are turned on. .. Therefore, the lower comparators 44 to 46 compare the reference voltages Va to Vc with the input analog signal Vin, respectively, and if the reference voltages Va to Vc are larger than the input analog signal Vin, the low level and the input analog signal Vin are the reference. If it is higher than the voltages Va to Vc, a high level output signal is output.

The output signals of the lower comparators 44 to 46 are input to the lower 2-bit encoder 48. Then, the lower 2 bit encoder 48 causes the input signal V
It is determined where in is in a level area obtained by dividing the large level area into four, encoded, and converted into digital outputs D1 to D0 of the lower 2 bits.

As described above, the two-step parallel type A / D
In the converter, first, the high level area of the input analog signal is determined to obtain the high-order bit output, and then the low level area is determined by determining where in the level area the high level area is appropriately divided. You are getting a bit output. That is, the two-step parallel A / D converter obtains the same conversion accuracy as that of the flash A / D converter by roughly determining the level of the input analog signal and then further finely determining based on the rough determination. still,
In the case of 4 bits, the two-step parallel type uses six comparators 41 to 46 as described above, but the flash type requires fifteen comparators. Therefore, the two-step parallel type can significantly reduce the number of comparators as compared with the flash type.

By the way, the comparator is roughly classified into a differential type and a chopper type in terms of its configuration. The differential type comparator using the differential amplifier has a drawback that the structure is complicated and the accuracy cannot be increased due to the offset of the differential amplifier. Therefore, a chopper type comparator is usually used for the upper and lower comparators 41 to 46 of the 2-step parallel A / D converter.

FIG. 5 shows each chopper type comparator 41.
It is a circuit diagram which shows the internal circuit of-46. The upper comparators 41 to 43 are all chopper type comparators having the same configuration, and are composed of CMOS analog switches 51 to 53 formed of transmission gates, CMOS inverter circuits 54 and 55, and a capacitor K.

That is, the analog switches 51 and 52 are connected to the inverter circuit 54 via the capacitor K,
The inverter circuit 54 is connected in parallel with the analog switch 53, and the inverter circuits 54 and 55 are connected in series. The input analog signal Vin is applied to the analog switch 51, and the reference voltages V1 to V3 are applied to the analog switch 52, respectively.

The analog switches 51 to 53 are on / off controlled by control signals φ1, bars φ1, φ2, and bar φ2 output from the controller 56. That is, the analog switches 51 and 53 are controlled by the high-level control signal φ1.
(Low-level control signal bar φ1) turns on, and low-level control signal φ1 (High-level control signal bar φ1
1) Turn off by. Also, the analog switch 52
Is turned on by the high-level control signal φ2 (low-level control signal bar φ2), and the low-level control signal φ2
It is turned off by (high-level control signal bar φ2).

The controller 56 is a clock generator 57.
Each control signal φ1, bar φ1, φ2, bar φ2, φ3, and bar φ3 are generated based on the clock signal CL output from.

The high-order comparator 4 constructed in this way
The operations of 1 to 43 will be described by taking the upper comparator 41 as an example. In order to compare the input analog signal Vin and the reference voltage V1 by the upper comparator 41, first,
A high-level control signal φ 1 (low-level control signal bar φ 1) is input to each analog switch 51, 53 to turn it on, and a low-level control signal φ 2 (high-level control signal bar φ 2) is supplied to the analog switch 52. Enter and turn off.

Then, the input voltage Vin is applied to the electrode of the capacitor K on the analog switch 51 side. Further, since the input / output of the inverter circuit 54 is short-circuited, the input / output voltage converges on the threshold voltage VTH of the inverter circuit 54. Therefore, the potential of the electrode of the capacitor K on the side of the inverter circuit 54 becomes the threshold voltage VTH. Therefore, the capacitor K is charged by the difference voltage (Vin-VTH) between the input voltage Vin and the threshold voltage VTH, and the charge is accumulated. Incidentally, this period is called a reset period, and this operation is called a reset operation.

Next, a low level control signal φ 1 (high level control signal bar φ
1) is turned off by inputting the analog switch 5
A high level control signal φ 2 (low level control signal bar φ 2) is input to 2 and turned on.

Then, the reference voltage V1 is applied to the electrode of the capacitor K on the analog switch 52 side. Since the electric charge accumulated in the capacitor K is not discharged during the reset period, its electric quantity does not change. Therefore, the potential of the electrode on the side of the inverter circuit 54 of the capacitor K (the input voltage of the inverter circuit 54) is the input voltage Vin and the reference voltage V1.
Difference voltage (Vin-V1) from the threshold voltage VTH, resulting in (Vin-V1 + VTH).

Therefore, the inverter circuit 54 outputs a low level output signal when the input voltage Vin is higher than the reference voltage V1 and a high level output signal when the input voltage Vin is lower than the reference voltage V1. Note that this period is called a comparison period, and this operation is called a comparison operation.

Therefore, from the inverter circuit 55, when the input voltage Vin is higher than the reference voltage V1, the high level,
When the input voltage Vin is lower than the reference voltage V1, a low level output signal is output.

Since the lower comparators 44 to 46 have the same structure as the upper comparators 41 to 44, the same reference numerals will be suffixed with "A" and their description will be omitted. The operation of the lower comparators 44 to 46 is output from the control device 56 in the same manner as the analog switch 52 of the upper comparators 41 to 44 is on / off controlled by the control signal φ1 and the bar φ1 output from the control device 56. The analog switch 52A is on / off controlled by the control signal .phi.3 and the bar .phi.3, which are the same as the upper comparators 41 to 44, and the description thereof is omitted.

[0023]

By the way, the controller 5
6, control signal φ1 (bar φ1) and control signal φ2 (bar φ2), control signal φ1 (bar φ1) and control signal φ3 (bar φ3), control signal φ2 (bar φ2) and control signal φ3 (bar φ3), If there is an overlap between each of the
However, there is a problem in that the A / D conversion accuracy also decreases due to the decrease in the accuracy.

That is, when there is an overlap between the control signal φ1 (bar φ1) and the control signal φ2 (bar φ2),
During the overlap period, the upper comparators 41 to 41
The input voltage Vin and each of the reference voltages V1 to V3 are simultaneously applied to the electrode of the condenser K of the capacitor 43 on the analog switch 51 side. Therefore, the charge accumulated in the capacitor K changes, each operation of reset / comparison is not normally performed, and the accuracy of the upper comparators 41 to 43 decreases.

When there is an overlap between the control signal φ1 (bar φ1) and the control signal φ3 (bar φ3), the accuracy of the lower comparators 44 to 46 is reduced due to the same cause as in the case of the upper comparators 41 to 43. ..

When there is an overlap between the control signal φ2 (bar φ2) and the control signal φ3 (bar φ3), the upper comparators 41 to 43 and the lower comparators 44 to 46 operate simultaneously during the overlap. To do. Therefore, the lower comparators 44 to 46 operate before the upper 2-bit encoder 47 determines the large level area and turns on the switches S1 to S4.
The charges accumulated in the capacitor KA of No. 6 change, the reset / comparison operations are not normally performed, and the accuracy of the lower comparators 44 to 46 decreases.

Therefore, control signal φ1 (bar φ1) and control signal φ2 (bar φ2), control signal φ1 (bar φ1) and control signal φ3 (bar φ3), control signal φ2 (bar φ2) and control signal φ3 (bar φ
It is necessary to prevent the overlap between 3) and 3), that is, non-overlap.

Therefore, conventionally, by simply using a logic circuit,
As shown in FIG. 6, the control signals φ1 to φ3 (bars φ1 to φ3) are generated in synchronization with the rising of the clock signal CL of the clock generator 57, thereby achieving non-overlap. Therefore, each control signal φ1, φ2,
φ3 is high level (each control signal bar φ1, bar φ2, bar φ
The period of 3 (low level) and the non-overlap period are the same length.

Therefore, when the non-overlap period is minimized in order to speed up the A / D conversion, the control signals φ1 to φ3 are at the high level (the control signal bars φ1 to φ3 are at the low level). Similarly, the period becomes shorter, and the upper comparators 41 to 4 are reset during the reset period.
It becomes impossible to accumulate sufficient charges in the capacitor K of No. 3 and the capacitors K A of the lower comparators 44 to 46. Therefore, each comparator 41-46
Of the A / D conversion accuracy also decreases.

On the contrary, if the period during which the control signals φ1 to φ3 are at the high level (the control signal bars φ1 to φ3 are at the low level) is made sufficiently long in order to improve the accuracy of the comparators 41 to 46, the non-overrun occurs. Since the lap period also becomes long, it becomes impossible to perform high-speed A / D conversion.

The present invention has been made to solve the above problems, and its object is to provide a simple configuration capable of generating a non-overlap signal whose non-overlap period can be adjusted appropriately. To provide a non-overlap signal generating circuit.

[0032]

FIG. 1 illustrates the principle of the present invention. The frequency divider circuit 1 includes a plurality of flip-flop circuits F
It is constructed by connecting F1 to FFn in series. Then, the activation signal SL is input to the first-stage flip-flop circuit FF1, and in response to the activation signal, the output signal Q1 of the flip-flop circuit FF1 is changed to the next-stage flip-flop circuit F.
Output to F2. In addition, the first stage flip-flop circuit FF
The output signal Qn of the final stage flip-flop circuit FFn is input to 1 as a clear signal, and the level of the output signal Q1 is inverted and reset. The clock signal CL is input to the flip-flop circuits FF2 to FFn. Then, the flip-flop circuits FF1 to FFn output the output signals Q1 to Qn, which are obtained by dividing the frequency of the clock signal CL.

The signal generating circuit 2 includes flip-flop circuits FF2 to FFn except the first-stage flip-flop circuit FF1.
It is composed of logic circuits A1 to An-1 respectively provided for the above. Each logic circuit A1 to An-1 outputs the output signal Q2 of its corresponding flip-flop circuit FF2 to FFn.
To Qn and the flip-flop circuits FF1 to FFn-1 in the previous stage
Output signals Q1 to Qn-1 of the control signals φ1 to φn-1 which are inverted by the output signals Q2 to Qn, respectively, and control signals φ1 to φn-1 which are inverted by the output signals Q1 to Qn-1. Output to 3.

Different delay times are set in the respective delay circuits 3 and the final stage flip-flop circuit FFn.
The delay time is set to be longer on the side of the delay circuit 3 which inputs the control signal φn-1 corresponding to.

[0035]

Therefore, according to the present invention, the control signals .phi.1 to .phi.n-1 generated by the frequency dividing circuit 1 and the signal generating circuit 2 are generated.
Are appropriately delayed by the delay circuits 3 and do not overlap each other. In addition, since the delay time can be freely adjusted in each delay circuit 3, each control signal φ
The output time of 1 to φn-1 can be adjusted appropriately.

Then, each of the control signals φ1 to φn-1 is set to 2
It can be used as a suitable timing control signal for the reset operation and the comparison operation of the upper and lower chopper type comparators used in the step parallel type A / D converter.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A control device 20 according to an embodiment of the present invention will be described below with reference to FIGS.

In the present embodiment, the same components as those of the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 2, the first stage D flip-flop (da
The data input terminal D of the ta flip-flop) 21 is connected to the high potential side power source Vcc and is at a high level. The output terminal Q of the D flip-flop 21 is the D flip-flop 2
2 is connected to the data input terminal D, and the output terminal Q of the D flip-flop 22 is the final stage D flip-flop 2
3 is connected to the data input terminal D, and the output terminal Q of the D flip-flop 23 is connected to the clear input terminal CLEAR of the D flip-flop 21.

Each of the D flip-flops 21 to 23 stores the level of the D input terminal when the level of the clock input terminal C rises, and the stored levels are output from the output terminals Q to the output signals Q1 to Q1, respectively. Output as Q3. The D flip-flop 21 clears the stored level each time the level of the clear input terminal CLEAR rises, and the data input terminal D and the clock input terminal C
The low-level output signal Q1 is output regardless of the respective levels.

The H active input terminal of the AND circuit 24 is connected to the output terminal Q of the D flip-flop 21, and the L active input terminal of the AND circuit 24 is connected to the output terminal Q of the D flip-flop 22. The H active input terminal of the AND circuit 25 is connected to the output terminal Q of the D flip-flop 22, and the L active input terminal of the AND circuit 25 is connected to the output terminal Q of the D flip-flop 23.

The control signal φ1 is output from the output terminal of the AND circuit 24, and the control signal φ2 is output from the output terminal of the AND circuit 25 via the delay circuit 26.
Further, the control signal φ is output from the output terminal Q of the D flip-flop 23 via the two delay circuits 26 connected in series.
3 is output.

The clock generator 27 outputs the synchronized clock signals CL and SY. As shown in FIG. 3, every time the clock signal CL rises four times, the clock signal CL
SY stands up once. The clock signal SY is input to the clock input terminal C of the D flip-flop 21 via the three delay circuits 26 connected in series, and the clock signal CL is input to the D flip-flop 22,
It is input to each clock input terminal C of 23.

Each delay circuit 26 delays the input signal by time τ and outputs it. Next, the operation of the control device 20 configured as described above will be described with reference to FIG.
The output signals Q1 to Q3 are output in the following order.

1) When the clock signal SY rises, the level of the clock input terminal C of the D flip-flop 21 becomes 3
The delay circuits 26 start up with a delay of 3τ. Since the data input terminal D of the D flip-flop 21 is connected to the high potential side power source Vcc and is at high level, when the level of the clock input terminal C rises, it outputs the high level output signal Q1. Therefore, the output signal Q1
Rises after a delay of 3τ from the clock signal SY.

2) When the output signal Q1 is at a high level (the data input terminal D of the D flip-flop 22 is at a high level), the clock signal CL rises (the level of the clock input terminal C of the D flip-flop 22 rises). ), The output signal Q2 also rises.

3) When the clock signal CL rises (the level of the clock input terminal C of the D flip-flop 23 rises when the output signal Q2 is at the high level (the data input terminal D of the D flip-flop 23 is at the high level)). ), The output signal Q3 also rises.

4) When the output signal Q3 rises, the level of the clear input terminal CLEAR of the D flip-flop 21 also rises and the output signal Q1 falls. 5) Output signal Q1 is low level (D flip-flop 2
When the clock signal CL falls (when the level of the clock input terminal C of the D flip-flop 22 falls) while the data input terminal D of 2 is low level, the output signal Q2 also falls.

6) When the output signal Q2 is low level (the data input terminal D of the D flip-flop 23 is low level) and the clock signal CL falls (the level of the clock input terminal C of the D flip-flop 23 rises). Output signal Q3 also falls.

7) At the same time as the output signal Q3 falls, the clock signal SY rises. Hereinafter, the operation from 1) above is repeated. Therefore, the control signal φ1 rises after a delay of 3τ from the clock signal SY, and falls when the output signal Q2 rises. When the output signal Q2 rises, the control signal φ2 rises with a delay of time τ by the delay circuit 26,
When the output signal Q3 rises, the delay circuit 26 delays it with a delay of time τ. When the output signal Q3 rises, the control signal φ3 rises with a delay of 2τ by the two delay circuits 26, and when the output signal Q3 falls, it falls with a delay of 2τ by the two delay circuits 26. Next, the control signal φ1 rises after a lapse of time τ from the fall of the control signal φ3.

That is, a non-overlap period of time τ occurs between the control signals φ1 to φ3. As described above, the control device 20 controls the clock generation device 27.
The control signals φ1 to φ3 are generated based on the clock signals CL and SY output from
Non-overlap of ~ φ3 can be achieved.
The non-overlap period can be easily changed by adjusting the delay time τ of each delay circuit 26 by a known method. Therefore, the non-overlap period is set to the minimum necessary, and the A / D converter A shown in FIGS.
/ D conversion can be speeded up and each control signal φ1 to φ3
Is at a high level (each control signal bar φ1 to bar φ3 is at a low level) by sufficiently lengthening the period.
The accuracy of 6 can be improved. Therefore, high-speed and highly accurate A / D conversion can be performed.

The present invention is not limited to the above embodiment, and for example, the non-overlap period may be appropriately set by connecting an appropriate number of delay circuits 26 in series.

[0052]

As described above in detail, according to the present invention, a non-overlap signal generating circuit having a simple structure can generate a non-overlap signal whose non-overlap period can be adjusted appropriately. There is an excellent effect that can be.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram of an embodiment embodying the present invention.

FIG. 3 is a time chart of an example.

FIG. 4 is a circuit diagram of a 2-step parallel A / D converter.

FIG. 5 is a circuit diagram of a chopper type comparator which is a higher and lower comparator of a two-step parallel A / D converter.

FIG. 6 is a time chart of a control device of a conventional example.

[Explanation of symbols]

FF1 to FFn Flip-flop circuit FF1 First stage flip-flop circuit FFn Final stage flip-flop circuit Q1 to Qn Output signal of each flip-flop circuit FF1 to FFn Q1 First stage flip-flop circuit FF1 output signal Qn Final stage flip-flop circuit FFn Output signal A1 to An-1 logic circuit φ1 to φn-1 control signal 3 signal generation circuit 4 delay circuit SL start signal CL clock signal

Claims (2)

[Claims] 1. Flip-flop circuits (FF1 to FFn)
) Are connected in series and each flip-flop circuit (FF2 to F except the flip-flop circuit (FF1) at the first stage is connected.
The clock signal (CL) is input to Fn), the start signal (SL) is input to the first stage flip-flop circuit (FF1), and the output signal (Qn) of the final stage flip-flop circuit (FFn) is input as a clear signal. The flip-flop circuit (FF1) outputs the output signal (Q1 to Qn) obtained by dividing the clock signal (CL) in each flip-flop circuit (FF1 to FFn) and the flip-flop circuit (FF1) other than the first-stage flip-flop circuit (FF1). To the logic circuits (A1 to An-1) provided for the flip-flop circuits (FF2 to FFn) and the output signals (Q2 to Qn) of the flip-flop circuits (FF2 to FFn) and the preceding flip-flop circuits (FF1 to FFn). -1) output signals (Q1 to Qn-1) are respectively input and logically operated, and control signals (φ1 to
The signal generation circuit (2) for generating φn-1) and the control signals (φ1 to φn-1) output from the logic circuits (A1 to An-1) of the signal generation circuit (2) are delayed by different delays. A non-overlap signal generation circuit comprising a delay circuit (3) which delays and outputs the delayed signal. 2. The control signals output through the delay circuit of the non-overlap signal generation circuit according to claim 1 are used as timing control signals for the set operation and the comparison operation of the upper and lower chopper type comparators. Step parallel type A / D converter.