JPH05324700A - Matrix multiplication device - Google Patents

Abstract

PURPOSE:To reduce the number of times of the read-out of the element of a first matrix from a storage device by multiplying each element of the matrix, and accumulating and summing the multiplied result of each element of the same row of the first matrix. CONSTITUTION:One element of the matrix B and the elements of the matrix A are multiplied successively by a multiplication circuit 4, and results are stored in a multiplied result storage circuit 5, and the multiplied result and contents read out of a total added result storage circuit 9 to an added result storage circuit 6 are summed by an addition circuit 7, and after this result is stored temporarily in a temporary added result storage circuit 8, it is written in the total added result storage circuit 9. Thus, the multiplied result stored in the multiplied result storage circuit 5 and the contents read out of the total added result storage circuit 9 to the added result storage circuit 6 are summed by the addition circuit 7, and this result is written in the total added result storage circuit 9 after being stored temporarily in the temporary added result storage circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix multiplication device used in a computer for performing matrix multiplication, and more particularly to a matrix multiplication device suitable for performing matrix multiplication at high speed.

[0002]

2. Description of the Related Art When a computer is used to process scientific and technological calculations, a great deal of processing time is spent in processing matrix calculations. Matrix multiplication frequently appears in this matrix calculation. A computer that performs such matrix multiplication will be described with reference to FIGS. 10 to 13 below.

FIG. 10 is an explanatory diagram showing a notation form of matrix multiplication, and FIG. 11 is an explanatory diagram showing a matrix multiplication procedure by a conventional computer. The matrix A (l × m) and the matrix B (m × n), and the product of the matrix A and the matrix B is the matrix C (l × n), and the elements in the rows i and j of the matrices A, B and C Are respectively aij, bij, and cij, matrix multiplication is expressed in the notation form shown in FIG. When a computer multiplies the matrix A and the matrix B to calculate the matrix C, the data of each element of the matrices A, B, and C is stored in a storage device (memory or the like). To obtain one element cij of the matrix C, as shown in the following expression (1), paying attention to the part of the matrix surrounded by a frame in FIG. 11, the element aik (k = 1 to 1 of the matrix A is focused. m) and the element bk of the matrix B
The elements corresponding to j (k = 1 to m) are respectively multiplied, and the multiplication results are cumulatively added.

Here, since the performance cannot be improved by writing the intermediate result of the cumulative addition back to the storage device each time the calculation is completed, the register in the processing device (processor etc.) is used to perform the cumulative addition. Store the intermediate results. However, since there are restrictions on the registers and the like for storing the intermediate result of cumulative addition, normally, the elements of the matrix C are sequentially added one by one, as described in FIG. 12 and FIG. To seek.

FIG. 12 is a block diagram showing the structure of a conventional processor for performing matrix multiplication. The processing device 111 is
The matrix A storage area 114 and the matrix B storage area 1 for reading and storing the elements 112 of the matrix A and the elements 113 of the matrix B stored in the storage device 110, respectively.
A register group 116 including 15 and the like, and a matrix multiplication of the matrix A and the matrix B using the register group 116, and the result, that is, the element 117 of the matrix C is written by the computing unit 118. It is configured. In the register group 116, a multiplication result storage area 119 for storing the result of multiplication of the element 112 of each matrix A and the element 113 of the matrix B by the arithmetic unit 118, and the cumulative addition of the multiplication result by the arithmetic unit 118. An addition result storage area 120 for storing the result is provided. The operation of the processing apparatus having such a configuration for obtaining one element cij of the matrix C will be described with reference to FIG.

FIG. 13 is a flow chart showing the operation of the matrix multiplication of the processing device in FIG. First, the element aik of the matrix A stored in the storage device is read into the matrix A storage area 114 of the register group 116 of FIG. 12 (step 1201). Next, the element bkj of the matrix B stored in the storage device is read into the matrix B storage area 115 of the register group 116 in FIG. 12 (step 1202). Then, the contents of the matrix A storage area and the contents of the matrix B storage area are multiplied by the arithmetic unit 118 of FIG. 12, and the result is stored in the multiplication result storage area 119 of FIG. 12 (step 1
203). The contents of this multiplication result storage area and (k-1)
The contents of the addition result storage area 120 of FIG. 12, which stores the cumulative addition results up to the first time, are calculated by the arithmetic unit 118 of FIG.
The result of addition is calculated and the result is added area 1 in FIG.
Write back to 20 (step 1204). This process is m
After repeating (step 1205), the content of the addition result storage area 120 of FIG. 12 is written in the storage device 110 of FIG. 12 as the element Cij of the matrix C (step 12).
06).

Then, this processing is performed by the number of elements of the matrix C (l
× n) times are repeated to obtain the entire matrix C. as a result,
In order to obtain the entire matrix C, the matrix elements are read out from the storage device 2m × l × n times, m × l × n multiplication operations, m × l × n addition operations, and l × The process of writing the matrix element to the storage device n times is required. Also, on the computer, the program (software)
Is expanded into an instruction word and stored in the storage device. Therefore, in the above example, (4m + 1) × l from the storage device
It is necessary to read the instruction word × n times. It does not include the number of times the address is updated and the instruction word for controlling the loop count is read.

Thus, there are more accesses to the storage device than there are calculations within the processor. At present, since the processing capacity of the processing device is higher than the data transfer capacity between the storage device and the processing device, the entire processing time is determined by the data transfer capacity between the storage device and the processing device. This is what is called the von Neumann bottleneck.

In order to eliminate this bottleneck, for example, in supercomputers and the like, the concept of vector instructions is adopted. This vector instruction specifies transfer and operation of data to be processed by repeating a predetermined procedure with one instruction. All current supercomputer architectures are characterized by having this vector instruction, which is intended to speed up matrix operations. In addition to this vector instruction, one instruction of a normal computer is called a scalar instruction.

Further, in supercomputers and the like, high-speed arithmetic technology is adopted so as to maximize the data transfer capability with the storage device. High-speed arithmetic techniques for achieving such high speed include pipeline processing and parallel arithmetic. Furthermore, due to recent advances in device technology, a large-capacity storage device (memory, etc.) can be stored inside a processing device (processor, etc.), enabling high-speed data transfer to the storage device and shortening processing time. Is being pursued.

Regarding the speed-up technology of the processing device such as pipeline processing and vector instruction, for example, "Electronic Information and Communication Handbook" edited by The Institute of Electronics, Information and Communication Engineers.
(Published by Ohmsha, Ltd. in 1988), pages 1627 to 1
Page 632.

[0012]

The problem to be solved by the present invention is that, in the conventional technique, when matrix multiplication is performed, the number of times of data transfer between the processing device and the storage device is very large, and the data transfer is It takes a lot of time and cannot perform high-speed processing. The purpose of the present invention is to
These conventional problems are solved, the number of data transfers between the processing device and the storage device is reduced, the pipeline processing technology and the parallel operation technology are easily used together, and high-speed matrix multiplication is enabled. A matrix multiplication device is provided.

[0013]

In order to achieve the above object, the matrix multiplication device of the present invention (1) multiplies two first and second matrices stored in a storage device,
This is a matrix multiplication device that writes this multiplication result in a storage device, and for each element of the first matrix read from the storage device, all multiplication elements of the second matrix corresponding to this element are stored in the storage device. A matrix arithmetic circuit for sequentially reading out, performing each multiplication, accumulating and adding the multiplication results corresponding to each element of the first matrix is provided, and the addition result of the matrix arithmetic circuit is written to a storage device. And
(2) In the matrix multiplication device according to (1) above, the matrix operation circuit includes a first matrix read circuit that reads one element of the first matrix from the storage device, and the first matrix read circuit. A second matrix read circuit that sequentially reads from the storage device all the multiplication elements of the second matrix that correspond to the elements that were read in step 1, and each multiplication element that is sequentially read by the second matrix read circuit; Of the matrix read circuit, and a multiplication circuit for sequentially performing multiplication with one element read by the matrix read circuit, and this multiplication circuit corresponds to each element sequentially read by the first matrix read circuit and the second matrix read circuit. The present invention is characterized by including an adder circuit for sequentially accumulatively adding the calculated multiplication results, and writing the addition result of the adder circuit to a storage device. Also,
(3) In the matrix multiplication device according to (2), the first
The matrix read circuit of 1 is characterized in that one element is sequentially read from the element group of the same column of the first matrix. (4) In the matrix multiplication device according to (2) above,
The first matrix reading circuit is characterized in that one element is sequentially read from the element group in the same row of the first matrix. (5) In the matrix multiplication device according to any one of (2) to (4), the second matrix reading circuit sequentially reads the multiplication elements from the element group in the same column of the second matrix. It is characterized by Also, (6) above (2)
In the matrix multiplication device according to any one of (4) to (4),
The second matrix read circuit is characterized in that the multiplication elements are sequentially read from the element groups in the same row of the second matrix.
(7) In the matrix multiplication device according to any one of (1) to (6), the matrix operation circuit includes a partial addition result storage circuit that stores an addition result, and the partial addition result storage circuit includes: It is characterized in that the stored addition results are sequentially written in the storage device when the matrix multiplication between the corresponding elements is completed. (8) In the matrix multiplication device according to any one of (1) to (6), the matrix operation circuit stores the addition result until the matrix multiplication between all the elements is completed. The present invention is characterized by including a circuit, and when the matrix multiplication between all the elements is completed, all the addition results stored in the full addition result storage circuit are collectively written in the storage device. (9) In the matrix multiplication device according to any one of (1) to (8), at least reading of each element of the second matrix by the matrix calculation circuit from the storage device and multiplication and addition are performed. It is characterized by comprising a control circuit for carrying out pipeline processing of the operation including. Also, (1
0) In the matrix multiplication device according to any one of (1) to (9), the multiplication of the first and second two matrices stored in the storage device is performed in arbitrarily divided units, respectively. , A plurality of matrix operation circuits that are operated in parallel are provided.

[0014]

In the present invention, the matrix multiplication device reads all the multiplication elements of the corresponding second matrix for each element of the first matrix and performs the multiplication of each element of the matrix. Then, the multiplication results of the respective elements in the same column of the first matrix are accumulated and added. This makes it possible to reduce the number of times the elements of the first matrix are read from the storage device. Further, by performing pipeline processing in the matrix multiplication device, matrix multiplication can be processed at high speed. Further, by providing a plurality of matrix operation circuits and using them in parallel, it is possible to further speed up the matrix multiplication process.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a configuration according to the present invention of a matrix multiplication device according to the present invention. The matrix multiplication device 11 of the present embodiment is
The matrix A storage circuit 3 as the second matrix reading circuit of the present invention that reads and stores the element 1a of the matrix A as the second matrix of the present invention, and the storage device 1 as the first matrix of the present invention. The matrix B storage circuit 2 as the first matrix readout circuit of the present invention for reading and storing the element 1b of the matrix B of the above, and the present invention for multiplying the contents of these matrix A storage circuit 3 and matrix B storage circuit 2 The related multiplication circuit 4, the multiplication result storage circuit 5 for storing the result of multiplication by the multiplication circuit 4, and the full addition result according to the present invention for storing the intermediate result of cumulative addition of all the elements of the matrix obtained in the matrix calculation. The storage circuit 9, the addition result storage circuit 6 for reading and storing the contents of the full addition result storage circuit 9, the contents of the addition result storage circuit 6, and the contents of the multiplication result storage circuit 5 are added. The addition circuit 7 according to the present invention, the temporary addition storage circuit 8 for temporarily storing the result of addition by the addition circuit 7 before writing it in the full addition result storage circuit 9, and the overall control of the matrix multiplication device 11. , A control circuit 10 for controlling access to the storage device 1 and controlling pipeline processing according to the present invention. Each circuit except the control circuit 10 constitutes a matrix operation circuit of the present invention, and the element 1c of the matrix C which is the multiplication result is written in the storage device 1 under the control of the control circuit 10.

With such a configuration, the matrix multiplication device 11 of this embodiment can reduce the number of times of reading the elements of the matrix from the storage device 1 and speed up the multiplication of the matrix A and the matrix B. .. The operation of the matrix multiplication device 11 will be described below using the matrix multiplication formulas shown in FIGS.
Calculation of each element of matrix C of matrix multiplication (C = AB) In the above, a case where the element of the j-th column of the matrix C is calculated will be described.

2 to 4 are explanatory views showing one embodiment of the matrix multiplication procedure according to the present invention of the matrix multiplication apparatus in FIG. First, as shown in FIG. 2, for each matrix A, B, and C, pay attention to the portion surrounded by a frame. That is, one element b1j of matrix B and element a of matrix A
k1 (k = 1 to 1) is sequentially multiplied by the multiplication circuit 4 of FIG. 1, and the result is stored in the multiplication result storage circuit 5 of FIG. Then, the multiplication result and the content (initial value “0”) read from the full addition result storage circuit 9 of FIG. 1 to the addition result storage circuit 6 are added by the addition circuit 7 of FIG. Is temporarily stored in the temporary addition result storage circuit 8 of FIG. 1 and then written in the full addition result storage circuit 9 of FIG.

Next, as shown in FIG. 3, each matrix A, B,
For C, pay attention to the part surrounded by the frame. That is,
One element b2j of matrix B and element ak2 (k of matrix A
= 1 to 1) are sequentially multiplied by the multiplication circuit 4 of FIG. 1, and the result is stored in the multiplication result storage circuit 5 of FIG. Then, the multiplication result and the contents read from the full addition result storage circuit 9 of FIG. 1 to the addition result storage circuit 6 are added by the addition circuit 7 of FIG. 1, and the result is temporarily shown in FIG. 1 is stored in the temporary addition result storage circuit 8 and then written in the full addition result storage circuit 9 in FIG.

As described above, in the i-th processing, as shown in FIG. 4, for each matrix A, B, and C, paying attention to the portion surrounded by the frame, one element bij of the matrix B and , The element aki (= j) (k = 1 to 1) of the matrix A is multiplied by the multiplication circuit 4 of FIG.
1 and the result is stored in the multiplication result storage circuit 5 of FIG. 1, and the multiplication result and the contents read from the full addition result storage circuit 9 of FIG. 1 to the addition result storage circuit 6 ((i-
1) cumulative addition result up to the first time) and the addition circuit 7 in FIG.
1 and the result is temporarily stored in the temporary addition result storage circuit 8 of FIG. 1, and then the full addition result storage circuit 9 of FIG.
Write in. Such processing is performed by the number of columns of the matrix C (n
The entire matrix C is obtained repeatedly.

Next, referring to FIG. 5 and FIG. 6, FIG.
The operation of the matrix multiplication device 11 will be described in more detail.
5 and 6 are flowcharts showing an embodiment of the operation of the matrix multiplication apparatus in FIG. 1 according to the present invention. First, as shown in FIG. 5, the element bkj of the matrix B stored in the storage device is read into the matrix B storage circuit 2 of FIG. 1 (step 501). Next, the element aij of the matrix A stored in the storage device is stored in the matrix A storage circuit 3 of FIG.
(Step 502). Then, the contents of the matrix A storage circuit and the contents of the matrix B storage circuit are multiplied by the multiplication circuit 4 in FIG. 1 (step 503). The result of the multiplication is stored in the multiplication result storage circuit 5 of FIG. 1 (step 5).
04).

Next, the (k-1) th addition result is read from the addition result storage circuit 9 of FIG. 1 which stores the cumulative addition result to the addition result storage circuit 6 of FIG. 1 (step 505). The contents of this addition result storage circuit and the contents of the multiplication result storage circuit stored in step 503 are
The addition circuit 7 of FIG. 1 performs addition (step 506). Then, the addition result is written to the temporary addition result storage circuit 8 of FIG. 1 (step 507), and the content of the temporary addition result storage circuit is written to the full addition result storage circuit 9 of FIG. 1 (step 508). ..

Then, as shown in FIG. 6, step 50
The loop of 2 to 508 is repeated 1 times (step 50
9), one element of the matrix B, for example, as shown in FIG. 2, the element b1j is multiplied by all the multiplication elements (a11 to al1) of the matrix A corresponding to this element b1j,
Each element of the matrix C for the element b1j (c1j to clj)
To get In this way, when each element of the matrix C is obtained corresponding to one element of the matrix B, the process returns to step 501 and one element of the next matrix B, for example, the element b2 shown in FIG.
j is read, and then the loop of steps 501 to 508 is repeated l times. As a result, the cumulative result of each element (c1j to clj) of the matrix C for the element b1j and each element (c1j to clj) of the matrix C for the element b2j can be obtained.

The same processing is repeated for the next element of the matrix B, and the loop of steps 501 to 509 is repeated m times (step 510). This gives the matrix B
Of all the elements in one column, for example, each multiplication element (a of the matrix A for each element (b1j to bmj) in FIGS. 2 to 4).
11 to alm) and cumulative addition are performed to obtain all the elements (c1j to clj) in one column of the matrix C. In this way, when all the elements of one column of the matrix C are obtained corresponding to all the elements of one column of the matrix B, the process returns to step 501 and one element of the next column of the matrix B, for example, Figure 2
~ The element b1n shown in FIG. 4 is read.

After that, the loop of steps 502-508 is repeated 1 times and the loop of steps 501-509 is repeated m times, and one of the matrix C corresponds to all elements in the next column of the matrix B. All elements in one row (c1n to cln)
Can be obtained. Then, for each element of the matrix A and the matrix B, the loop of steps 502-508 is repeated 1 times and the loop of steps 501-509 is repeated m times (step 51
1), all the elements (c11 to cln) of the matrix C can be obtained.

In this way, all the elements (c11 to cln) of the matrix C stored in the full addition result storage circuit 9 of FIG.
Is written in the storage device (step 512), and the process ends. As a result, m × (l + 1) × n times of reading of matrix elements from the storage device, m × l × n times of multiplication and addition operations, and 1 × n times of writing of the matrix elements to the storage device. Therefore, the number of times of reading the elements of the matrix from the storage device can be reduced as compared with the conventional technique. That is, conventionally, it is 2m × l × n times, and the difference is 2m × l × n−m × (l + 1) × n = mn (l−
1), and under the condition of l> 1, 2m × l × n−m × (l
+1) × n> 0, therefore 2m × l × n> m × (l + 1)
Xn.

Next, referring to FIG. 7, the above step 50 is performed.
The application of pipeline processing to the processing of 2 to 508 will be described. FIG. 7 is an explanatory diagram showing an embodiment of pipeline processing according to the present invention of the matrix multiplication device in FIG. In the figure, reference numerals 61a to 61c denote a process of reading the matrix A from the storage device to the matrix A storage circuit. In the figure, for example, AMR (k) is the matrix A from the storage device to the matrix A storage circuit. Represents the k-th reading process of
This corresponds to step 502 in FIG. Also, 62a to 62
c is a multiplication of the matrix A and the matrix B, and a writing process of the multiplication result to the multiplication result storage circuit 5 of FIG. 1. For example, in the figure, MUX (k) is the kth matrix A The multiplication and the writing process of the matrix B are shown, which correspond to steps 503 and 504 of FIG. 5, respectively.

Reference numerals 63a to 63c denote a process of reading the cumulative addition result from the full addition result storage circuit 9 of FIG. 1 to the addition result storage circuit 6, for example, ARR (k).
Represents the process of reading the cumulative addition result up to the (k-1) th time and corresponds to step 505 in FIG. Also, 6
Reference numerals 4a to 64c denote addition of the contents of the multiplication result storage circuit 5 and the contents of the addition result storage circuit 6 of FIG. 1, and a writing process of the addition result to the temporary addition result storage circuit 8 of FIG. For example, ADD (k) represents addition and writing processing of the contents of the kth multiplication result storage circuit and the contents of the addition result storage circuit up to (k-1) th time, and respectively.
This corresponds to steps 506 and 507 in FIG. Also, 65
a to 65c are processes for writing the contents of the temporary addition result storage circuit 8 of FIG. 1 to the full addition result storage circuit 9. In the figure, for example, ARW (k) is the kth temporary addition result storage circuit. Represents the process of writing the contents to the full addition result storage circuit,
This corresponds to step 508 in FIG.

As described above, in this embodiment, the processing of steps 502 to 508 in FIG. 5 is divided into three independent processings. As a result, the calculation speed of the matrix multiplication device 11 in FIG. 1 can be increased. Furthermore, by dividing the matrix and performing matrix multiplication,
Since the processing speed can be increased, the following FIG. 8 and FIG.
The configuration and operation of the matrix multiplication device will be described using.

FIG. 8 is an explanatory view showing an embodiment of a matrix division mode according to the present invention. In the present embodiment, the matrix A71 is divided into L in the row direction. Then, for example, when the element group of the I-th matrix aI72 (hatched portion in the drawing) of the divided matrix A71 and the entire matrix B73 (hatched portion) are processed, the matrix is transformed regardless of the elements of other matrices of the matrix A71. C
The element group of the I-th matrix cI74 (hatched portion) of is calculated. Here, as shown in FIG. 9 below, a plurality of matrix operation circuits described in FIG. 1 are provided corresponding to each matrix of the matrix A71, and processing can be performed independently for each matrix. it can.

FIG. 9 is a block diagram showing a second embodiment of the configuration according to the present invention of the matrix multiplication device in FIG. In this embodiment, a plurality of matrix operation circuits 81 to 8 are provided.
4, each of the matrices a1 to aL of the matrix A71 shown in FIG. 8 and the matrix B73 are multiplied in parallel. Thus, the number of divisions of the matrix A (L
), Matrix operation circuits 81 to 84 are provided, and the element group of each matrix a1 to aL obtained by dividing the matrix A71 of FIG.
By causing the matrix operation circuits 81 to 84 to process the whole in parallel, the matrix multiplication can be performed at a higher speed.

As described above with reference to FIGS. 1 to 9, in the matrix multiplication apparatus of the present embodiment, in the matrix multiplication, every one element of one matrix has all the multiplication elements of the other matrix. Multiplication of. This makes it possible to reduce the number of times the matrix elements stored in the storage device are read out. Moreover, the processing time can be shortened by using the pipeline processing technique as the arithmetic technique inside the matrix multiplication device. Further, since the matrix is divided to facilitate parallel processing, the processing speed can be further increased.

The present invention is not limited to the embodiment described with reference to FIGS. For example, in the embodiments described with reference to FIGS. 1 to 6, matrix multiplication and cumulative addition are performed in column units, but they may be performed in row units.
Further, the operation of storing all the results in the full addition result storage circuit and collectively writing the results in the storage device until the matrix multiplication is completed is explained. For example, the partial addition result storage circuit of the present invention is used. Thus, the writing to the recording device may be sequentially performed for each element for which the addition result is completed.

[0033]

According to the present invention, it is possible to reduce the number of times of data transfer between the processing device and the storage device. Furthermore, by adopting the pipeline processing technology and the parallel operation technology, the matrix multiplication can be performed. It becomes possible to process at high speed.

[0034]

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a configuration according to the present invention of a matrix multiplication device according to the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of a matrix multiplication procedure according to the present invention of the matrix multiplication device in FIG.

FIG. 3 is an explanatory diagram showing an embodiment of a matrix multiplication procedure according to the present invention of the matrix multiplication device in FIG.

4 is an explanatory diagram showing an example of a matrix multiplication procedure according to the present invention of the matrix multiplication device in FIG.

5 is a flowchart showing an embodiment of the operation of the matrix multiplication device in FIG. 1 according to the present invention.

FIG. 6 is a flowchart showing an embodiment of the operation of the matrix multiplication device in FIG. 1 according to the present invention.

7 is an explanatory diagram showing an example of pipeline processing according to the present invention of the matrix multiplication device in FIG. 1. FIG.

FIG. 8 is an explanatory diagram showing an example of a matrix division mode according to the present invention.

FIG. 9 is a block diagram showing a second embodiment of the configuration of the matrix multiplication device according to the present invention according to the present invention.

FIG. 10 is an explanatory diagram showing a notation form of matrix multiplication.

FIG. 11 is an explanatory diagram showing a matrix multiplication procedure by a conventional computer.

FIG. 12 is a block diagram showing a configuration of a conventional processing device for performing matrix multiplication.

13 is a flowchart showing an operation of matrix multiplication of the processing device in FIG.

[Explanation of symbols]

1 storage device 1a element of matrix A 1b element of matrix B 1c element of matrix C 2 matrix B storage circuit 3 matrix A storage circuit 4 multiplication circuit 5 multiplication result storage circuit 6 addition result storage circuit 7 addition circuit 8 temporary addition storage circuit 9 Full addition result storage circuit 10 Control circuit 11 Matrix multiplication device 61a to 61c Matrix A reading process 62a to 62c Multiplying matrix A and matrix B and writing process 63a to 63c Cumulative addition result reading process 64a to 64c Of multiplication result storage circuit Addition of contents and contents of addition result storage circuit and write processing 65a to 65c Write processing to full addition result storage circuit 71 Matrix A 72 I-th matrix aI 73 of matrix A 73 B 74 I-th matrix of matrix C 81 -84 matrix operation circuit 110 storage device 111 processing device 112 element of matrix A 113 element of matrix B 1 4 matrix A storage area 115 matrix B storage area 116 of the register group 117 matrix C elements 118 calculator 119 multiplies the result storage area 120 addition result storage area

Claims (10)

[Claims] 1. A matrix multiplication device that multiplies two first and second matrices stored in a storage device and writes the multiplication result into the storage device, wherein the first and second matrices are read from the storage device. For each element of one matrix, all the multiplication elements of the second matrix corresponding to the element are sequentially read from the storage device, and each multiplication is performed to obtain each element of the first matrix. A matrix multiplication device characterized by comprising matrix operation means for accumulating and adding corresponding multiplication results, and writing the addition result of the matrix operation means to the storage device. 2. The matrix multiplication device according to claim 1, wherein the matrix calculation means includes first matrix reading means for reading one element of the first matrix from the storage device, and the first matrix. Second matrix reading means for sequentially reading from the storage device all the multiplication elements of the second matrix corresponding to the elements read by the reading means;
Multiplication means for sequentially multiplying each of the multiplication elements sequentially read by the matrix reading means and one element read by the first matrix reading means, and the first matrix reading means by the multiplication means. And an adding means for sequentially accumulatively adding the respective multiplication results calculated corresponding to the respective elements sequentially read by the second matrix reading means, and the addition results of the adding means are stored in the storage device. A matrix multiplication device characterized by writing. 3. The matrix multiplication device according to claim 2, wherein the first matrix reading means sequentially reads the one element from an element group in the same column of the first matrix. Matrix multiplication device. 4. The matrix multiplication device according to claim 2, wherein the first matrix reading means sequentially reads the one element from an element group in the same row of the first matrix. Matrix multiplication device. 5. The matrix multiplication device according to any one of claims 2 to 4, wherein the second matrix reading means sequentially outputs the multiplication elements from an element group in the same column of the second matrix. A matrix multiplication device characterized in that it is read out to. 6. The matrix multiplication device according to any one of claims 2 to 4, wherein the second matrix reading means sequentially outputs the multiplication elements from an element group in the same row of the second matrix. A matrix multiplication device characterized in that it is read out to. 7. The matrix multiplication device according to claim 1, wherein the matrix calculation means comprises a partial addition result storage means for storing the addition result, and the partial addition result storage means. The matrix multiplication device characterized in that when the addition results stored in [3] are all matrix multiplied between corresponding elements, the addition results are sequentially written to the storage device. 8. The matrix multiplication device according to claim 1, wherein the matrix calculation means stores the addition result until the matrix multiplication between all the elements is completed. Matrix multiplication characterized by comprising storage means and, when the matrix multiplication between all the elements is completed, all the addition results stored in the full addition result storage means are collectively written in the storage device. apparatus. 9. The matrix multiplication device according to claim 1, wherein at least each element of the second matrix is read from the storage device by the matrix calculation means, and the multiplication and A matrix multiplying device comprising a control means for pipeline processing of operations including addition. 10. The matrix multiplication device according to claim 1, wherein the multiplication of the first and second matrices stored in the storage device is an arbitrarily divided unit. The matrix multiplying device is characterized in that a plurality of matrix calculating means are provided in parallel.