JPH05316056A - Voice signal processor - Google Patents

Abstract

PURPOSE:To reduce a ratio of occurrence of noise or click noise with respect to the processing of a voice signal when no flag is detected or error correction is disable while an error check code is added to data and resulting data are sent. CONSTITUTION:A detection section 15 detects number of inputted data whose value is not in existence in the conversion rule based on an output of a conversion circuit 11 and an output of a control section 16 controls a reproduction processing circuit 14 into the output voice mute state when the result of detection indicates a prescribed level or over.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing device, and more particularly, it cannot detect a flag when an error correction signal is added and transmitted in units of a plurality of digital data obtained by sampling an audio signal. The present invention relates to a processing device for processing a voice signal in the case where an error cannot be corrected.

Audio data which is obtained by sampling an analog audio signal which is continuous in time into digital data which is time-discrete, and which includes a plurality of these digital data and an error correction code generated from them as one unit (one frame). It is widely performed in the fields of broadcasting, communication, package media, etc. to sequentially transmit each unit. In this specification, "transmission" means transmission and reception,
Recording and reproduction are included respectively.

In the above-mentioned voice data received or reproduced,
When there are a large number of errors due to the transmission path, or at the moment when the signal disappears, a very loud click sound may be emitted from the speaker. In this case, the listener may feel discomfort. Not only does it give a bad influence on the speaker, etc. Therefore, it is necessary to process the audio signal so that the click sound is not pronounced when there are too many errors in the received or reproduced audio data or when the signal disappears. ..

[0004]

2. Description of the Related Art FIG. 6 shows a block diagram of an example of a conventional audio signal processing apparatus. In the figure, the received or reproduced frame data is supplied to the ternary binary conversion circuit 21. Here, the frame data is, for example, audio data that is audio compression difference data, a specific pattern flag indicating the beginning of a frame, a control signal, an error correction code, and other digital data that constitutes one frame of 1350 bits. Thus, each frame is transmitted at a speed of 1 msec.

Further, this frame data is time-axis compressed in order to form a signal multiplexed with a video signal. At this time, the compression rate is increased by using a method called binary / ternary conversion. In this binary / ternary conversion, continuous binary 3-bit data is converted into ternary data 2 symbols (in the order of the first and second symbols in the following table) according to the conversion table shown in the following table.

[0006]

[Table 1]

The three-value / two-value conversion circuit 21 uses the above-mentioned two-value / three values.
The data whose value has been converted back to the original binary 3 bits is supplied to the error correction processing circuit 23 after the flag synchronization detection circuit 22 synchronously detects the above-mentioned flag, and here, one frame An error correction operation is performed based on a predetermined generator polynomial having each data as a generator element, and when there is an error that cannot be corrected, an interpolation processing flag indicating the possibility of an error is obtained. This complementary processing flag is supplied to the interpolation processing circuit 24 together with the audio data, and the audio data having an uncorrectable error is subjected to interpolation processing such as the average value of normal audio data before and after the error data. The output audio data of the interpolation processing circuit 24 is supplied to the audio PCM reproduction processing unit 25, where it is subjected to pulse code modulation (PCM) reproduction processing to be returned to the original analog audio signal, and then a speaker (not shown). ) Is output.

In the above conventional apparatus, when the error correction processing circuit 23 detects an error that cannot be corrected, the audio PCM reproduction processing circuit 25 is used in addition to the interpolation processing.
In some cases, the data may be muted. Further, in the flag synchronization detection circuit 22,
When the flag cannot be detected, it is determined that synchronization has not been detected, and the output audio signal of the audio processing circuit 25 is muted.

In this way, data that causes noise is remedied even for data that includes uncorrectable errors.

[0010]

However, in the error correction processing in the above-mentioned conventional apparatus, the error correction capacity of the error correction processing circuit 23 is limited, and noise is generated for data including an error higher than the error correction capacity. Preventive effect cannot be expected.

For example, when the package medium is changed from the reproduction state to the stopped state, a correctable error is detected at the moment when the received data is exhausted, although a large number of errors exist. When the state or the situation in which even the existence of an error cannot be detected is intermittent, and these erroneous data are reproduced as voice, they are pronounced as noise or an abnormal sound of a click sound.

This is because the error correction ability of the data of the signal recorded on the package medium is only capable of correcting at most 1 to 3 bits with respect to the data of about 100 bits or detecting the presence of an error. This is because in the above cases where there are more errors, error detection and correction cannot be performed correctly.

Further, the flag synchronization detection circuit 22 cannot detect the flag (frame synchronization is not locked).
In this case, the sound is muted, but it is difficult to deal with the click sound and the like in the situation where the data itself is lost as described above by only adjusting the frame synchronization sensitivity.

Normally, when the flag cannot be detected over several consecutive frames, the mute control is performed with the frame synchronization being in an unlocked state, but the time (number of frames) until it is determined that this frame synchronization is unlocked. This is because the mute control is not applied to the data output to, and the data is output as noise.

The present invention has been made in view of the above points,
By detecting the loss error and performing mute control,
An object of the present invention is to provide an audio signal processing device that solves the above problems.

[0016]

Means of digital audio data obtained by sampling an audio signal (where m is 2
The above integer) is used as a unit to convert into n (n <m) multivalued audio data, and one frame is composed of a plurality of the multivalued audio data and redundant bits such as flags and error correction codes. A conversion circuit 11, a flag synchronization detection circuit 12, and an error correction processing circuit 13 configured to reproduce or receive a digital signal transmitted in frame units and convert the digital signal into m data for every n data. An audio signal processing device for returning to the original audio signal supplied to at least the reproduction processing circuit 14 through at least the detector 15 and the controller 16.

The detection unit 15 detects whether or not the multi-valued voice data having a value that does not exist in the conversion rule for converting the m digital voice data into the n multi-valued voice data is input. When the detecting unit 15 detects the input of multi-valued voice data having a value that does not exist in the conversion rule, the control unit 16 detects
Based on the detection signal, the reproduction processing circuit 14 is controlled to the output audio signal mute state.

[0018]

According to the present invention, when converting m digital audio data into n multivalued audio data for transmission, the multivalued audio data having a value that does not originally exist in the conversion rule is received or When reproduced, the detection unit 15 detects this, and the control unit 16 controls the reproduction processing circuit 14 to the output audio signal mute state based on this detection signal. The mute state can be set in a shorter time than the time required until it is determined that the frame synchronization is unlocked.

[0019]

FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 6 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 2, three values 2
The frame data input to the value conversion circuit 26 is time-division multiplexed within a horizontal (or vertical) blanking period of a band-compressed video signal (MUSE signal) of a high-definition signal, which is received or reproduced from a video disc, for example. Frame data of a digital audio signal, for example, as shown in FIG.
A mode format shown in (B), or FIG.
The format is the B mode shown in (A) and (B).

In the A mode digital data shown in FIGS. 4A and 4B, one frame (1 ms) consists of 1350 bits, of which 16 bits are a frame synchronization signal.
22 bits are control code, 32 bits are range data, 1
28 bits are independent data, 128 bits are error correction code (for example, BCH code), and the remaining 1024 bits are 4-channel audio data (differential compression data).

The audio data is 8 bits each, and is shown in FIG.
In FIG. 4B, the data is transmitted in the horizontal direction, and in FIG. The error correction code is generated with two range data located in the same row, eight pieces of voice data, and one data as generating elements, and upon reception, this is used as a generating element to perform a predetermined operation to generate error data. Correct and restore.

The B-mode digital data shown in FIGS. 5A and 5B has 135 frames per frame (1 ms).
It is 0 bit, and is the same as the A mode in that a 16-bit frame synchronization signal and a 22-bit control code are added to the audio data, but the audio data is 2 channels and 11 bits each. The point is different from A mode. The error correction code in both the A mode and the B mode is usually 8 bits, but in the enhanced mode of the error correction process, it is 15 bits as shown in parentheses. In the normal mode where each of the 16 error correction codes in one frame is 8 bits, the error correction / detection ability is 1 bit error correction (SEC), 2 bit error detection (DED), and 1 bit error can be corrected and restored. Also, an error of 2 bits or more cannot be corrected and restored. On the other hand, in the enhancement mode in which the error correction code is 15 bits each, the error correction / detection capability is 2 bit error correction (DEC) and 3 bit error detection (TED).
An error of more than a bit cannot be corrected and restored.

Since one frame of digital data of such a signal format is band-compressed on the transmitting or recording side, three binary data are converted into two ternary data in advance according to the conversion table described above. (Ie 2
The value is converted into three values). Therefore, the ternary / binary conversion circuit 26 of FIG.
The original binary data is obtained by transmitting and converting into 3 pieces of data (per 2 symbols) and supplies it to the flag synchronization detection circuit 22.

The ternary binary conversion circuit 26 receives the frame data of the first symbol "1" and the second symbol "1" shown as "not applicable" in the conversion table shown in Table 1 above. At that time, the value is not originally present and is in an undefined state (normally this is called an erasure error), but the converted signal at this time is supplied to the detection unit 15.

The detection section 15 and the control section 16 which will be described later, together with the above-mentioned three-value binary conversion circuit 26, have a circuit configuration as shown in FIG. In the figure, the same components as those in FIG. 2 are designated by the same reference numerals. A read-only memory (ROM) 31 that constitutes the three-value binary conversion circuit 21 receives two data of a first symbol and a second symbol at its address input terminals A _{0 to} A ₃ , respectively. Output terminal D _{1 of} 3 bits of binary data converted from 3 values to 2 values according to the value
To D ₃ and, when the data of “1” is input to the address terminals A _{0 to} A ₃ together with the first symbol and the second symbol, the signal of “1” is output from the output terminal D _0. Supply to the counter 34.

Counter 34, first comparator 35 and second
Each of the comparators 36 constitutes the detection unit 15, and the counter 34 is cleared by a clear signal input from the terminal 32. This clear signal is, for example, a vertical sync signal detection signal. Further, the detection signal of the last data in the vertical blanking period of the MUSE signal in which frame data is time-division multiplexed is input to the terminal 33.

The counter 34 is cleared by the vertical synchronizing signal, and data having a value (both 1st and 2nd symbol "1") which should not originally exist in the frame data inputted subsequently to the vertical synchronizing signal is inputted. Then, the signals extracted from the D ₀ terminal of the ROM 31 are counted, and the counted values are supplied to the input terminals A of the comparators 35 and 36, respectively.

The comparator 35 compares the count value with a predetermined first threshold value Th ₁ input to the input terminal B,
When A> B, "1" is output from the output terminal Y. That is, only when undefined data more than the first threshold value Th ₁ is input from the comparator 35 to the frame data, the signal of the logical value “1” is taken out from the output terminal Y and becomes the mute-on signal. It is applied to the J terminal of the JK flip-flop 37.

Here, when a large amount of the above-mentioned undefined data is input, there are cases where the video disk is changed from the reproduction state to the stopped state and fast-forward reproduction is performed. In these cases, the reproduction digital data is Three-level intermediate level (middle point) signal, that is, "1" signal among "0", "1", and "2" can be obtained in large numbers, and digital audio data containing a great number of errors Is obtained. Therefore, in this embodiment, when the amount of undefined data is larger than the first threshold value Th ₁ , it is judged that the digital data (frame data) containing a large number of errors is reproduced, and the logical value of “1” is set. The mute-on signal is output from the comparator 35.

On the other hand, the second comparator 36 compares the output count value of the counter 34 with a predetermined second threshold value Th ₂ (where Th ₂ <Th ₁ ) which is input to the input terminal B. However, when A <B, “1” is output from the output terminal Y. That is, only when the number of undefined data in the frame data is smaller than the second threshold value Th ₂ from the comparator 36, the signal of the logical value “1” is taken out from the output terminal Y and is output as JK as the mute release signal. It is applied to the K terminal of the flip-flop 37.

The JK flip-flop 37 constitutes the above-mentioned control unit 16, and the last digital data detection signal of the vertical blanking time is inputted to the clock terminal via the terminal 33. Further, in the JK flip-flop 37, both output signals of the comparators 35 and 36 in the initial state are both "0", so that the Q output is usually "0". On the other hand, when digital data containing a large number of errors is input, such as at the moment when the video disc is changed from the reproduction state to the stopped state, the count value of the counter 34 is larger than the first threshold value Th _1. Therefore, “1” is output from the output terminal Y of the comparator 35. As a result, the Q output of the JK flip-flop 37 becomes "1" and puts the audio PCM reproduction processing circuit 25 shown in FIG. 2 in the muting state.

Further, in the muting state, when the error of the digital data is reduced, the counter 3
The count value of 4 is the first and second threshold values Th ₁ and Th _2.
The output of the comparator 35 becomes "0", the output of the comparator 36 becomes "1", and when the signal is input from the terminal 33, the Q output of the JK flip-flop 37 becomes "0". Become. As a result, the audio PCM reproduction processing circuit 25 shown in FIG. 2 is released from the audio mute state.

Thus, according to this embodiment, for example, 3
Of the digital audio data transmitted together with the video signal at a rate of 50 frames per field, the mute control can be performed from the digital audio data within one vertical blanking period.
Since it takes several frames to detect the unlocked state by 2, it is possible to determine the presence or absence of mute in a much shorter time, and at the initial stage of the playback process, so the noise output ratio Can be significantly reduced.

[0034]

As described above, according to the present invention, it is possible to detect an abnormality in digital data received or reproduced in a shorter time than detecting that the frame synchronization is unlocked. It has a feature that the ratio of noise and click sound being emitted from the speaker can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a circuit diagram of an embodiment of a main part in FIG.

FIG. 4 is a diagram showing an example of a format of an audio signal.

FIG. 5 is a diagram showing another example of the format of an audio signal.

FIG. 6 is a block diagram of an example of a conventional device.

[Explanation of symbols]

 11 conversion circuit 12,22 flag synchronization detection circuit 13,23 error correction processing circuit 14,25 reproduction processing circuit 15 detection unit 16 control unit 26 three-value binary conversion circuit 31 read only memory (ROM) 34 counter 35,36 Comparator 37 JK flip-flop

Claims (4)

[Claims] 1. Digital audio data obtained by sampling an audio signal is converted into n (where n <m) multivalued audio data in units of m (where m is an integer of 2 or more). , A plurality of multi-valued audio data and a redundant bit such as a flag and an error correction code constitute one frame to reproduce or receive a digital signal transmitted in frame units, and the digital signal is converted into n pieces of data. The original audio signal is supplied to the reproduction processing circuit (14) through at least the conversion circuit (11), the flag synchronization detection circuit (12) and the error correction processing circuit (13) for converting m data each time. In the audio signal processing device for returning, a detection unit for detecting whether or not the multi-valued audio data having a value that does not exist in the conversion rule for converting the m digital audio data into the n multi-valued audio data is input. 15) and when the detection unit (15) detects the input of multi-valued audio data having a value that does not exist in the conversion rule, the reproduction processing circuit (14) outputs the audio signal mute based on the detection signal. An audio signal processing device, comprising: a control unit (16) for controlling the state. 2. The detection unit (15) is configured to convert the multi-valued audio data having a value that does not exist in the conversion rule into the conversion circuit (11).
A counter (34) for counting the number of inputs to the counter, and a first comparator (35) for outputting the detection signal when the output count value of the counter (34) exceeds a predetermined first threshold value. The audio signal processing device according to claim 1, wherein the audio signal processing device comprises: 3. The detection section (15) outputs a second detection signal when the output count value of the counter (34) is less than a second threshold value smaller than the first threshold value. The audio signal processing apparatus according to claim 2, further comprising a second comparator (36) for outputting. 4. The audio signal processing according to claim 3, wherein the control unit (16) cancels the output audio signal mute state of the reproduction processing circuit (14) when the second detection signal is input. apparatus.